diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2018-05-23 11:28:06 +0200 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2018-05-23 11:28:06 +0200 |
| commit | 33f9cdf13af7828952c47a702c5f5244091473f9 (patch) | |
| tree | 366c4859fdb3dd28976d58fc27f99b12562ae8b7 | |
| parent | 6f61f861a60777907a49e314a21ce6b30518df47 (diff) | |
switch to FlexCAN instance 1
Use FlexCAN instance 1 with pinmux ENET1_RD2/ENET1_RD3 as CAN RX/TX.
This pads are available at SODIMM 63/55 and are compatible with
Colibri iMX6/VFxx.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| -rw-r--r-- | examples/imx7_colibri_m4/board.h | 12 | ||||
| -rw-r--r-- | examples/imx7_colibri_m4/pin_mux.c | 18 |
2 files changed, 21 insertions, 9 deletions
diff --git a/examples/imx7_colibri_m4/board.h b/examples/imx7_colibri_m4/board.h index 814b443..0422ae7 100644 --- a/examples/imx7_colibri_m4/board.h +++ b/examples/imx7_colibri_m4/board.h @@ -159,12 +159,12 @@ #define BOARD_I2C_FXOS8700_ADDR (0x1E) /* FlexCAN information for this board */ -#define BOARD_FLEXCAN_RDC_PDAP rdcPdapFlexCan2 -#define BOARD_FLEXCAN_CCM_ROOT ccmRootCan2 -#define BOARD_FLEXCAN_CCM_CCGR ccmCcgrGateCan2 -#define BOARD_FLEXCAN_BASEADDR CAN2 -#define BOARD_FLEXCAN_IRQ_NUM FLEXCAN2_IRQn -#define BOARD_FLEXCAN_HANDLER FLEXCAN2_Handler +#define BOARD_FLEXCAN_RDC_PDAP rdcPdapFlexCan1 +#define BOARD_FLEXCAN_CCM_ROOT ccmRootCan1 +#define BOARD_FLEXCAN_CCM_CCGR ccmCcgrGateCan1 +#define BOARD_FLEXCAN_BASEADDR CAN1 +#define BOARD_FLEXCAN_IRQ_NUM FLEXCAN1_IRQn +#define BOARD_FLEXCAN_HANDLER FLEXCAN1_Handler /* GPC information for this board*/ #define BOARD_GPC_BASEADDR GPC diff --git a/examples/imx7_colibri_m4/pin_mux.c b/examples/imx7_colibri_m4/pin_mux.c index af15e4b..8dc611d 100644 --- a/examples/imx7_colibri_m4/pin_mux.c +++ b/examples/imx7_colibri_m4/pin_mux.c @@ -43,17 +43,29 @@ void configure_flexcan_pins(CAN_Type* base) switch((uint32_t)base) { case CAN1_BASE: - /*CAN 1 is not used in SDB Board*/ + // CAN1_TX SODIMM 63 + IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2 = IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_MUX_MODE(3); + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2 = IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_PE_MASK | + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_PS(3) | + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_DSE(0) | + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_HYS_MASK; + + // CAN1_RX SODIMM 55 + IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3 = IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_MUX_MODE(3); + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3 = IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PE_MASK | + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PS(3) | + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_DSE(0) | + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_HYS_MASK; break; case CAN2_BASE: - // CAN2_TX + // CAN2_TX SODIMM 178 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 = IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_MUX_MODE(3); IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15 = IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_PE_MASK | IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_PS(3) | IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_DSE(0) | IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_HYS_MASK; - // CAN2_RX + // CAN2_RX SODIMM 188 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14 = IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_MUX_MODE(3); IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14 = IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PE_MASK | IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PS(3) | |