ENGR00071509 Fix i.mx31 3stack board can not enter suspend mode by SPI

Fix error gpio inactive interface of SPI. and Enable wakeup interrupt for
RM mode. And add code to skip suspend check for un-attached spi client device

Signed-off-by: Sam Yang <r52096@freescale.com>

5 files changed, 90 insertions, 66 deletions

diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c
index d02368979759..7981d8dac41d 100644
--- a/arch/arm/mach-mx3/clock.c
+++ b/arch/arm/mach-mx3/clock.c
@@ -1160,7 +1160,7 @@ int __init mxc_clocks_init(void)
 
 	/* CCMR stby control */
 	reg = __raw_readl(MXC_CCM_CCMR);
-	reg |= MXC_CCM_CCMR_VSTBY;
+	reg |= MXC_CCM_CCMR_VSTBY | MXC_CCM_CCMR_WAMO;
 	__raw_writel(reg, MXC_CCM_CCMR);
 
 	/* Turn off all possible clocks */
diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-mx3/crm_regs.h
index acce9549df62..11bd36a88e70 100644
--- a/arch/arm/mach-mx3/crm_regs.h
+++ b/arch/arm/mach-mx3/crm_regs.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -60,6 +60,7 @@
 #define MXC_CCM_CCMR_LPM_MASK                   (0x3 << 14)
 #define MXC_CCM_CCMR_FIRS_OFFSET                11
 #define MXC_CCM_CCMR_FIRS_MASK                  (0x3 << 11)
+#define MXC_CCM_CCMR_WAMO                       (1 << 10)
 #define MXC_CCM_CCMR_UPE                        (1 << 9)
 #define MXC_CCM_CCMR_SPE                        (1 << 8)
 #define MXC_CCM_CCMR_MDS                        (1 << 7)
diff --git a/arch/arm/mach-mx3/mx3_3stack_gpio.c b/arch/arm/mach-mx3/mx3_3stack_gpio.c
index eaf9e0f30efb..c8a2fedd49a7 100644
--- a/arch/arm/mach-mx3/mx3_3stack_gpio.c
+++ b/arch/arm/mach-mx3/mx3_3stack_gpio.c
@@ -189,20 +189,21 @@ EXPORT_SYMBOL(gpio_keypad_active);
  */
 void gpio_keypad_inactive(void)
 {
-	mxc_request_iomux(MX31_PIN_KEY_COL0, OUTPUTCONFIG_GPIO,
-			  INPUTCONFIG_GPIO);
-	mxc_request_iomux(MX31_PIN_KEY_COL1, OUTPUTCONFIG_GPIO,
-			  INPUTCONFIG_GPIO);
-	mxc_request_iomux(MX31_PIN_KEY_COL2, OUTPUTCONFIG_GPIO,
-			  INPUTCONFIG_GPIO);
-	mxc_request_iomux(MX31_PIN_KEY_COL3, OUTPUTCONFIG_GPIO,
-			  INPUTCONFIG_GPIO);
-	mxc_request_iomux(MX31_PIN_KEY_ROW0, OUTPUTCONFIG_GPIO,
-			  INPUTCONFIG_GPIO);
-	mxc_request_iomux(MX31_PIN_KEY_ROW1, OUTPUTCONFIG_GPIO,
-			  INPUTCONFIG_GPIO);
-	mxc_request_iomux(MX31_PIN_KEY_ROW2, OUTPUTCONFIG_GPIO,
-			  INPUTCONFIG_GPIO);
+	mxc_request_gpio(MX31_PIN_KEY_COL0);
+	mxc_request_gpio(MX31_PIN_KEY_COL1);
+	mxc_request_gpio(MX31_PIN_KEY_COL2);
+	mxc_request_gpio(MX31_PIN_KEY_COL3);
+	mxc_request_gpio(MX31_PIN_KEY_ROW0);
+	mxc_request_gpio(MX31_PIN_KEY_ROW1);
+	mxc_request_gpio(MX31_PIN_KEY_ROW2);
+
+	mxc_free_iomux(MX31_PIN_KEY_COL0, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO);
+	mxc_free_iomux(MX31_PIN_KEY_COL1, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO);
+	mxc_free_iomux(MX31_PIN_KEY_COL2, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO);
+	mxc_free_iomux(MX31_PIN_KEY_COL3, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO);
+	mxc_free_iomux(MX31_PIN_KEY_ROW0, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO);
+	mxc_free_iomux(MX31_PIN_KEY_ROW1, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO);
+	mxc_free_iomux(MX31_PIN_KEY_ROW2, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO);
 }
 
 EXPORT_SYMBOL(gpio_keypad_inactive);
@@ -298,25 +299,25 @@ void gpio_spi_inactive(int cspi_mod)
 		/* setup GPR for CSPI BB */
 		iomux_config_gpr(MUX_PGP_CSPI_BB, false);
 		/* CSPI1 clock and RDY use full UART ALT1 mode */
-		mxc_free_iomux(MX31_PIN_DSR_DCE1, OUTPUTCONFIG_GPIO,
-			       INPUTCONFIG_GPIO);
-		mxc_free_iomux(MX31_PIN_RI_DCE1, OUTPUTCONFIG_GPIO,
-			       INPUTCONFIG_GPIO);
+		mxc_free_iomux(MX31_PIN_DSR_DCE1, OUTPUTCONFIG_FUNC,
+			       INPUTCONFIG_FUNC);
+		mxc_free_iomux(MX31_PIN_RI_DCE1, OUTPUTCONFIG_FUNC,
+			       INPUTCONFIG_FUNC);
 		break;
 	case 1:
 		/* SPI2 */
-		mxc_request_iomux(MX31_PIN_CSPI2_MISO, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_GPIO);
-		mxc_request_iomux(MX31_PIN_CSPI2_MOSI, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_GPIO);
-		mxc_request_iomux(MX31_PIN_CSPI2_SCLK, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_GPIO);
-		mxc_request_iomux(MX31_PIN_CSPI2_SPI_RDY, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_GPIO);
-		mxc_request_iomux(MX31_PIN_CSPI2_SS0, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_GPIO);
-		mxc_request_iomux(MX31_PIN_CSPI2_SS2, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_GPIO);
+		mxc_free_iomux(MX31_PIN_CSPI2_MISO, OUTPUTCONFIG_FUNC,
+			       INPUTCONFIG_FUNC);
+		mxc_free_iomux(MX31_PIN_CSPI2_MOSI, OUTPUTCONFIG_FUNC,
+			       INPUTCONFIG_FUNC);
+		mxc_free_iomux(MX31_PIN_CSPI2_SCLK, OUTPUTCONFIG_FUNC,
+			       INPUTCONFIG_FUNC);
+		mxc_free_iomux(MX31_PIN_CSPI2_SPI_RDY, OUTPUTCONFIG_FUNC,
+			       INPUTCONFIG_FUNC);
+		mxc_free_iomux(MX31_PIN_CSPI2_SS0, OUTPUTCONFIG_FUNC,
+			       INPUTCONFIG_FUNC);
+		mxc_free_iomux(MX31_PIN_CSPI2_SS2, OUTPUTCONFIG_FUNC,
+			       INPUTCONFIG_FUNC);
 		break;
 	case 2:
 		/* SPI3 */
@@ -367,21 +368,21 @@ void gpio_i2c_inactive(int i2c_num)
 {
 	switch (i2c_num) {
 	case 0:
-		mxc_request_iomux(MX31_PIN_I2C_CLK, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_FUNC);
-		mxc_request_iomux(MX31_PIN_I2C_DAT, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_FUNC);
+		mxc_free_iomux(MX31_PIN_I2C_CLK, OUTPUTCONFIG_FUNC,
+			       INPUTCONFIG_FUNC);
+		mxc_free_iomux(MX31_PIN_I2C_DAT, OUTPUTCONFIG_FUNC,
+			       INPUTCONFIG_FUNC);
 		break;
 	case 1:
-		mxc_request_iomux(MX31_PIN_CSPI2_MOSI, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_ALT1);
-		mxc_request_iomux(MX31_PIN_CSPI2_MISO, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_ALT1);
+		mxc_free_iomux(MX31_PIN_CSPI2_MOSI, OUTPUTCONFIG_FUNC,
+			       INPUTCONFIG_ALT1);
+		mxc_free_iomux(MX31_PIN_CSPI2_MISO, OUTPUTCONFIG_FUNC,
+			       INPUTCONFIG_ALT1);
 		break;
 	case 2:
-		mxc_request_iomux(MX31_PIN_CSPI2_SS2, OUTPUTCONFIG_GPIO,
+		mxc_request_iomux(MX31_PIN_CSPI2_SS2, OUTPUTCONFIG_FUNC,
 				  INPUTCONFIG_ALT1);
-		mxc_request_iomux(MX31_PIN_CSPI2_SCLK, OUTPUTCONFIG_GPIO,
+		mxc_request_iomux(MX31_PIN_CSPI2_SCLK, OUTPUTCONFIG_FUNC,
 				  INPUTCONFIG_ALT1);
 		break;
 	default:
@@ -467,18 +468,25 @@ void gpio_sdhc_inactive(int module)
 {
 	switch (module) {
 	case 0:
-		mxc_request_iomux(MX31_PIN_SD1_CLK, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_NONE);
-		mxc_request_iomux(MX31_PIN_SD1_CMD, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_NONE);
-		mxc_request_iomux(MX31_PIN_SD1_DATA0, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_NONE);
-		mxc_request_iomux(MX31_PIN_SD1_DATA1, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_NONE);
-		mxc_request_iomux(MX31_PIN_SD1_DATA2, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_NONE);
-		mxc_request_iomux(MX31_PIN_SD1_DATA3, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_NONE);
+		mxc_request_gpio(MX31_PIN_SD1_CLK);
+		mxc_request_gpio(MX31_PIN_SD1_CMD);
+		mxc_request_gpio(MX31_PIN_SD1_DATA0);
+		mxc_request_gpio(MX31_PIN_SD1_DATA1);
+		mxc_request_gpio(MX31_PIN_SD1_DATA2);
+		mxc_request_gpio(MX31_PIN_SD1_DATA3);
+
+		mxc_free_iomux(MX31_PIN_SD1_CLK, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_NONE);
+		mxc_free_iomux(MX31_PIN_SD1_CMD, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_NONE);
+		mxc_free_iomux(MX31_PIN_SD1_DATA0, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_NONE);
+		mxc_free_iomux(MX31_PIN_SD1_DATA1, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_NONE);
+		mxc_free_iomux(MX31_PIN_SD1_DATA2, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_NONE);
+		mxc_free_iomux(MX31_PIN_SD1_DATA3, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_NONE);
 
 		mxc_iomux_set_pad(MX31_PIN_SD1_CLK,
 				  (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
@@ -498,18 +506,18 @@ void gpio_sdhc_inactive(int module)
 		break;
 	case 1:
 		/* TODO:what are the pins for SDHC2? */
-		mxc_request_iomux(MX31_PIN_PC_CD2_B, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_NONE);
-		mxc_request_iomux(MX31_PIN_PC_CD1_B, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_NONE);
-		mxc_request_iomux(MX31_PIN_PC_WAIT_B, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_NONE);
-		mxc_request_iomux(MX31_PIN_PC_READY, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_NONE);
-		mxc_request_iomux(MX31_PIN_PC_VS1, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_NONE);
-		mxc_request_iomux(MX31_PIN_PC_PWRON, OUTPUTCONFIG_GPIO,
-				  INPUTCONFIG_NONE);
+		mxc_free_iomux(MX31_PIN_PC_CD2_B, OUTPUTCONFIG_FUNC,
+			       INPUTCONFIG_NONE);
+		mxc_free_iomux(MX31_PIN_PC_CD1_B, OUTPUTCONFIG_FUNC,
+			       INPUTCONFIG_NONE);
+		mxc_free_iomux(MX31_PIN_PC_WAIT_B, OUTPUTCONFIG_FUNC,
+			       INPUTCONFIG_NONE);
+		mxc_free_iomux(MX31_PIN_PC_READY, OUTPUTCONFIG_FUNC,
+			       INPUTCONFIG_NONE);
+		mxc_free_iomux(MX31_PIN_PC_VS1, OUTPUTCONFIG_FUNC,
+			       INPUTCONFIG_NONE);
+		mxc_free_iomux(MX31_PIN_PC_PWRON, OUTPUTCONFIG_FUNC,
+			       INPUTCONFIG_NONE);
 		break;
 	default:
 		break;
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index d8872b3e46d9..570aac57b787 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -1098,6 +1098,9 @@ static int suspend_devices(struct device *dev, void *pm_message)
 {
 	pm_message_t *state = pm_message;
 
+	if (!dev->driver)
+		return 0;
+
 	if (dev->power.power_state.event != state->event) {
 		dev_warn(dev, "mismatch in pm state request\n");
 		return -1;
diff --git a/drivers/video/mxc/mxcfb_epson_vga.c b/drivers/video/mxc/mxcfb_epson_vga.c
index 6622deb5f1f1..0ef6bb8ca032 100644
--- a/drivers/video/mxc/mxcfb_epson_vga.c
+++ b/drivers/video/mxc/mxcfb_epson_vga.c
@@ -166,6 +166,16 @@ static int __devexit lcd_spi_remove(struct spi_device *spi)
 	return 0;
 }
 
+static int lcd_suspend(struct spi_device *spi, pm_message_t message)
+{
+	return 0;
+}
+
+static int lcd_resume(struct spi_device *spi)
+{
+	return 0;
+}
+
 /*!
  * spi driver structure for LTV350QV
  */
@@ -177,6 +187,8 @@ static struct spi_driver lcd_spi_dev_driver = {
 		   },
 	.probe = lcd_spi_probe,
 	.remove = __devexit_p(lcd_spi_remove),
+	.suspend = lcd_suspend,
+	.resume = lcd_resume,
 };
 
 #define param(x) ((x) | 0x100)