diff options
| author | Wayne Zou <b36644@freescale.com> | 2012-04-27 14:31:55 +0800 |
|---|---|---|
| committer | Wayne Zou <b36644@freescale.com> | 2012-04-28 13:41:48 +0800 |
| commit | e5b03acb5325b30a1b53dcc1b921ea75eea83c81 (patch) | |
| tree | 55bac884c48af2b3906fe2b57658d338d8ea664f | |
| parent | cb2ad24cd3d5b58acdf11455b79c34f734109345 (diff) | |
ENGR00181191 MX6: set ipu2_clk parent from pll2_pfd_400M
On mx6dl, set ipu2_clk's parent from pll2_pfd_400M.
On mx6q, ipu2_clk's parent from mmdc_ch0_axi_clk, and it is 264MHz by default.
Signed-off-by: Wayne Zou <b36644@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx6/clock.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 41b74f5bbfd2..9d69f5d0fb15 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -5280,10 +5280,6 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, /* S/PDIF */ clk_set_parent(&spdif0_clk[0], &pll3_pfd_454M); - /* pxp & epdc */ - clk_set_parent(&ipu2_clk, &pll2_pfd_400M); - clk_set_rate(&ipu2_clk, 200000000); - if (mx6q_revision() == IMX_CHIP_REVISION_1_0) { gpt_clk[0].parent = &ipg_perclk; gpt_clk[0].get_rate = NULL; @@ -5294,6 +5290,9 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, } if (cpu_is_mx6dl()) { + /* pxp & epdc */ + clk_set_parent(&ipu2_clk, &pll2_pfd_400M); + clk_set_rate(&ipu2_clk, 200000000); if (epdc_enabled) clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk); else |