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authorSerah Peterson <speterson@phytec.com>2013-06-24 14:09:25 -0700
committerAnthony Felice <tony.felice@timesys.com>2013-08-28 18:26:23 -0400
commit67df987a2664c54a350591df00ff4dc82b8f5dff (patch)
tree1c37b0e06a1882806dfeddc6285d704f24bfcbe3
parentf55b7be24bf255c248d2a488f3404f1d908d03a6 (diff)
pcm052: fec1: support added for ETH1
Signed-off-by: Serah Peterson <speterson@phytec.com>
-rw-r--r--arch/arm/mach-mvf/board-pcm052.c28
-rw-r--r--[-rwxr-xr-x]drivers/net/fec.c12
2 files changed, 39 insertions, 1 deletions
diff --git a/arch/arm/mach-mvf/board-pcm052.c b/arch/arm/mach-mvf/board-pcm052.c
index 50b2eead4eb7..27e737158ae2 100644
--- a/arch/arm/mach-mvf/board-pcm052.c
+++ b/arch/arm/mach-mvf/board-pcm052.c
@@ -47,6 +47,7 @@
#include <linux/pmic_status.h>
#include <linux/ipu.h>
#include <linux/mxcfb.h>
+#include <linux/phy.h>
#include <linux/pwm_backlight.h>
#include <linux/leds_pwm.h>
#include <linux/fec.h>
@@ -87,6 +88,11 @@
#define PCM052_SD1_CD 85
#define PCM052_TS_IRQ 32
+/* FEC1 definitions */
+#define FEC1_BUS_ID "2:01" // SP: BUS_ID for ETH1
+#define KSZ8051_PHY_CTRL2 0x1F // SP: PHY Ctrl2 reg addr
+#define KSZ8051_50MHZ_CLK_MODE (1 << 7) // SP: PHY Ctrl2 reg val for 50 MHz clk
+
#ifdef PCM952_REV0
#undef PCM952_REV0
#endif
@@ -274,6 +280,17 @@ static struct switch_platform_data switch_data __initdata = {
.phy = PHY_INTERFACE_MODE_RMII,
};
+/* SP: Additional configuration is required to setup ETH1 on the phyCORE-Vybrid
+ * (1) Set to 50 MHz (enable bit 7 in the PHY control 2 register)
+ - Write: reg - 0x1F; data - (0x1 << 7)
+*/
+static int mvf_fec1_phy_fixup(struct phy_device *phydev){
+ int regval;
+ regval = phy_read(phydev, KSZ8051_PHY_CTRL2);
+ regval |= KSZ8051_50MHZ_CLK_MODE;
+ phy_write(phydev, KSZ8051_PHY_CTRL2, regval);
+}
+
static int pcm052_spi_cs[] = {
41,
};
@@ -412,10 +429,21 @@ static const struct esdhc_platform_data pcm052_sd1_data __initconst = {
.wp_gpio = -1,
};
+/* SP: Replicate the AM335x solution for phy_fixup
+ * - make the required changes for FEC1/ETH1 - see 'mvf_fec1_phy_fixup'
+ */
+static void pcm052_setup(struct memory_accessor *mem_acc, void *context)
+{
+ phy_register_fixup_for_id(FEC1_BUS_ID, mvf_fec1_phy_fixup);
+ return;
+}
+
static struct at24_platform_data board_eeprom = {
.byte_len = 4096,
.page_size = 32,
.flags = AT24_FLAG_ADDR16,
+ .setup = pcm052_setup, // SP: added to replicate the am335x board file
+ .context = (void *)NULL, // SP: added to replicate the am335x board file
};
static struct stmpe_gpio_platform_data pba_gpio_stm_data = {
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index 73f3f2b49a61..2deace6cd4c3 100755..100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -869,7 +869,9 @@ static int fec_enet_mii_probe(struct net_device *ndev)
static int fec_enet_mii_init(struct platform_device *pdev)
{
+#if !(defined(CONFIG_MACH_PCM052) || defined(CONFIG_MACH_PCL052))
static struct mii_bus *fec0_mii_bus;
+#endif
struct net_device *ndev = platform_get_drvdata(pdev);
struct fec_enet_private *fep = netdev_priv(ndev);
const struct platform_device_id *id_entry =
@@ -892,11 +894,18 @@ static int fec_enet_mii_init(struct platform_device *pdev)
* mdio interface in board design, and need to be configured by
* fec0 mii_bus.
*/
+ /*
+ * SP: Modified for dual fec interfaces on the phyCORE-Vybrid
+ * - fec0 and fec1 must be on different mdio interfaces
+ * - configured by fep -> mii_bus instead of fec0 mii_bus
+ */
+#if !(defined(CONFIG_MACH_PCM052) || defined(CONFIG_MACH_PCL052))
if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && pdev->id) {
/* fec1 uses fec0 mii_bus */
fep->mii_bus = fec0_mii_bus;
return 0;
}
+#endif
fep->mii_timeout = 0;
@@ -905,7 +914,6 @@ static int fec_enet_mii_init(struct platform_device *pdev)
*/
fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk),
(FEC_ENET_MII_CLK << 2)) << 1;
-
fep->phy_speed |= 0x10;
/* set hold time to 2 internal clock cycle */
@@ -940,9 +948,11 @@ static int fec_enet_mii_init(struct platform_device *pdev)
if (mdiobus_register(fep->mii_bus))
goto err_out_free_mdio_irq;
+#if !(defined(CONFIG_MACH_PCM052) || defined(CONFIG_MACH_PCL052))
/* save fec0 mii_bus */
if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
fec0_mii_bus = fep->mii_bus;
+#endif
return 0;