ENGR00181401,ENGR00181396-1: Add USB OTG controller support for MVF platform

OTG1 acts as gadget and OTG2 acts as host on TWR-MVF600 board.

Signed-off-by: Jingchang Lu <b35083@freescale.com>

8 files changed, 1259 insertions, 4 deletions

diff --git a/arch/arm/mach-mvf/usb.h b/arch/arm/mach-mvf/usb.h
new file mode 100644
index 000000000000..14d9bff94bf0
--- /dev/null
+++ b/arch/arm/mach-mvf/usb.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <mach/common.h>
+
+extern int usbotg_init(struct platform_device *pdev);
+extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata);
+extern int usbotg2_init(struct platform_device *pdev);
+extern void usbotg2_uninit(struct fsl_usb2_platform_data *pdata);
+extern struct platform_device *host_pdev_register(struct resource *res,
+		  int n_res, struct fsl_usb2_platform_data *config);
+
+extern int fsl_usb_host_init(struct platform_device *pdev);
+extern void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata);
+extern int gpio_usbotg_utmi_active(void);
+extern void gpio_usbotg_utmi_inactive(void);
+
+extern void __init mvf_usb_dr_init(void);
+extern void __init mvf_usb_dr2_init(void);
+extern void __init mvf_usb_h1_init(void);
+
+typedef void (*driver_vbus_func)(bool);
+extern void mvf_set_host1_vbus_func(driver_vbus_func);
+extern void mvf_set_otghost_vbus_func(driver_vbus_func);
+extern struct platform_device anatop_thermal_device;
+extern struct platform_device mvf_usbdr_otg_device;
+extern struct platform_device mvf_usbdr_udc_device;
+extern struct platform_device mvf_usbdr_host_device;
+extern struct platform_device mvf_usbdr_wakeup_device;
+extern struct platform_device mvf_usbh1_device;
+extern struct platform_device mvf_usbh1_wakeup_device;
+
+/*
+ * Used to set pdata->operating_mode before registering the platform_device.
+ * If OTG is configured, the controller operates in OTG mode,
+ * otherwise it's either host or device.
+ */
+#ifdef CONFIG_USB_OTG
+#define DR_UDC_MODE	FSL_USB2_DR_OTG
+#define DR_HOST_MODE	FSL_USB2_DR_OTG
+#else
+#define DR_UDC_MODE	FSL_USB2_DR_DEVICE
+#define DR_HOST_MODE	FSL_USB2_DR_HOST
+#endif
+
+extern void __iomem *imx_otg_base;
diff --git a/arch/arm/mach-mvf/usb_dr.c b/arch/arm/mach-mvf/usb_dr.c
new file mode 100644
index 000000000000..2467acc1bf28
--- /dev/null
+++ b/arch/arm/mach-mvf/usb_dr.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <mach/arc_otg.h>
+#include <mach/hardware.h>
+#include <mach/clock.h>
+#include "devices-mvf.h"
+#include "crm_regs.h"
+#include "regs-anadig.h"
+#include "usb.h"
+
+static int usbotg_init_ext(struct platform_device *pdev);
+static void usbotg_uninit_ext(struct platform_device *pdev);
+static void usbotg_clock_gate(bool on);
+static void _dr_discharge_line(bool enable);
+
+/* The usb_phy0_clk do not have enable/disable function at clock.c
+ * and PLL output for usb0's phy should be always enabled.
+ * usb_phy0_clk only stands for usb uses pll3 as its parent.
+ */
+static struct clk *usb_phy0_clk;
+static u8 otg_used;
+
+/* Beginning of Common operation for DR port */
+
+/*
+ * platform data structs
+ * - Which one to use is determined by CONFIG options in usb.h
+ * - operating_mode plugged at run time
+ */
+static struct fsl_usb2_platform_data dr_utmi_config = {
+	.name              = "DR",
+	.init              = usbotg_init_ext,
+	.exit              = usbotg_uninit_ext,
+	.phy_mode          = FSL_USB2_PHY_UTMI_WIDE,
+	.power_budget      = 500,		/* 500 mA max power */
+	.usb_clock_for_pm  = usbotg_clock_gate,
+	.transceiver       = "utmi",
+	.phy_regs = MVF_USBPHY0_BASE_ADDR,
+	.dr_discharge_line = _dr_discharge_line,
+};
+
+static void usbotg_internal_phy_clock_gate(bool on)
+{
+	u32 reg;
+
+	void __iomem *phy_reg = MVF_IO_ADDRESS(MVF_USBPHY0_BASE_ADDR);
+	reg = __raw_readl(phy_reg + HW_USBPHY_CTRL);
+
+	if (on)
+		reg &= ~BM_USBPHY_CTRL_CLKGATE;
+	else
+		reg |= BM_USBPHY_CTRL_CLKGATE;
+
+	__raw_writel(reg, phy_reg + HW_USBPHY_CTRL);
+}
+
+static int usb_phy_enable(struct fsl_usb2_platform_data *pdata)
+{
+	u32 tmp;
+	void __iomem *phy_reg = MVF_IO_ADDRESS(MVF_USBPHY0_BASE_ADDR);
+	void __iomem *phy_ctrl;
+
+	/* Stop then Reset */
+	UOG_USBCMD &= ~UCMD_RUN_STOP;
+	while (UOG_USBCMD & UCMD_RUN_STOP)
+		;
+
+	UOG_USBCMD |= UCMD_RESET;
+	while ((UOG_USBCMD) & (UCMD_RESET))
+		;
+	/* Reset USBPHY module */
+	phy_ctrl = phy_reg + HW_USBPHY_CTRL;
+	tmp = __raw_readl(phy_ctrl);
+	tmp |= BM_USBPHY_CTRL_SFTRST;
+	__raw_writel(tmp, phy_ctrl);
+	udelay(10);
+
+	/* Remove CLKGATE and SFTRST */
+	tmp = __raw_readl(phy_ctrl);
+	tmp &= ~(BM_USBPHY_CTRL_CLKGATE | BM_USBPHY_CTRL_SFTRST);
+	__raw_writel(tmp, phy_ctrl);
+	udelay(10);
+
+	/* Power up the PHY */
+	__raw_writel(0, phy_reg + HW_USBPHY_PWD);
+
+	return 0;
+}
+/* Notes: configure USB clock*/
+static int usbotg_init_ext(struct platform_device *pdev)
+{
+	struct clk *usb_clk;
+	u32 ret;
+
+	usb_clk = clk_get(NULL, "mvf-usb.0");
+	clk_enable(usb_clk);
+	usb_phy0_clk = usb_clk;
+
+	ret = usbotg_init(pdev);
+	if (ret) {
+		printk(KERN_ERR "otg init fails......\n");
+		return ret;
+	}
+	if (!otg_used) {
+		usbotg_internal_phy_clock_gate(true);
+		usb_phy_enable(pdev->dev.platform_data);
+		/*
+		 * after the phy reset,can not read the value for id/vbus at
+		 * the register of otgsc ,cannot  read at once ,need delay 3 ms
+		 */
+		mdelay(3);
+	}
+	otg_used++;
+
+	return ret;
+}
+
+static void usbotg_uninit_ext(struct platform_device *pdev)
+{
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+
+	clk_disable(usb_phy0_clk);
+	clk_put(usb_phy0_clk);
+
+	usbotg_uninit(pdata);
+	otg_used--;
+}
+
+static void usbotg_clock_gate(bool on)
+{
+	pr_debug("%s: on is %d\n", __func__, on);
+	if (on)
+		clk_enable(usb_phy0_clk);
+	else
+		clk_disable(usb_phy0_clk);
+}
+/*
+void mvf_set_otghost_vbus_func(driver_vbus_func driver_vbus)
+{
+	dr_utmi_config.platform_driver_vbus = driver_vbus;
+}
+*/
+static void _dr_discharge_line(bool enable)
+{
+	void __iomem *phy_reg = MVF_IO_ADDRESS(MVF_USBPHY0_BASE_ADDR);
+	if (enable) {
+		__raw_writel(BF_USBPHY_DEBUG_ENHSTPULLDOWN(0x3),
+				phy_reg + HW_USBPHY_DEBUG_SET);
+		__raw_writel(BF_USBPHY_DEBUG_HSTPULLDOWN(0x3),
+				phy_reg + HW_USBPHY_DEBUG_SET);
+	} else {
+		__raw_writel(BF_USBPHY_DEBUG_ENHSTPULLDOWN(0x3),
+				phy_reg + HW_USBPHY_DEBUG_CLR);
+		__raw_writel(BF_USBPHY_DEBUG_HSTPULLDOWN(0x3),
+				phy_reg + HW_USBPHY_DEBUG_CLR);
+	}
+
+}
+
+/* Below two macros are used at otg mode to indicate usb mode*/
+#define ENABLED_BY_HOST   (0x1 << 0)
+#define ENABLED_BY_DEVICE (0x1 << 1)
+
+#ifdef CONFIG_USB_EHCI_ARC_OTG
+#endif /* CONFIG_USB_EHCI_ARC_OTG */
+
+
+#ifdef CONFIG_USB_GADGET_ARC
+#endif /* CONFIG_USB_GADGET_ARC */
+
+void __init mvf_usb_dr_init(void)
+{
+	struct platform_device *pdev;
+	u32 reg;
+#ifdef CONFIG_USB_GADGET_ARC
+	dr_utmi_config.operating_mode = DR_UDC_MODE;
+	dr_utmi_config.platform_suspend = NULL;
+	dr_utmi_config.platform_resume  = NULL;
+
+	pdev = mvf_add_fsl_usb2_udc(&dr_utmi_config);
+
+	__raw_writel(((0x01 << 30) | 0x2), ANADIG_USB1_MISC);
+
+	__raw_writel(0x00000894, USBPHY1_CTRL);
+	udelay(10);
+
+	__raw_writel(0x0, USBPHY1_PWD);
+	__raw_writel(0x1, USBPHY1_IP);
+	udelay(20);
+	__raw_writel(0x7, USBPHY1_IP);
+
+	reg = __raw_readl(USBPHY1_DEBUG);
+	reg &= ~0x40000000; /* clear gate clock */
+	__raw_writel(reg, USBPHY1_DEBUG);
+
+	__raw_writel(0x10000007, USBPHY1_TX);
+	reg = __raw_readl(USBPHY1_CTRL);
+	reg |= ((0xD1 << 11) | 0x6);
+	__raw_writel(reg, USBPHY1_CTRL);
+
+	reg = __raw_readl(ANADIG_USB1_VBUS_DETECT);
+	reg |= 0xE8;
+	__raw_writel(reg, ANADIG_USB1_VBUS_DETECT);
+	__raw_writel(0x001c0000, ANADIG_USB1_CHRG_DETECT);
+#endif
+
+}
diff --git a/arch/arm/mach-mvf/usb_dr2.c b/arch/arm/mach-mvf/usb_dr2.c
new file mode 100644
index 000000000000..d26cfde125e0
--- /dev/null
+++ b/arch/arm/mach-mvf/usb_dr2.c
@@ -0,0 +1,285 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <mach/arc_otg.h>
+#include <mach/hardware.h>
+#include <mach/clock.h>
+#include "devices-mvf.h"
+#include "crm_regs.h"
+#include "regs-anadig.h"
+#include "usb.h"
+
+static int usbotg2_init_ext(struct platform_device *pdev);
+static void usbotg2_uninit_ext(struct platform_device *pdev);
+static void usbotg_clock_gate(bool on);
+static void _dr_discharge_line(bool enable);
+
+static struct clk *usb_phy1_clk;
+static u8 otg2_used;
+
+/* Beginning of Common operation for DR port */
+
+/*
+ * platform data structs
+ * - Which one to use is determined by CONFIG options in usb.h
+ * - operating_mode plugged at run time
+ */
+static struct fsl_usb2_platform_data dr_utmi_config = {
+	.name              = "DR",
+	.init              = usbotg2_init_ext,
+	.exit              = usbotg2_uninit_ext,
+	.phy_mode          = FSL_USB2_PHY_UTMI_WIDE,
+	.power_budget      = 500,		/* 500 mA max power */
+	.usb_clock_for_pm  = usbotg_clock_gate,
+	.transceiver       = "utmi",
+	.phy_regs = MVF_USBPHY1_BASE_ADDR,
+	.dr_discharge_line = _dr_discharge_line,
+};
+
+static void usbotg_internal_phy_clock_gate(bool on)
+{
+	void __iomem *phy_reg = MVF_IO_ADDRESS(MVF_USBPHY1_BASE_ADDR);
+
+	if (on)
+		__raw_writel(BM_USBPHY_CTRL_CLKGATE,
+				phy_reg + HW_USBPHY_CTRL_CLR);
+	else
+		__raw_writel(BM_USBPHY_CTRL_CLKGATE,
+				phy_reg + HW_USBPHY_CTRL_SET);
+
+}
+
+static int usb_phy_enable(struct fsl_usb2_platform_data *pdata)
+{
+	u32 tmp;
+	void __iomem *phy_reg = MVF_IO_ADDRESS(MVF_USBPHY1_BASE_ADDR);
+	void __iomem *phy_ctrl;
+
+	/* Stop then Reset */
+	UOG2_USBCMD &= ~UCMD_RUN_STOP;
+	while (UOG2_USBCMD & UCMD_RUN_STOP)
+		;
+
+	UOG2_USBCMD |= UCMD_RESET;
+	while ((UOG2_USBCMD) & (UCMD_RESET))
+		;
+	/* Reset USBPHY module */
+	phy_ctrl = phy_reg + HW_USBPHY_CTRL;
+	tmp = __raw_readl(phy_ctrl);
+	tmp |= BM_USBPHY_CTRL_SFTRST;
+	__raw_writel(tmp, phy_ctrl);
+	udelay(10);
+
+	/* Remove CLKGATE and SFTRST */
+	tmp = __raw_readl(phy_ctrl);
+	tmp &= ~(BM_USBPHY_CTRL_CLKGATE | BM_USBPHY_CTRL_SFTRST);
+	__raw_writel(tmp, phy_ctrl);
+	udelay(10);
+
+	/* Power up the PHY */
+	__raw_writel(0, phy_reg + HW_USBPHY_PWD);
+	if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
+			(pdata->operating_mode == FSL_USB2_DR_OTG)) {
+		/* enable FS/LS device */
+		__raw_writel(
+		BM_USBPHY_CTRL_ENUTMILEVEL2 | BM_USBPHY_CTRL_ENUTMILEVEL3,
+				phy_reg + HW_USBPHY_CTRL_SET);
+	}
+
+	return 0;
+}
+/* Notes: configure USB clock*/
+static int usbotg2_init_ext(struct platform_device *pdev)
+{
+	struct clk *usb_clk;
+	u32 ret;
+
+	usb_clk = clk_get(NULL, "mvf-usb.1");
+	clk_enable(usb_clk);
+	usb_phy1_clk = usb_clk;
+
+	ret = usbotg2_init(pdev);
+	if (ret) {
+		printk(KERN_ERR "otg init fails......\n");
+		return ret;
+	}
+	if (!otg2_used) {
+		usbotg_internal_phy_clock_gate(true);
+		usb_phy_enable(pdev->dev.platform_data);
+		/*
+		 * after the phy reset,can't read the value for id/vbus at
+		 * the register of otgsc at once ,need delay 3 ms
+		 */
+		mdelay(3);
+	}
+	otg2_used++;
+
+	return ret;
+}
+
+static void usbotg2_uninit_ext(struct platform_device *pdev)
+{
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+
+	clk_disable(usb_phy1_clk);
+	clk_put(usb_phy1_clk);
+
+	usbotg2_uninit(pdata);
+	otg2_used--;
+}
+
+static void usbotg_clock_gate(bool on)
+{
+
+	if (on)
+		clk_enable(usb_phy1_clk);
+	else
+		clk_disable(usb_phy1_clk);
+
+}
+
+static void _dr_discharge_line(bool enable)
+{
+	void __iomem *phy_reg = MVF_IO_ADDRESS(MVF_USBPHY1_BASE_ADDR);
+
+	if (enable) {
+		__raw_writel(BF_USBPHY_DEBUG_ENHSTPULLDOWN(0x3),
+				phy_reg + HW_USBPHY_DEBUG_SET);
+		__raw_writel(BF_USBPHY_DEBUG_HSTPULLDOWN(0x3),
+				phy_reg + HW_USBPHY_DEBUG_SET);
+	} else {
+		__raw_writel(BF_USBPHY_DEBUG_ENHSTPULLDOWN(0x3),
+				phy_reg + HW_USBPHY_DEBUG_CLR);
+		__raw_writel(BF_USBPHY_DEBUG_HSTPULLDOWN(0x3),
+				phy_reg + HW_USBPHY_DEBUG_CLR);
+	}
+
+}
+
+/* Below two macros are used at otg mode to indicate usb mode*/
+#define ENABLED_BY_HOST   (0x1 << 0)
+#define ENABLED_BY_DEVICE (0x1 << 1)
+/* End of Common operation for DR port */
+
+#ifdef CONFIG_USB_EHCI_ARC_OTG
+/* Beginning of host related operation for DR port */
+static void _host_platform_suspend(struct fsl_usb2_platform_data *pdata)
+{
+	void __iomem *phy_reg = MVF_IO_ADDRESS(MVF_USBPHY1_BASE_ADDR);
+	u32 tmp;
+
+	tmp = (BM_USBPHY_PWD_TXPWDFS
+		| BM_USBPHY_PWD_TXPWDIBIAS
+		| BM_USBPHY_PWD_TXPWDV2I
+		| BM_USBPHY_PWD_RXPWDENV
+		| BM_USBPHY_PWD_RXPWD1PT1
+		| BM_USBPHY_PWD_RXPWDDIFF
+		| BM_USBPHY_PWD_RXPWDRX);
+	__raw_writel(tmp, phy_reg + HW_USBPHY_PWD_SET);
+}
+
+static void _host_platform_resume(struct fsl_usb2_platform_data *pdata)
+{
+	void __iomem *phy_reg = MVF_IO_ADDRESS(MVF_USBPHY1_BASE_ADDR);
+	u32 tmp;
+
+	tmp = (BM_USBPHY_PWD_TXPWDFS
+		| BM_USBPHY_PWD_TXPWDIBIAS
+		| BM_USBPHY_PWD_TXPWDV2I
+		| BM_USBPHY_PWD_RXPWDENV
+		| BM_USBPHY_PWD_RXPWD1PT1
+		| BM_USBPHY_PWD_RXPWDDIFF
+		| BM_USBPHY_PWD_RXPWDRX);
+	__raw_writel(tmp, phy_reg + HW_USBPHY_PWD_CLR);
+}
+
+/* End of host related operation for DR port */
+#endif /* CONFIG_USB_EHCI_ARC_OTG */
+
+
+void __init mvf_usb_dr2_init(void)
+{
+	struct platform_device *pdev;
+	u32 reg;
+
+#ifdef CONFIG_USB_EHCI_ARC_OTG
+	dr_utmi_config.operating_mode = DR_HOST_MODE;
+	dr_utmi_config.platform_suspend = _host_platform_suspend;
+	dr_utmi_config.platform_resume  = _host_platform_resume;
+
+	pdev = mvf_add_fsl_ehci_otg(&dr_utmi_config);
+
+	__raw_writel(0x0220C802, USBPHY2_CTRL);
+	udelay(20);
+
+	__raw_writel(0x0, USBPHY2_PWD);
+
+	reg = __raw_readl(USBPHY2_DEBUG);
+	reg &= ~0x40000000; /* clear clock gate */
+	__raw_writel(reg, USBPHY2_DEBUG);
+
+	reg = __raw_readl(ANADIG_USB2_MISC);
+	reg |= (0x01 << 30); /* Enable CLK_TO_UTMI */
+	__raw_writel(reg, ANADIG_USB2_MISC);
+
+	__raw_writel(0x10000007, USBPHY2_TX);
+	/*__raw_writel(0x100F0F07, USBPHY2_TX);*/
+
+	/* Enable disconnect detect */
+	reg = __raw_readl(USBPHY2_CTRL);
+	reg &= ~0x040; /* clear OTG ID change IRQ */
+	reg |= (0x1 << 14); /* Enable UTMI+ level2 */
+	reg |= (0x1 << 9);
+	reg |= (0x1 << 15); /* Enable UTMI+ level3 */
+	reg &= ~((0xD1 << 11) | 0x6);
+	__raw_writel(reg, USBPHY2_CTRL);
+	__raw_writel(0x1 << 3, USBPHY2_CTRL + 0x8);
+
+	/* Disable VBUS and CHARGER detect */
+	reg = __raw_readl(ANADIG_USB2_VBUS_DETECT);
+	reg |= 0xE8;
+	__raw_writel(reg, ANADIG_USB2_VBUS_DETECT);
+	__raw_writel(0x001c0000, ANADIG_USB2_CHRG_DETECT);
+
+#endif
+}
+
+/* USB HIGH_SPEED disconnect detect on/off */
+void fsl_platform_set_usb_phy_dis(struct fsl_usb2_platform_data *pdata,
+		bool enable)
+{
+	u32 reg;
+	reg =  __raw_readl(USBPHY2_CTRL);
+
+	if (enable)
+		reg |= ((0xD1 << 11) | 0x6);
+	else
+		reg &= ~((0xD1 << 11) | 0x6);
+
+	__raw_writel(reg, USBPHY2_CTRL);
+
+	__raw_writel(0x1 << 3, USBPHY2_CTRL + 0x8);
+
+}
diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
index 34e522a06247..d50c5b0be550 100644
--- a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
+++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
  *
  * Copyright (C) 2010 Pengutronix
  * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
@@ -43,6 +43,13 @@ const struct imx_fsl_usb2_udc_data imx6q_fsl_usb2_udc_data __initconst =
 	imx_fsl_usb2_udc_data_entry_single(MX6Q);
 #endif /* ifdef CONFIG_SOC_IMX6Q */
 
+#ifdef CONFIG_ARCH_MVF
+const struct imx_fsl_usb2_udc_data mvf_fsl_usb2_udc_data __initconst = {
+	.iobase = MVF_USBC0_BASE_ADDR,
+	.irq = MVF_INT_USBOTG0,
+};
+#endif
+
 struct platform_device *__init imx_add_fsl_usb2_udc(
 		const struct imx_fsl_usb2_udc_data *data,
 		const struct fsl_usb2_platform_data *pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c
index 700cf468ea8e..f700d656c3b7 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c
+++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c
@@ -58,6 +58,14 @@ const struct imx_mxc_ehci_data imx6q_mxc_ehci_hs_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX6Q */
 
+#ifdef CONFIG_ARCH_MVF
+const struct imx_mxc_ehci_data mvf_mxc_ehci_otg_data __initconst = {
+	.id = 0,
+	.iobase = MVF_USBC1_BASE_ADDR,
+	.irq = MVF_INT_USB2,
+};
+#endif
+
 struct platform_device *__init imx_add_mxc_ehci(
 		const struct imx_mxc_ehci_data *data,
 		const struct mxc_usbh_platform_data *pdata)
diff --git a/arch/arm/plat-mxc/include/mach/arc_otg.h b/arch/arm/plat-mxc/include/mach/arc_otg.h
index bdb6b252b356..51945e0fa957 100755
--- a/arch/arm/plat-mxc/include/mach/arc_otg.h
+++ b/arch/arm/plat-mxc/include/mach/arc_otg.h
@@ -27,6 +27,19 @@ extern void __iomem *imx_otg_base;
 #define OTG_BASE_ADDR           imx_otg_base
 #endif
 
+#ifdef CONFIG_ARCH_MVF
+
+#define USB_OTGREGS_BASE	MVF_IO_ADDRESS(0x40034000)
+#define USB_OTG2REGS_BASE	MVF_IO_ADDRESS(0x400B4000)
+#define USB_H1REGS_BASE		MVF_IO_ADDRESS(0x400B4000)
+/* dummy h2regs for MVF */
+#define USB_H2REGS_BASE		MVF_IO_ADDRESS(0x400B4000)
+#define USBC0_OTHERREGS_BASE	MVF_IO_ADDRESS(0x40034800)
+#define USBC1_OTHERREGS_BASE	MVF_IO_ADDRESS(0x400B4800)
+#define USB_OTHERREGS_BASE	USBC0_OTHERREGS_BASE
+
+#else
+
 #define USB_OTGREGS_BASE	(OTG_BASE_ADDR + 0x000)
 #define USB_H1REGS_BASE		(OTG_BASE_ADDR + 0x200)
 #define USB_H2REGS_BASE		(OTG_BASE_ADDR + 0x400)
@@ -37,6 +50,8 @@ extern void __iomem *imx_otg_base;
 #define USB_OTHERREGS_BASE	(OTG_BASE_ADDR + 0x600)
 #endif
 
+#endif
+
 #define USBOTG_REG32(offset)	(*((volatile u32 __force *)(USB_OTGREGS_BASE + (offset))))
 #define USBOTG_REG16(offset)	(*((volatile u16 __force *)(USB_OTGREGS_BASE + (offset))))
 
@@ -51,6 +66,16 @@ extern void __iomem *imx_otg_base;
 
 #define USBOTHER_REG(offset)	(*((volatile u32 __force *)(USB_OTHERREGS_BASE + (offset))))
 
+#ifdef CONFIG_ARCH_MVF
+#define USBOTG2_REG32(offset)	\
+		(*((volatile u32 __force *)(USB_OTG2REGS_BASE + (offset))))
+#define USBOTG2_REG16(offset)	\
+		(*((volatile u16 __force *)(USB_OTG2REGS_BASE + (offset))))
+#define USBC0_OTHER_REG(offset)	\
+		(*((volatile u32 __force *)(USBC0_OTHERREGS_BASE + (offset))))
+#define USBC1_OTHER_REG(offset)	\
+		(*((volatile u32 __force *)(USBC1_OTHERREGS_BASE + (offset))))
+#endif
 /*
  * OTG registers
  */
@@ -96,6 +121,52 @@ extern void __iomem *imx_otg_base;
 #define UOG_EPCTRL6		USBOTG_REG32(0x1d8)	/* endpoint control6 */
 #define UOG_EPCTRL7		USBOTG_REG32(0x1dc)	/* endpoint control7 */
 
+#ifdef CONFIG_ARCH_MVF
+/*
+ * OTG2 registers
+ */
+#define UOG2_ID			USBOTG2_REG32(0x00) /* Host ID */
+#define UOG2_HWGENERAL		USBOTG2_REG32(0x04) /* Host General */
+#define UOG2_HWHOST		USBOTG2_REG32(0x08) /* Host h/w params */
+#define UOG2_HWTXBUF		USBOTG2_REG32(0x10) /*TX buffer h/w params*/
+#define UOG2_HWRXBUF		USBOTG2_REG32(0x14) /*RX buffer h/w params*/
+#define UOG2_CAPLENGTH		USBOTG2_REG16(0x100) /*Capability reg length*/
+#define UOG2_HCIVERSION		USBOTG2_REG16(0x102) /*Host Interface version*/
+#define UOG2_HCSPARAMS		USBOTG2_REG32(0x104) /*Host ctrl struct parm*/
+#define UOG2_HCCPARAMS		USBOTG2_REG32(0x108) /*ctrl capability params*/
+#define UOG2_DCIVERSION		USBOTG2_REG32(0x120) /*device interface ver*/
+/* start EHCI registers: */
+#define UOG2_USBCMD		USBOTG2_REG32(0x140) /* USB command register */
+#define UOG2_USBSTS		USBOTG2_REG32(0x144) /* USB status register */
+#define UOG2_USBINTR		USBOTG2_REG32(0x148) /* interrupt enable reg */
+#define UOG2_FRINDEX		USBOTG2_REG32(0x14c) /* USB frame index */
+#define UOG2_PERIODICLISTBASE	USBOTG2_REG32(0x154) /* host list base addr */
+#define UOG2_DEVICEADDR		USBOTG2_REG32(0x154) /* device crtlr address */
+#define UOG2_ASYNCLISTADDR	USBOTG2_REG32(0x158) /* host next async addr */
+#define UOG2_EPLISTADDR		USBOTG2_REG32(0x158) /* device ep list addr */
+#define UOG2_BURSTSIZE		USBOTG2_REG32(0x160) /* host TT async buf sts*/
+#define UOG2_TXFILLTUNING	USBOTG2_REG32(0x164) /* TX FIFO fill tuning */
+#define UOG2_ULPIVIEW		USBOTG2_REG32(0x170) /* ULPI viewport */
+#define UOG2_CFGFLAG		USBOTG2_REG32(0x180) /* cfgflg (supports HS) */
+#define UOG2_PORTSC1		USBOTG2_REG32(0x184) /* port status and ctrl */
+/* end EHCI registers: */
+#define UOG2_OTGSC		USBOTG2_REG32(0x1a4) /* OTG status and ctrl */
+#define UOG2_USBMODE		USBOTG2_REG32(0x1a8) /* USB device mode */
+#define UOG2_ENDPTSETUPSTAT	USBOTG2_REG32(0x1ac) /* ep setup status */
+#define UOG2_ENDPTPRIME		USBOTG2_REG32(0x1b0) /* ep initialization */
+#define UOG2_ENDPTFLUSH		USBOTG2_REG32(0x1b4) /* ep de-initialize */
+#define UOG2_ENDPTSTAT		USBOTG2_REG32(0x1b8) /* endpoint status */
+#define UOG2_ENDPTCOMPLETE	USBOTG2_REG32(0x1bc) /* endpoint complete */
+#define UOG2_EPCTRL0		USBOTG2_REG32(0x1c0) /* endpoint control0 */
+#define UOG2_EPCTRL1		USBOTG2_REG32(0x1c4) /* endpoint control1 */
+#define UOG2_EPCTRL2		USBOTG2_REG32(0x1c8) /* endpoint control2 */
+#define UOG2_EPCTRL3		USBOTG2_REG32(0x1cc) /* endpoint control3 */
+#define UOG2_EPCTRL4		USBOTG2_REG32(0x1d0) /* endpoint control4 */
+#define UOG2_EPCTRL5		USBOTG2_REG32(0x1d4) /* endpoint control5 */
+#define UOG2_EPCTRL6		USBOTG2_REG32(0x1d8) /* endpoint control6 */
+#define UOG2_EPCTRL7		USBOTG2_REG32(0x1dc) /* endpoint control7 */
+
+#endif
 /*
  * Host 1 registers
  */
@@ -219,6 +290,12 @@ extern void __iomem *imx_otg_base;
 #define USBH1_PHY_CTRL1		USBOTHER_REG(0x20)	/* USB Cotrol Register 1*/
 #define USB_CLKONOFF_CTRL       USBOTHER_REG(0x24)      /* USB Clock on/off Control Register */
 
+/* MVF other regs */
+#define USBC0_CTRL		USBC0_OTHER_REG(0x00)
+#define USBC0_PHY_CTRL_0        USBC0_OTHER_REG(0x18)
+#define USBC1_CTRL              USBC1_OTHER_REG(0x00)
+#define USBC1_PHY_CTRL_0	USBC1_OTHER_REG(0x18)
+
 /* mx6x other regs */
 #define USB_OTG_CTRL			USBOTHER_REG(0x00)	/* USB OTG Control register */
 #define USB_H1_CTRL			USBOTHER_REG(0x04)	/* USB H1 Control register */
@@ -334,6 +411,8 @@ extern void __iomem *imx_otg_base;
 extern enum fsl_usb2_modes get_usb_mode(struct fsl_usb2_platform_data *pdata);
 #ifdef CONFIG_ARCH_MX6
 #include "regs-usbphy-mx6.h"
+#elif defined(CONFIG_ARCH_MVF)
+#include "regs-usbphy-mvf.h"
 #else
 #include "regs-usbphy-others.h"
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/regs-usbphy-mvf.h b/arch/arm/plat-mxc/include/mach/regs-usbphy-mvf.h
new file mode 100644
index 000000000000..ee19a057f624
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/regs-usbphy-mvf.h
@@ -0,0 +1,427 @@
+/*
+ * Freescale USBPHY Register Definitions
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#ifndef __ARCH_ARM___USBPHY_H
+#define __ARCH_ARM___USBPHY_H
+
+
+#define HW_USBPHY_PWD	(0x00000000)
+#define HW_USBPHY_PWD_SET	(0x00000004)
+#define HW_USBPHY_PWD_CLR	(0x00000008)
+#define HW_USBPHY_PWD_TOG	(0x0000000c)
+
+#define BP_USBPHY_PWD_RSVD2      21
+#define BM_USBPHY_PWD_RSVD2 0xFFE00000
+#define BF_USBPHY_PWD_RSVD2(v) \
+	(((v) << 21) & BM_USBPHY_PWD_RSVD2)
+#define BM_USBPHY_PWD_RXPWDRX 0x00100000
+#define BM_USBPHY_PWD_RXPWDDIFF 0x00080000
+#define BM_USBPHY_PWD_RXPWD1PT1 0x00040000
+#define BM_USBPHY_PWD_RXPWDENV 0x00020000
+#define BP_USBPHY_PWD_RSVD1      13
+#define BM_USBPHY_PWD_RSVD1 0x0001E000
+#define BF_USBPHY_PWD_RSVD1(v)  \
+	(((v) << 13) & BM_USBPHY_PWD_RSVD1)
+#define BM_USBPHY_PWD_TXPWDV2I 0x00001000
+#define BM_USBPHY_PWD_TXPWDIBIAS 0x00000800
+#define BM_USBPHY_PWD_TXPWDFS 0x00000400
+#define BP_USBPHY_PWD_RSVD0      0
+#define BM_USBPHY_PWD_RSVD0 0x000003FF
+#define BF_USBPHY_PWD_RSVD0(v)  \
+	(((v) << 0) & BM_USBPHY_PWD_RSVD0)
+
+#define HW_USBPHY_TX	(0x00000010)
+
+#define BP_USBPHY_TX_RSVD2      20
+#define BM_USBPHY_TX_RSVD2 0xFFF00000
+#define BF_USBPHY_TX_RSVD2(v) \
+	(((v) << 20) & BM_USBPHY_TX_RSVD2)
+#define BP_USBPHY_TX_TXCAL45DP      16
+#define BM_USBPHY_TX_TXCAL45DP 0x000F0000
+#define BF_USBPHY_TX_TXCAL45DP(v)  \
+	(((v) << 16) & BM_USBPHY_TX_TXCAL45DP)
+#define BP_USBPHY_TX_RSVD1      12
+#define BM_USBPHY_TX_RSVD1 0x0000F000
+#define BF_USBPHY_TX_RSVD1(v)  \
+	(((v) << 12) & BM_USBPHY_TX_RSVD1)
+#define BP_USBPHY_TX_TXCAL45DN      8
+#define BM_USBPHY_TX_TXCAL45DN 0x00000F00
+#define BF_USBPHY_TX_TXCAL45DN(v)  \
+	(((v) << 8) & BM_USBPHY_TX_TXCAL45DN)
+#define BP_USBPHY_TX_RSVD0      4
+#define BM_USBPHY_TX_RSVD0 0x000000F0
+#define BF_USBPHY_TX_RSVD0(v)  \
+	(((v) << 4) & BM_USBPHY_TX_RSVD0)
+#define BP_USBPHY_TX_D_CAL      0
+#define BM_USBPHY_TX_D_CAL 0x0000000F
+#define BF_USBPHY_TX_D_CAL(v)  \
+	(((v) << 0) & BM_USBPHY_TX_D_CAL)
+
+#define HW_USBPHY_RX	(0x00000020)
+#define HW_USBPHY_RX_SET	(0x00000024)
+#define HW_USBPHY_RX_CLR	(0x00000028)
+#define HW_USBPHY_RX_TOG	(0x0000002c)
+
+#define BP_USBPHY_RX_RSVD2      23
+#define BM_USBPHY_RX_RSVD2 0xFF800000
+#define BF_USBPHY_RX_RSVD2(v) \
+	(((v) << 23) & BM_USBPHY_RX_RSVD2)
+#define BM_USBPHY_RX_RXDBYPASS 0x00400000
+#define BP_USBPHY_RX_RSVD1      7
+#define BM_USBPHY_RX_RSVD1 0x003FFF80
+#define BF_USBPHY_RX_RSVD1(v)  \
+	(((v) << 7) & BM_USBPHY_RX_RSVD1)
+#define BP_USBPHY_RX_DISCONADJ      4
+#define BM_USBPHY_RX_DISCONADJ 0x00000070
+#define BF_USBPHY_RX_DISCONADJ(v)  \
+	(((v) << 4) & BM_USBPHY_RX_DISCONADJ)
+#define BM_USBPHY_RX_RSVD0 0x00000008
+#define BP_USBPHY_RX_ENVADJ      0
+#define BM_USBPHY_RX_ENVADJ 0x00000007
+#define BF_USBPHY_RX_ENVADJ(v)  \
+	(((v) << 0) & BM_USBPHY_RX_ENVADJ)
+
+#define HW_USBPHY_CTRL	(0x00000030)
+#define HW_USBPHY_CTRL_SET	(0x00000034)
+#define HW_USBPHY_CTRL_CLR	(0x00000038)
+#define HW_USBPHY_CTRL_TOG	(0x0000003c)
+
+#define BM_USBPHY_CTRL_SFTRST 0x80000000
+#define BM_USBPHY_CTRL_CLKGATE 0x40000000
+#define BM_USBPHY_CTRL_UTMI_SUSPENDM 0x20000000
+#define BM_USBPHY_CTRL_HOST_FORCE_LS_SE0 0x10000000
+#define BM_USBPHY_CTRL_OTG_ID_VALUE 0x08000000
+#define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS 0x04000000
+#define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE 0x02000000
+#define BM_USBPHY_CTRL_FSDLL_RST_EN 0x01000000
+#define BM_USBPHY_CTRL_ENVBUSCHG_WKUP 0x00800000
+#define BM_USBPHY_CTRL_ENIDCHG_WKUP 0x00400000
+#define BM_USBPHY_CTRL_ENDPDMCHG_WKUP 0x00200000
+#define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD 0x00100000
+#define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE 0x00080000
+#define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL 0x00040000
+#define BM_USBPHY_CTRL_WAKEUP_IRQ 0x00020000
+#define BM_USBPHY_CTRL_ENIRQWAKEUP 0x00010000
+#define BM_USBPHY_CTRL_ENUTMILEVEL3 0x00008000
+#define BM_USBPHY_CTRL_ENUTMILEVEL2 0x00004000
+#define BM_USBPHY_CTRL_DATA_ON_LRADC 0x00002000
+#define BM_USBPHY_CTRL_DEVPLUGIN_IRQ 0x00001000
+#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800
+#define BM_USBPHY_CTRL_RESUME_IRQ 0x00000400
+#define BM_USBPHY_CTRL_ENIRQRESUMEDETECT 0x00000200
+#define BM_USBPHY_CTRL_RESUMEIRQSTICKY 0x00000100
+#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080
+#define BM_USBPHY_CTRL_OTG_ID_CHG_IRQ 0x00000040
+#define BM_USBPHY_CTRL_DEVPLUGIN_POLARITY 0x00000020
+#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010
+#define BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ 0x00000008
+#define BM_USBPHY_CTRL_ENIRQHOSTDISCON 0x00000004
+#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002
+#define BM_USBPHY_CTRL_ENOTG_ID_CHG_IRQ 0x00000001
+
+#define HW_USBPHY_STATUS	(0x00000040)
+
+#define BP_USBPHY_STATUS_RSVD4      11
+#define BM_USBPHY_STATUS_RSVD4 0xFFFFF800
+#define BF_USBPHY_STATUS_RSVD4(v) \
+	(((v) << 11) & BM_USBPHY_STATUS_RSVD4)
+#define BM_USBPHY_STATUS_RESUME_STATUS 0x00000400
+#define BM_USBPHY_STATUS_RSVD3 0x00000200
+#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100
+#define BM_USBPHY_STATUS_RSVD2 0x00000080
+#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040
+#define BP_USBPHY_STATUS_RSVD1      4
+#define BM_USBPHY_STATUS_RSVD1 0x00000030
+#define BF_USBPHY_STATUS_RSVD1(v)  \
+	(((v) << 4) & BM_USBPHY_STATUS_RSVD1)
+#define BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS 0x00000008
+#define BP_USBPHY_STATUS_RSVD0      0
+#define BM_USBPHY_STATUS_RSVD0 0x00000007
+#define BF_USBPHY_STATUS_RSVD0(v)  \
+	(((v) << 0) & BM_USBPHY_STATUS_RSVD0)
+
+#define HW_USBPHY_DEBUG	(0x00000050)
+#define HW_USBPHY_DEBUG_SET	(0x00000054)
+#define HW_USBPHY_DEBUG_CLR	(0x00000058)
+#define HW_USBPHY_DEBUG_TOG	(0x0000005c)
+
+#define BM_USBPHY_DEBUG_RSVD3 0x80000000
+#define BM_USBPHY_DEBUG_CLKGATE 0x40000000
+#define BM_USBPHY_DEBUG_HOST_RESUME_DEBUG 0x20000000
+#define BP_USBPHY_DEBUG_SQUELCHRESETLENGTH      25
+#define BM_USBPHY_DEBUG_SQUELCHRESETLENGTH 0x1E000000
+#define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(v)  \
+	(((v) << 25) & BM_USBPHY_DEBUG_SQUELCHRESETLENGTH)
+#define BM_USBPHY_DEBUG_ENSQUELCHRESET 0x01000000
+#define BP_USBPHY_DEBUG_RSVD2      21
+#define BM_USBPHY_DEBUG_RSVD2 0x00E00000
+#define BF_USBPHY_DEBUG_RSVD2(v)  \
+	(((v) << 21) & BM_USBPHY_DEBUG_RSVD2)
+#define BP_USBPHY_DEBUG_SQUELCHRESETCOUNT      16
+#define BM_USBPHY_DEBUG_SQUELCHRESETCOUNT 0x001F0000
+#define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(v)  \
+	(((v) << 16) & BM_USBPHY_DEBUG_SQUELCHRESETCOUNT)
+#define BP_USBPHY_DEBUG_RSVD1      13
+#define BM_USBPHY_DEBUG_RSVD1 0x0000E000
+#define BF_USBPHY_DEBUG_RSVD1(v)  \
+	(((v) << 13) & BM_USBPHY_DEBUG_RSVD1)
+#define BM_USBPHY_DEBUG_ENTX2RXCOUNT 0x00001000
+#define BP_USBPHY_DEBUG_TX2RXCOUNT      8
+#define BM_USBPHY_DEBUG_TX2RXCOUNT 0x00000F00
+#define BF_USBPHY_DEBUG_TX2RXCOUNT(v)  \
+	(((v) << 8) & BM_USBPHY_DEBUG_TX2RXCOUNT)
+#define BP_USBPHY_DEBUG_RSVD0      6
+#define BM_USBPHY_DEBUG_RSVD0 0x000000C0
+#define BF_USBPHY_DEBUG_RSVD0(v)  \
+	(((v) << 6) & BM_USBPHY_DEBUG_RSVD0)
+#define BP_USBPHY_DEBUG_ENHSTPULLDOWN      4
+#define BM_USBPHY_DEBUG_ENHSTPULLDOWN 0x00000030
+#define BF_USBPHY_DEBUG_ENHSTPULLDOWN(v)  \
+	(((v) << 4) & BM_USBPHY_DEBUG_ENHSTPULLDOWN)
+#define BP_USBPHY_DEBUG_HSTPULLDOWN      2
+#define BM_USBPHY_DEBUG_HSTPULLDOWN 0x0000000C
+#define BF_USBPHY_DEBUG_HSTPULLDOWN(v)  \
+	(((v) << 2) & BM_USBPHY_DEBUG_HSTPULLDOWN)
+#define BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD 0x00000002
+#define BM_USBPHY_DEBUG_OTGIDPIOLOCK 0x00000001
+
+#define HW_USBPHY_DEBUG0_STATUS	(0x00000060)
+
+#define BP_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT      26
+#define BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT 0xFC000000
+#define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v) \
+	(((v) << 26) & BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT)
+#define BP_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT      16
+#define BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT 0x03FF0000
+#define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v)  \
+	(((v) << 16) & BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT)
+#define BP_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT      0
+#define BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT 0x0000FFFF
+#define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v)  \
+	(((v) << 0) & BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT)
+
+#define HW_USBPHY_DEBUG1	(0x00000070)
+#define HW_USBPHY_DEBUG1_SET	(0x00000074)
+#define HW_USBPHY_DEBUG1_CLR	(0x00000078)
+#define HW_USBPHY_DEBUG1_TOG	(0x0000007c)
+
+#define BP_USBPHY_DEBUG1_RSVD1      15
+#define BM_USBPHY_DEBUG1_RSVD1 0xFFFF8000
+#define BF_USBPHY_DEBUG1_RSVD1(v) \
+	(((v) << 15) & BM_USBPHY_DEBUG1_RSVD1)
+#define BP_USBPHY_DEBUG1_ENTAILADJVD      13
+#define BM_USBPHY_DEBUG1_ENTAILADJVD 0x00006000
+#define BF_USBPHY_DEBUG1_ENTAILADJVD(v)  \
+	(((v) << 13) & BM_USBPHY_DEBUG1_ENTAILADJVD)
+#define BP_USBPHY_DEBUG1_RSVD0      0
+#define BM_USBPHY_DEBUG1_RSVD0 0x00001FFF
+#define BF_USBPHY_DEBUG1_RSVD0(v)  \
+	(((v) << 0) & BM_USBPHY_DEBUG1_RSVD0)
+
+#define HW_USBPHY_VERSION	(0x00000080)
+
+#define BP_USBPHY_VERSION_MAJOR      24
+#define BM_USBPHY_VERSION_MAJOR 0xFF000000
+#define BF_USBPHY_VERSION_MAJOR(v) \
+	(((v) << 24) & BM_USBPHY_VERSION_MAJOR)
+#define BP_USBPHY_VERSION_MINOR      16
+#define BM_USBPHY_VERSION_MINOR 0x00FF0000
+#define BF_USBPHY_VERSION_MINOR(v)  \
+	(((v) << 16) & BM_USBPHY_VERSION_MINOR)
+#define BP_USBPHY_VERSION_STEP      0
+#define BM_USBPHY_VERSION_STEP 0x0000FFFF
+#define BF_USBPHY_VERSION_STEP(v)  \
+	(((v) << 0) & BM_USBPHY_VERSION_STEP)
+
+#define HW_USBPHY_IP	(0x00000090)
+#define HW_USBPHY_IP_SET	(0x00000094)
+#define HW_USBPHY_IP_CLR	(0x00000098)
+#define HW_USBPHY_IP_TOG	(0x0000009c)
+
+#define BP_USBPHY_IP_RSVD1      19
+#define BM_USBPHY_IP_RSVD1 0xFF800000
+#define BF_USBPHY_IP_RSVD1(v) \
+	(((v) << 19) & BM_USBPHY_IP_RSVD1)
+#define BM_USBPHY_IP_TSTI_TX_DP 0x00040000
+#define BM_USBPHY_IP_TSTI_TX_DM 0x00020000
+#define BM_USBPHY_IP_ANALOG_TESTMODE 0x00010000
+#define BP_USBPHY_IP_RSVD0      3
+#define BM_USBPHY_IP_RSVD0 0x0000FFF8
+#define BF_USBPHY_IP_RSVD0(v)  \
+	(((v) << 3) & BM_USBPHY_IP_RSVD0)
+#define BM_USBPHY_IP_EN_USB_CLKS 0x00000004
+#define BM_USBPHY_IP_PLL_LOCKED 0x00000002
+#define BM_USBPHY_IP_PLL_POWER 0x00000001
+
+/* The register definition for usbphy which includes at usb core's register set
+ * (from USB_CORE_BASE + 0x800)
+ */
+#define USB_CTRL		USBOTHER_REG(0x00) /* USB OTG Control reg */
+#define USB_H1_CTRL		USBOTHER_REG(0x04) /* USB H1 Control reg */
+#define USB_H2_CTRL		USBOTHER_REG(0x08) /* USB H2 Control reg */
+#define USB_H3_CTRL		USBOTHER_REG(0x0c) /* USB H3 Control reg */
+#define USB_UH2_HSIC_CTRL	USBOTHER_REG(0x10) /* USB H2 HSIC Ctrl Reg */
+#define USB_UH3_HSIC_CTRL	USBOTHER_REG(0x14) /* USB H3 HSIC Ctrl Reg */
+#define USB_OTG_PHY_CTRL_0	USBOTHER_REG(0x18) /* OTG UTMI PHY Ctrl0 Reg */
+/*
+ * register bits
+ */
+
+/* USBCTRL */
+#define UCTRL_OSIC_MASK		(3 << 29) /* OTG  Serial Interface Config: */
+#define UCTRL_OSIC_DU6		(0 << 29) /* Diff/unidirectional 6 wire */
+#define UCTRL_OSIC_DB4		(1 << 29) /* Diff/bidirectional  4 wire */
+#define UCTRL_OSIC_SU6		(2 << 29) /* SE/unidirectional 6 wire */
+#define UCTRL_OSIC_SB3		(3 << 29) /* SE/bidirectional  3 wire */
+#define UCTRL_OUIE		(1 << 28) /* OTG ULPI intr enable */
+#define UCTRL_OBPVAL_RXDP	(1 << 26) /* OTG RxDp status in bypass mode */
+#define UCTRL_OBPVAL_RXDM	(1 << 25) /* OTG RxDm status in bypass mode */
+#define UCTRL_OPM		(1 << 24) /* OTG power mask */
+#define UCTRL_O_PWR_POL	(1 << 24)	/* OTG power pin polarity */
+#define UCTRL_H2WIR		(1 << 17) /* H2 wakeup intr request received */
+#define UCTRL_H2SIC_MASK	(3 << 21) /* H2 Serial Interface Config: */
+#define UCTRL_H2SIC_DU6		(0 << 21) /*Differential/unidirectional 6wire*/
+#define UCTRL_H2SIC_DB4		(1 << 21) /*Differential/bidirectional 4 wire*/
+#define UCTRL_H2SIC_SU6		(2 << 21) /*single-ended/unidirectional 6wire*/
+#define UCTRL_H2SIC_SB3		(3 << 21) /*single-ended/bidirectional 3 wire*/
+#define UCTRL_H2UIE		(1 << 8)	/* HOST2 ULPI intr enable */
+#define UCTRL_H2WIE		(1 << 7)	/* HOST2 wakeup intr enable */
+#define UCTRL_H2PP		0	/* Power Polarity for uh2 */
+#define UCTRL_H2PM		(1 << 4) /* HOST2 power mask */
+#define UCTRL_H2OVBWK_EN	(1 << 6) /* OTG VBUS Wakeup Enable */
+#define UCTRL_H2OIDWK_EN	(1 << 5) /* OTG ID Wakeup Enable */
+
+#define UCTRL_H1WIR		(1 << 15) /* H1 wakeup intr request received */
+#define UCTRL_H1SIC_MASK	(3 << 13) /* H1 Serial Interface Config: */
+#define UCTRL_H1SIC_DU6		(0 << 13) /*Differential/unidirectional 6wire*/
+#define UCTRL_H1SIC_DB4		(1 << 13) /*Differential/bidirectional 4 wire*/
+#define UCTRL_H1SIC_SU6		(2 << 13) /*singleended/unidirectional 6 wire*/
+#define UCTRL_H1SIC_SB3		(3 << 13) /*singleended/bidirectional  3 wire*/
+#define UCTRL_OLOCKD		(1 << 13) /* otg lock disable */
+#define UCTRL_H2LOCKD		(1 << 12) /* HOST2 lock disable */
+#define UCTRL_H1UIE		(1 << 12) /* H1 ULPI interrupt enable */
+
+#define UCTRL_PP                (1 << 11) /* power polarity bit */
+#define UCTRL_H1WIE		(1 << 11) /* H1 wakeup intr enable */
+#define UCTRL_H1BPVAL_RXDP	(1 << 10) /* H1 RxDp status in bypass mode */
+#define UCTRL_XCSO              (1 << 10) /* Xcvr Clock Select for OTG port */
+#define UCTRL_H1BPVAL_RXDM	(1 <<  9) /* H1 RxDm status in bypass mode */
+#define UCTRL_XCSH2             (1 <<  9) /* Xcvr Clock Select for Host port */
+#define UCTRL_H1PM		(1 <<  8) /* HOST1 power mask */
+#define UCTRL_IP_PULIDP         (1 <<  8) /* Ipp_Puimpel_Pullup_Dp */
+
+#define UCTRL_IP_PUE_UP         (1 <<  7)       /* ipp_pue_pullup_dp */
+#define UCTRL_IP_PUE_DOWN       (1 <<  6)       /* ipp_pue_pulldwn_dpdm */
+#define UCTRL_H2DT		(1 <<  5)	/* HOST2 TLL disabled */
+#define UCTRL_H1DT		(1 <<  4)	/* HOST1 TLL disabled */
+#define UCTRL_USBTE             (1 <<  4)       /* USBT Transceiver enable */
+#define UCTRL_OCPOL             (1 <<  8)       /* OverCurrent Polarity */
+#define UCTRL_OCE               (1 <<  7)       /* OverCurrent Enable */
+#define UCTRL_H2OCPOL		(1 <<  2) /* OverCurrent Polarity of Host2 */
+#define UCTRL_H2OCS             (1 <<  1)       /* Host OverCurrent State */
+#define UCTRL_BPE		(1 <<  0)	/* bypass mode enable */
+#define UCTRL_OTD		(1 <<  0)	/* OTG TLL Disable */
+#define UCTRL_OOCS              (1 <<  0)       /* OTG OverCurrent State */
+
+/* OTG_MIRROR */
+#define OTGM_SESEND		(1 << 4)	/* B device session end */
+#define OTGM_VBUSVAL		(1 << 3)	/* Vbus valid */
+#define OTGM_BSESVLD		(1 << 2)	/* B session Valid */
+#define OTGM_ASESVLD		(1 << 1)	/* A session Valid */
+#define OTGM_IDIDG		(1 << 0)	/* OTG ID pin status */
+				/* 1=high: Operate as B-device */
+				/* 0=low : Operate as A-device */
+
+/* USB_PHY_CTRL_FUNC */
+/* PHY control0 Register Bit Masks */
+#define USB_UTMI_PHYCTRL_CONF2	(1 << 26)
+
+#define USB_UTMI_PHYCTRL_UTMI_ENABLE (1 << 24)
+#define USB_UTMI_PHYCTRL_CHGRDETEN (1 << 24) /* Enable Charger Detector */
+#define USB_UTMI_PHYCTRL_CHGRDETON (1 << 23) /* Charger Detector Pwr On Ctrl*/
+#define USB_UTMI_PHYCTRL_OC_POL	(1 << 9) /* OTG Polarity of Overcurrent */
+#define USB_UTMI_PHYCTRL_OC_DIS	(1 << 8) /* OTG Disable Overcurrent Event */
+#define USB_UH1_OC_DIS	(1 << 5)	/* UH1 Disable Overcurrent Event */
+#define USB_UH1_OC_POL	(1 << 6)	/* UH1 Polarity of OC,Low active */
+/* USB_PHY_CTRL_FUNC2*/
+#define USB_UTMI_PHYCTRL2_PLLDIV_MASK		0x3
+#define USB_UTMI_PHYCTRL2_PLLDIV_SHIFT		0
+#define USB_UTMI_PHYCTRL2_HSDEVSEL_MASK		0x3
+#define USB_UTMI_PHYCTRL2_HSDEVSEL_SHIFT	19
+
+/* USB_CTRL_1 */
+#define USB_CTRL_UH1_EXT_CLK_EN			(1 << 25)
+#define USB_CTRL_UH2_EXT_CLK_EN			(1 << 26)
+#define USB_CTRL_UH2_CLK_FROM_ULPI_PHY		(1 << 2)
+/* ULPIVIEW register bits */
+#define ULPIVW_OFF		(0x170)
+#define ULPIVW_WU		(1 << 31)	/* Wakeup */
+#define ULPIVW_RUN		(1 << 30)	/* read/write run */
+#define ULPIVW_WRITE		(1 << 29)	/* 0=read  1=write */
+#define ULPIVW_SS		(1 << 27)	/* SyncState */
+#define ULPIVW_PORT_MASK	0x07	/* Port field */
+#define ULPIVW_PORT_SHIFT	24
+#define ULPIVW_ADDR_MASK	0xFF	/* data address field */
+#define ULPIVW_ADDR_SHIFT	16
+#define ULPIVW_RDATA_MASK	0xFF	/* read data field */
+#define ULPIVW_RDATA_SHIFT	8
+#define ULPIVW_WDATA_MASK	0xFF	/* write data field */
+#define ULPIVW_WDATA_SHIFT	0
+
+/* USB Clock on/off Control Register */
+#define OTG_AHBCLK_OFF          (0x1<<17)      /* 1: OFF */
+#define H1_AHBCLK_OFF           (0x1<<18)      /* 1: OFF */
+
+/* OTG CTRL - H3 CTRL */
+/* OTG wakeup intr request received */
+#define UCTRL_OWIR		(1 << 31)
+/* bit 18 - bit 30 is reserved at mx6q */
+/* OTG wake-up on VBUS change enable */
+#define UCTRL_WKUP_VBUS_EN	(1 << 17)
+/* OTG wake-up on ID change enable */
+#define UCTRL_WKUP_ID_EN	(1 << 16)
+#define UCTRL_WKUP_SW		(1 << 15) /* OTG Software Wake-up */
+#define UCTRL_WKUP_SW_EN	(1 << 14) /* OTG Software Wake-up enable */
+/* Force OTG UTMI PHY clock output on even if suspend mode */
+#define UCTRL_UTMI_ON_CLOCK	(1 << 13)
+#define UCTRL_SUSPENDM		(1 << 12) /* Force OTG UTMI PHY Suspend */
+#define UCTRL_RESET		(1 << 11) /* Force OTG UTMI PHY Reset */
+#define UCTRL_OWIE		(1 << 10) /* OTG wakeup intr request received*/
+#define UCTRL_PM		(1 << 9) /* OTG Power Mask */
+#define UCTRL_OVER_CUR_POL	(1 << 8) /* OTG Polarity of Overcurrent */
+#define UCTRL_OVER_CUR_DIS	(1 << 7) /* Disable OTG Overcurrent Detection*/
+/* bit 0 - bit 6 is reserved at mx6q */
+
+/* Host2/3 HSIC Ctrl */
+/* Indicating whether HSIC clock is valid */
+#define CLK_VLD		(1 << 31)
+#define HSIC_DEV_CONN		(1 << 21)	/* set after device connected */
+#define HSIC_EN		(1 << 12)	/* HSIC enable */
+/* Force HSIC module 480M clock on,
+ * even when in Host is in suspend mode
+ */
+#define HSIC_CLK_ON		(1 << 11)
+/* OTG/HOST1 Phy Ctrl */
+/* Indicating whether OTG UTMI PHY Clock Valida */
+#define PHY_UTMI_CLK_VLD	(1 << 31)
+
+#define NOP_XCVR		(0xffffffff)	/* Indicate it is no usb phy */
+#endif /* __ARCH_ARM___USBPHY_H */
diff --git a/arch/arm/plat-mxc/usb_common.c b/arch/arm/plat-mxc/usb_common.c
index bb9c45a0127e..0aa3d590d1d2 100755
--- a/arch/arm/plat-mxc/usb_common.c
+++ b/arch/arm/plat-mxc/usb_common.c
@@ -46,6 +46,7 @@
 #include <linux/regulator/consumer.h>
 #include <linux/io.h>
 #include <asm/mach-types.h>
+#include <mach/mvf.h>
 #include <mach/arc_otg.h>
 #include <mach/hardware.h>
 #include <mach/mxc.h>
@@ -86,6 +87,9 @@ static int fsl_check_usbclk(void)
 {
 	unsigned long freq;
 
+	if (cpu_is_mvf())
+		return 0;
+
 	usb_ahb_clk = clk_get(NULL, "usb_ahb_clk");
 	if (clk_enable(usb_ahb_clk)) {
 		if (cpu_is_mx6q() || cpu_is_mx6dl())
@@ -716,11 +720,15 @@ static void otg_set_utmi_xcvr(void)
 	} else if (cpu_is_mx50()) {
 		USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS;
 	} else {
+#ifndef CONFIG_ARCH_MVF
 		/* USBOTG_PWR low active */
 		USBCTRL &= ~UCTRL_PP;
 		/* OverCurrent Polarity is Low Active */
 		USBCTRL &= ~UCTRL_OCPOL;
-
+#else
+		USBCTRL |= USB_UTMI_PHYCTRL_OC_DIS;
+		USBC0_CTRL &= ~UCTRL_OCPOL;
+#endif
 		if (cpu_is_mx35() && (imx_cpu_ver() < IMX_CHIP_REVISION_2_0))
 			/* OTG Lock Disable */
 			USBCTRL |= UCTRL_OLOCKD;
@@ -728,9 +736,11 @@ static void otg_set_utmi_xcvr(void)
 
 	if (cpu_is_mx51())
 		USBCTRL &= ~UCTRL_OPM;	/* OTG Power Mask */
-
+#ifndef CONFIG_ARCH_MVF
 	USBCTRL &= ~UCTRL_OWIE;	/* OTG Wakeup Intr Disable */
-
+#else
+	USBC0_CTRL &= ~UCTRL_OWIE;
+#endif
 	/* set UTMI xcvr */
 	tmp = UOG_PORTSC1 & ~PORTSC_PTS_MASK;
 	tmp |= PORTSC_PTS_UTMI;
@@ -832,6 +842,9 @@ int usbotg_init(struct platform_device *pdev)
 			} else if (xops->xcvr_type == PORTSC_PTS_UTMI) {
 				otg_set_utmi_xcvr();
 			}
+#ifdef CONFIG_ARCH_MVF
+			USB_OTG_CTRL |= UCTRL_OVER_CUR_DIS;
+#endif
 		} else {
 #ifdef CONFIG_ARCH_MX6
 			if (machine_is_mx6q_arm2())
@@ -879,6 +892,151 @@ void usbotg_uninit(struct fsl_usb2_platform_data *pdata)
 }
 EXPORT_SYMBOL(usbotg_uninit);
 
+static void otg2_set_utmi_xcvr(void)
+{
+	u32 tmp;
+
+	/* Stop then Reset */
+	UOG2_USBCMD &= ~UCMD_RUN_STOP;
+
+	while (UOG2_USBCMD & UCMD_RUN_STOP)
+		;
+
+	UOG2_USBCMD |= UCMD_RESET;
+	while ((UOG2_USBCMD) & (UCMD_RESET))
+		;
+
+	/* USBOTG_PWR low active */
+	/* OverCurrent Polarity is Low Active */
+	USBC1_CTRL &= ~UCTRL_OCPOL;
+
+
+	USBC1_CTRL &= ~UCTRL_OWIE;	/* OTG Wakeup Intr Disable */
+
+	/* set UTMI xcvr */
+	tmp = UOG2_PORTSC1 & ~PORTSC_PTS_MASK;
+	tmp |= PORTSC_PTS_UTMI;
+	UOG2_PORTSC1 = tmp;
+
+	/* Workaround an IC issue for ehci driver:
+	 * when turn off root hub port power, EHCI set
+	 * PORTSC reserved bits to be 0, but PTW with 0
+	 * means 8 bits tranceiver width, here change
+	 * it back to be 16 bits and do PHY diable and
+	 * then enable.
+	 */
+	UOG2_PORTSC1 |= PORTSC_PTW;
+
+	/* need to reset the controller here so that the ID pin
+	 * is correctly detected.
+	 */
+	/* Stop then Reset */
+	UOG2_USBCMD &= ~UCMD_RUN_STOP;
+	while (UOG2_USBCMD & UCMD_RUN_STOP)
+		;
+
+	UOG2_USBCMD |= UCMD_RESET;
+	while ((UOG2_USBCMD) & (UCMD_RESET))
+		;
+
+	/* allow controller to reset, and leave time for
+	 * the ULPI transceiver to reset too.
+	 */
+	msleep(100);
+
+}
+
+static int mxc_otg2_used;
+
+int usbotg2_init(struct platform_device *pdev)
+{
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+	struct fsl_xcvr_ops *xops;
+	unsigned long reg32;
+
+
+	pr_debug("%s: pdev=0x%p  pdata=0x%p\n", __func__, pdev, pdata);
+
+	xops = fsl_usb_get_xcvr(pdata->transceiver);
+	if (!xops) {
+		printk(KERN_ERR "DR transceiver ops missing\n");
+		return -EINVAL;
+	}
+	pdata->xcvr_ops = xops;
+	pdata->xcvr_type = xops->xcvr_type;
+	pdata->pdev = pdev;
+
+
+	if (fsl_check_usbclk() != 0)
+		return -EINVAL;
+	if (!mxc_otg2_used) {
+
+		pr_debug("%s: grab pins\n", __func__);
+		if (pdata->gpio_usb_active && pdata->gpio_usb_active())
+			return -EINVAL;
+		if (xops->init)
+			xops->init(xops);
+		if (!((cpu_is_mx6q() || cpu_is_mx6dl()))) {
+			UOG2_PORTSC1 = UOG2_PORTSC1 & ~PORTSC_PHCD;
+
+
+			if (xops->xcvr_type == PORTSC_PTS_SERIAL) {
+				if (pdata->operating_mode == FSL_USB2_DR_HOST) {
+					otg_set_serial_host();
+					/* need reset */
+					UOG2_USBCMD |= UCMD_RESET;
+					msleep(100);
+				} else if (pdata->operating_mode ==
+							FSL_USB2_DR_DEVICE)
+					otg_set_serial_peripheral();
+				otg_set_serial_xcvr();
+			} else if (xops->xcvr_type == PORTSC_PTS_ULPI) {
+				otg_set_ulpi_xcvr();
+			} else if (xops->xcvr_type == PORTSC_PTS_UTMI) {
+				otg2_set_utmi_xcvr();
+			}
+		} else {
+#ifdef CONFIG_ARCH_MX6
+			if (machine_is_mx6q_arm2())
+				USB_OTG_CTRL &= ~UCTRL_OVER_CUR_POL;
+			else if (machine_is_mx6q_sabrelite())
+				USB_OTG_CTRL |= UCTRL_OVER_CUR_POL;
+			USB_OTG_CTRL |= UCTRL_OVER_CUR_DIS;
+#endif
+		}
+	}
+
+	if (usb_register_remote_wakeup(pdev))
+		pr_debug("DR is not a wakeup source.\n");
+
+	mxc_otg2_used++;
+	pr_debug("%s: success\n", __func__);
+	return 0;
+}
+EXPORT_SYMBOL(usbotg2_init);
+
+void usbotg2_uninit(struct fsl_usb2_platform_data *pdata)
+{
+	pr_debug("%s\n", __func__);
+
+	mxc_otg_used--;
+	if (!mxc_otg2_used) {
+		if (pdata->xcvr_ops && pdata->xcvr_ops->uninit)
+			pdata->xcvr_ops->uninit(pdata->xcvr_ops);
+
+		pdata->regs = NULL;
+
+		msleep(1);
+		UOG2_PORTSC1 = UOG2_PORTSC1 | PORTSC_PHCD;
+		if (pdata->gpio_usb_inactive)
+			pdata->gpio_usb_inactive();
+		if (pdata->xcvr_type == PORTSC_PTS_SERIAL)
+			clk_disable(usb_clk);
+	}
+}
+EXPORT_SYMBOL(usbotg2_uninit);
+
+
 /*
  * This function is used to debounce the reading value for id/vbus at
  * the register of otgsc