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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2013-03-14 09:59:09 +0100
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2013-03-14 09:59:09 +0100
commit78aeecd7bb86f199ea85987413922a9b866aaf5a (patch)
treede00366dcc8ad462834bf23052e4e8f49fc42578
parent5aa0cf77e07f59d1cd84e827d1748f0353997eaa (diff)
apalis_t30: default full HD LVDS resolution
By default configure for LG LP156WF1 15.6 inch full HD dual channel LVDS panel.
-rw-r--r--arch/arm/mach-tegra/board-apalis_t30-panel.c6
-rw-r--r--arch/arm/mach-tegra/board-apalis_t30.h2
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/board-apalis_t30-panel.c b/arch/arm/mach-tegra/board-apalis_t30-panel.c
index d8bfbec38706..8be309edf52c 100644
--- a/arch/arm/mach-tegra/board-apalis_t30-panel.c
+++ b/arch/arm/mach-tegra/board-apalis_t30-panel.c
@@ -259,7 +259,6 @@ static struct tegra_dc_mode apalis_t30_panel_modes[] = {
.h_front_porch = 16, /* right_margin */
.v_front_porch = 10, /* lower_margin */
},
-#else /* TEGRA_FB_VGA */
{
/* 800x480@60 (e.g. EDT ET070080DH6) */
.pclk = 32460000,
@@ -410,6 +409,7 @@ static struct tegra_dc_mode apalis_t30_panel_modes[] = {
.v_front_porch = 1,
//high active vertical sync polarity
},
+#else /* TEGRA_FB_VGA */
{
/* LG LP156WF1 15.6 inch full HD dual channel LVDS panel */
.pclk = 138500000,
@@ -503,8 +503,8 @@ static struct tegra_fb_data apalis_t30_fb_data = {
.xres = 640,
.yres = 480,
#else /* TEGRA_FB_VGA */
- .xres = 800,
- .yres = 480,
+ .xres = 1920,
+ .yres = 1080,
#endif /* TEGRA_FB_VGA */
.bits_per_pixel = 16,
.flags = TEGRA_FB_FLIP_ON_PROBE,
diff --git a/arch/arm/mach-tegra/board-apalis_t30.h b/arch/arm/mach-tegra/board-apalis_t30.h
index 0e68be4e4de5..ad9d68c591d2 100644
--- a/arch/arm/mach-tegra/board-apalis_t30.h
+++ b/arch/arm/mach-tegra/board-apalis_t30.h
@@ -27,7 +27,7 @@
#include <mach/irqs.h>
/* Run framebuffer in VGA mode */
-#define TEGRA_FB_VGA
+//#define TEGRA_FB_VGA
/* GPIO */