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authorShreshtha SAHU <ssahu@nvidia.com>2014-09-03 17:45:17 +0530
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2014-09-03 14:55:26 +0200
commit2df7c712311f5b6b0ed6ee281564f91713a6ebf2 (patch)
treea876ae488f03558c29dab68ae125016758df48cc
parentf19862239945df13113ec429e46c1ba6935eadc6 (diff)
arm: tegra30: pcie: do not disable clk after deasserting resetsApalis_T30_LinuxImageV2.3Beta2_20140903
Do not disable and re-enable clocks after deasserting PCIE, AFI and PCIEX resets. Deasserting the resets should be followed by programming the PCIE. Bug 1521306 Change-Id: Idc43bc9b21cac3818852ed059fe512f4cd75b748 Signed-off-by: Shreshtha SAHU <ssahu@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/powergate.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 637877e..96ac446 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -709,7 +709,10 @@ int tegra_unpowergate_partition(int id)
mc_flush_done(id);
/* Disable all clks enabled earlier. Drivers should enable clks */
- partition_clk_disable(id);
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+ if (id != TEGRA_POWERGATE_PCIE)
+#endif
+ partition_clk_disable(id);
return 0;
@@ -744,9 +747,14 @@ int tegra_unpowergate_partition_with_clk_on(int id)
goto err_unpowergating;
/* Enable clks for the partition */
- ret = partition_clk_enable(id);
- if (ret)
- goto err_unpowergate_clk;
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+ if (id != TEGRA_POWERGATE_PCIE)
+#endif
+ {
+ ret = partition_clk_enable(id);
+ if (ret)
+ goto err_unpowergate_clk;
+ }
return ret;