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| author | Preetham Chandru R <pchandru@nvidia.com> | 2015-10-26 17:21:46 +0530 |
|---|---|---|
| committer | Matthew Pedro <mapedro@nvidia.com> | 2015-12-10 08:50:26 -0800 |
| commit | fa425425dc12dbb8266354307244edb3b962fc06 (patch) | |
| tree | 892d9bd3dc938c161814f92a0bbd017c0de7c95f | |
| parent | def1339b1678fd043bed01ffbb3efa188f37c1bd (diff) | |
ata: ahci: Enable 40 bit alignment detection
Bug 1694187
Change-Id: Idb8d95f0a7bc099989cc5b7b0bc97bf5cc896b32
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/837972
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
| -rw-r--r-- | drivers/ata/ahci-tegra.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/ata/ahci-tegra.c b/drivers/ata/ahci-tegra.c index 08cccf357584..a80a8b1fc825 100644 --- a/drivers/ata/ahci-tegra.c +++ b/drivers/ata/ahci-tegra.c @@ -1105,6 +1105,7 @@ static int tegra_ahci_controller_init(struct tegra_ahci_host_priv *tegra_hpriv, */ val = scfg_readl(T_SATA0_CFG_PHY_REG); val |= T_SATA0_CFG_PHY_SQUELCH_MASK; + val &= ~PHY_USE_7BIT_ALIGN_DET_FOR_SPD_MASK; scfg_writel(val, T_SATA0_CFG_PHY_REG); val = scfg_readl(T_SATA0_NVOOB); |