Apalis iMX6: further bringup

- Pinmuxing

3 files changed, 603 insertions, 52 deletions

diff --git a/arch/arm/configs/colibri_imx6_defconfig b/arch/arm/configs/apalis_imx6_defconfig
index bd1be4079fe4..bfe253bdb772 100644
--- a/arch/arm/configs/colibri_imx6_defconfig
+++ b/arch/arm/configs/apalis_imx6_defconfig
@@ -155,7 +155,7 @@ CONFIG_PPPOLAC=y
 CONFIG_PPPOPNS=y
 CONFIG_INPUT_POLLDEV=y
 CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_GPIO is not set
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_INPUT_MISC=y
@@ -182,9 +182,9 @@ CONFIG_MEDIA_SUPPORT=y
 CONFIG_VIDEO_DEV=y
 # CONFIG_RC_CORE is not set
 # CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_VIDEO_MXC_CAMERA=m
-CONFIG_MXC_CAMERA_OV5642=m
-CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
+# CONFIG_VIDEO_MXC_CAMERA=m
+# CONFIG_MXC_CAMERA_OV5642=m
+# CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
 CONFIG_USB_VIDEO_CLASS=y
 # CONFIG_RADIO_ADAPTERS is not set
 CONFIG_DRM=m
diff --git a/arch/arm/mach-mx6/board-mx6_nitrogen6x.c b/arch/arm/mach-mx6/board-mx6_nitrogen6x.c
index b46e882f5d68..fb6ac45aa736 100644
--- a/arch/arm/mach-mx6/board-mx6_nitrogen6x.c
+++ b/arch/arm/mach-mx6/board-mx6_nitrogen6x.c
@@ -79,15 +79,17 @@
 #include "crm_regs.h"
 #include "cpu_op-mx6.h"
 
-#define GP_SD3_CD		IMX_GPIO_NR(7, 0)
-#define GP_SD3_WP		IMX_GPIO_NR(7, 1)
-#define GP_SD4_CD		IMX_GPIO_NR(2, 6)
-#define GP_SD4_WP		IMX_GPIO_NR(2, 7)
+#define GP_SD1_CD		IMX_GPIO_NR(4, 20) /* Apalis MMC1 */
+#define GP_SD1_WP		(-1)
+#define GP_SD4_CD		IMX_GPIO_NR(6, 14) /* Apalis SD1 */
+#define GP_SD4_WP		(-1)
 #define GP_ECSPI1_CS1	IMX_GPIO_NR(3, 19)
 #define GP_USB_OTG_PWR	IMX_GPIO_NR(3, 22)
 #define GP_CAP_TCH_INT1	IMX_GPIO_NR(1, 9)
 #define GP_DRGB_IRQGPIO	IMX_GPIO_NR(4, 20)
-#define GP_USB_HUB_RESET	IMX_GPIO_NR(7, 12)
+#define GP_USB_PEN	IMX_GPIO_NR(1, 0) /* USBH_EN */
+#define GP_USB_HUB_VBUS	IMX_GPIO_NR(3, 28) /* USB_VBUS_DET */
+#ifdef TODO
 #define GP_CAN1_STBY		IMX_GPIO_NR(1, 2)
 #define GP_CAN1_EN		IMX_GPIO_NR(1, 4)
 #define GP_CAN1_ERR		IMX_GPIO_NR(1, 7)
@@ -99,12 +101,13 @@
 #define GP_VOL_DOWN_KEY	IMX_GPIO_NR(4, 5)
 #define GP_CSI0_RST		IMX_GPIO_NR(1, 8)
 #define GP_CSI0_PWN		IMX_GPIO_NR(1, 6)
+#endif
 #define GP_ENET_PHY_INT	IMX_GPIO_NR(1, 28)
-
+#if 0
 #define N6_WL1271_WL_IRQ		IMX_GPIO_NR(6, 14)
 #define N6_WL1271_WL_EN			IMX_GPIO_NR(6, 15)
 #define N6_WL1271_BT_EN			IMX_GPIO_NR(6, 16)
-
+#endif
 #define CAN1_ERR_TEST_PADCFG	(PAD_CTL_PKE | PAD_CTL_PUE | \
 		PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
 		PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
@@ -127,9 +130,9 @@
 #define CSI0_CAMERA
 #endif
 
-#include "pads-mx6_nitrogen6x.h"
+#include "pads-mx6_apalis_imx6.h"
 #define FOR_DL_SOLO
-#include "pads-mx6_nitrogen6x.h"
+#include "pads-mx6_apalis_imx6.h"
 
 void __init early_console_setup(unsigned long base, struct clk *clk);
 static struct clk *sata_clk;
@@ -159,31 +162,18 @@ static int mxc_iomux_v3_setup_pads(iomux_v3_cfg_t *mx6q_pad_list,
         }
         return 0;
 }
-
+#if 0
 struct gpio n6w_wl1271_gpios[] __initdata = {
 	{.label = "wl1271_int",		.gpio = N6_WL1271_WL_IRQ,	.flags = GPIOF_DIR_IN},
 	{.label = "wl1271_bt_en",	.gpio = N6_WL1271_BT_EN,	.flags = 0},
 	{.label = "wl1271_wl_en",	.gpio = N6_WL1271_WL_EN,	.flags = 0},
 };
+#endif
 
 __init static int is_nitrogen6w(void)
 {
-	int ret = gpio_request_array(n6w_wl1271_gpios,
-			ARRAY_SIZE(n6w_wl1271_gpios));
-	if (ret) {
-		printk(KERN_ERR "%s gpio_request_array failed("
-				"%d) for n6w_wl1271_gpios\n", __func__, ret);
-		return ret;
-	}
-	ret = gpio_get_value(N6_WL1271_WL_IRQ);
-	if (ret <= 0) {
-		/* Sabrelite, not nitrogen6w */
-		gpio_free(N6_WL1271_WL_IRQ);
-		gpio_free(N6_WL1271_WL_EN);
-		gpio_free(N6_WL1271_BT_EN);
-		ret = 0;
-	}
-	return ret;
+	/* TODO implement module type detection */
+	return 1;
 }
 
 enum sd_pad_mode {
@@ -222,13 +212,14 @@ static int plt_sd_pad_change(unsigned int index, int clock)
 	return IOMUX_SETUP(sd_pads[i]);
 }
 
+#if 0
 static void sdio_set_power(int on)
 {
 	pr_debug("%s:%s: set power(%d)\n",
 		 __FILE__, __func__, on);
 	gpio_set_value(N6_WL1271_WL_EN,on);
 }
-
+#endif
 #ifdef CONFIG_WL12XX_PLATFORM_DATA
 static struct esdhc_platform_data sd2_data = {
 	.always_present = 1,
@@ -242,8 +233,8 @@ static struct esdhc_platform_data sd2_data = {
 #endif
 
 static struct esdhc_platform_data sd3_data = {
-	.cd_gpio = GP_SD3_CD,
-	.wp_gpio = GP_SD3_WP,
+	.cd_gpio = -1,
+	.wp_gpio = -1,
 	.keep_power_at_suspend = 1,
 	.platform_pad_change = plt_sd_pad_change,
 };
@@ -260,10 +251,16 @@ static const struct anatop_thermal_platform_data
 		.name = "anatop_thermal",
 };
 
-static const struct imxuart_platform_data mx6_arm2_uart2_data __initconst = {
+/* TODO Enable all 8 lines, i.e. DTR, DSR, DCD, RI */
+static const struct imxuart_platform_data mx6_arm2_uart1_data __initconst = { /* Apalis UART 1 */
+	.flags      = IMXUART_HAVE_RTSCTS,
+};
+
+static const struct imxuart_platform_data mx6_arm2_uart2_data __initconst = { /* Apalis UART 2 */
 	.flags      = IMXUART_HAVE_RTSCTS,
 };
 
+#ifdef TODO
 #if !(defined(CSI0_CAMERA))
 static const struct imxuart_platform_data mx6_arm2_uart3_data __initconst = {
 	.flags      = IMXUART_HAVE_RTSCTS,
@@ -273,6 +270,7 @@ static const struct imxuart_platform_data mx6_arm2_uart4_data __initconst = {
 	.flags      = IMXUART_HAVE_RTSCTS,
 };
 #endif
+#endif
 
 static unsigned short ksz9031_por_cmds[] = {
 	0x0204, 0x0,		/* RX_CTL/TX_CTL output pad skew */
@@ -772,6 +770,7 @@ static struct ahci_platform_data sata_data = {
 	.exit = exit_sata,
 };
 
+#ifdef TODO
 static struct gpio flexcan_gpios[] = {
 	{ GP_CAN1_ERR, GPIOF_DIR_IN, "flexcan1-err" },
 	{ GP_CAN1_EN, GPIOF_OUT_INIT_LOW, "flexcan1-en" },
@@ -798,6 +797,7 @@ static const struct flexcan_platform_data
 	flexcan0_tja1040_pdata __initconst = {
 	.transceiver_switch = flexcan0_tja1040_switch,
 };
+#endif
 
 static struct viv_gpu_platform_data imx6_gpu_pdata __initdata = {
 	.reserved_mem_size = SZ_128M,
@@ -895,17 +895,37 @@ static void lcd_enable_pins(void)
 static void lcd_disable_pins(void)
 {
 	pr_info("%s\n", __func__);
-	IOMUX_SETUP(lcd_pads_disable);
+//	IOMUX_SETUP(lcd_pads_disable);
+}
+
+static void vga_dac_enable_pins(void)
+{
+	pr_info("%s\n", __func__);
+	IOMUX_SETUP(vga_dac_enable);
+}
+
+static void vga_dac_disable_pins(void)
+{
+	pr_info("%s\n", __func__);
+	IOMUX_SETUP(vga_dac_disable);
 }
 
 static struct fsl_mxc_lcd_platform_data lcdif_data = {
-	.ipu_id = 0,
-	.disp_id = 0,
-	.default_ifmt = IPU_PIX_FMT_RGB565,
+	.ipu_id = 1,
+	.disp_id = 1,
+	.default_ifmt = IPU_PIX_FMT_RGB24,
 	.enable_pins = lcd_enable_pins,
 	.disable_pins = lcd_disable_pins,
 };
 
+static struct fsl_mxc_lcd_platform_data vgadacif_data = {
+	.ipu_id = 1,
+	.disp_id = 0,
+	.default_ifmt = IPU_PIX_FMT_RGB565,
+	.enable_pins = vga_dac_enable_pins,
+	.disable_pins = vga_dac_disable_pins,
+};
+
 static struct fsl_mxc_ldb_platform_data ldb_data = {
 	.ipu_id = 1,
 	.disp_id = 0,
@@ -984,6 +1004,7 @@ static const struct pm_platform_data pm_data __initconst = {
 	.wakeup		= wake,					\
 }
 
+#ifdef TODO
 static struct gpio_keys_button buttons[] = {
 	GPIO_BUTTON(GP_ONOFF_KEY, KEY_POWER, 1, "key-power", 1),
 	GPIO_BUTTON(GP_MENU_KEY, KEY_MENU, 1, "key-memu", 0),
@@ -994,7 +1015,9 @@ static struct gpio_keys_button buttons[] = {
 	GPIO_BUTTON(GP_VOL_DOWN_KEY, KEY_VOLUMEDOWN, 1, "volume-down", 0),
 #endif
 };
+#endif
 
+#ifdef TODO
 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 static struct gpio_keys_platform_data button_data = {
 	.buttons	= buttons,
@@ -1025,6 +1048,7 @@ static void __init add_device_buttons(void)
 	}
 }
 #endif
+#endif /* TODO */
 
 #ifdef CONFIG_WL12XX_PLATFORM_DATA
 static void wl1271_set_power(bool enable)
@@ -1280,8 +1304,10 @@ static void __init board_init(void)
 #endif
 	IOMUX_SETUP(common_pads);
 	lcd_disable_pins();
+	//vga_dac_enable_pins();
 
 	isn6 = is_nitrogen6w();
+#ifdef TODO /* Audio */
 	if (isn6) {
 		audio_data.ext_port = 3;
 		sd3_data.wp_gpio = -1 ;
@@ -1289,6 +1315,7 @@ static void __init board_init(void)
 	} else {
 		IOMUX_SETUP(sabrelite_pads);
 	}
+#endif
 	printk(KERN_ERR "------------ Board type %s\n",
                isn6 ? "Nitrogen6X/W" : "Sabre Lite");
 
@@ -1305,8 +1332,6 @@ static void __init board_init(void)
 	soc_reg_id = dvfscore_data.soc_id;
 	pu_reg_id = dvfscore_data.pu_id;
 
-	imx6q_add_imx_uart(0, NULL);
-
 #ifdef ONE_WIRE
 	one_wire_gp = IMX_GPIO_NR(4, 5);
 	gpio_request(one_wire_gp, "one-wire-12v");
@@ -1314,14 +1339,15 @@ static void __init board_init(void)
 	gpio_export(one_wire_gp, 1);
 #endif
 
-	imx6q_add_imx_uart(1, NULL);
-	if (isn6)
-		imx6q_add_imx_uart(2, &mx6_arm2_uart2_data);
-
-#if !defined(CSI0_CAMERA)
-	imx6q_add_imx_uart(3, &mx6_arm2_uart3_data);
-	imx6q_add_imx_uart(4, &mx6_arm2_uart4_data);
-#endif
+	printk(KERN_ERR "------------ 1 \n");
+	imx6q_add_imx_uart(0, &mx6_arm2_uart1_data);
+	printk(KERN_ERR "------------ 2 \n");
+	imx6q_add_imx_uart(1, &mx6_arm2_uart2_data);
+	printk(KERN_ERR "------------ 3 \n");
+	imx6q_add_imx_uart(3, NULL); /* Apalis UART 3 */
+	printk(KERN_ERR "------------ 4 \n");
+	imx6q_add_imx_uart(4, NULL); /* Apalis UART 4 */
+	printk(KERN_ERR "------------ 5 \n");
 
 	if (!cpu_is_mx6q()) {
 		ldb_data.ipu_id = 0;
@@ -1397,8 +1423,9 @@ static void __init board_init(void)
 	imx_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk");
 	imx6q_add_asrc(&imx_asrc_data);
 
-	/* release USB Hub reset */
-	gpio_set_value(GP_USB_HUB_RESET, 1);
+	/* USB host */
+	gpio_set_value(GP_USB_HUB_VBUS, 1);
+	gpio_set_value(GP_USB_PEN, 1);
 
 	imx6q_add_mxc_pwm(0);
 	imx6q_add_mxc_pwm(1);
@@ -1415,11 +1442,14 @@ static void __init board_init(void)
 
 	imx6q_add_dvfs_core(&dvfscore_data);
 
+#ifdef TODO
 	add_device_buttons();
+#endif
 
 	imx6q_add_hdmi_soc();
 	imx6q_add_hdmi_soc_dai();
 
+#ifdef TODO
 	ret = gpio_request_array(flexcan_gpios,
 			ARRAY_SIZE(flexcan_gpios));
 	if (ret) {
@@ -1437,7 +1467,9 @@ static void __init board_init(void)
 			pr_info("Flexcan gpio_get_value CAN1_ERR failed\n");
 		}
 	}
-
+#else
+	(void) ret;
+#endif
 	clko2 = clk_get(NULL, "clko2_clk");
 	if (IS_ERR(clko2))
 		pr_err("can't get CLKO2 clock.\n");
@@ -1491,7 +1523,7 @@ static void __init timer_init(void)
 	mx6_clocks_init(32768, 24000000, 0, 0);
 
 	uart_clk = clk_get_sys("imx-uart.0", NULL);
-	early_console_setup(UART2_BASE_ADDR, uart_clk);
+	early_console_setup(UART1_BASE_ADDR, uart_clk);
 }
 
 static struct sys_timer timer __initdata = {
diff --git a/arch/arm/mach-mx6/pads-mx6_apalis_imx6.h b/arch/arm/mach-mx6/pads-mx6_apalis_imx6.h
new file mode 100644
index 000000000000..f4a1e8f99a49
--- /dev/null
+++ b/arch/arm/mach-mx6/pads-mx6_apalis_imx6.h
@@ -0,0 +1,519 @@
+#undef MX6PAD
+#undef MX6NAME
+#undef MX6
+
+//#define ONE_WIRE
+
+#ifdef FOR_DL_SOLO
+#define MX6(a) MX6DL_##a
+#define MX6PAD(a) MX6DL_PAD_##a
+#define MX6NAME(a) mx6dl_solo_##a
+#else
+#define MX6(a) MX6Q_##a
+#define MX6PAD(a) MX6Q_PAD_##a
+#define MX6NAME(a) mx6q_##a
+#endif
+
+#define MX6Q_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ	(PAD_CTL_PKE | PAD_CTL_PUE |	\
+		PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+		PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define MX6Q_USDHC_PAD_CTRL_50MHZ	MX6Q_USDHC_PAD_CTRL
+#define MX6Q_PAD_SD3_CLK__USDHC3_CLK	MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ
+#define MX6Q_PAD_SD3_CMD__USDHC3_CMD	MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ
+#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
+#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
+#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
+#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
+#define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
+#define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
+#define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
+#define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
+#define MX6Q_PAD_SD4_CLK__USDHC4_CLK	MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ
+#define MX6Q_PAD_SD4_CMD__USDHC4_CMD	MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ
+#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0	MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ
+#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1	MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ
+#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2	MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ
+#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3	MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ
+
+#define MX6DL_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ	MX6Q_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ
+#define MX6DL_USDHC_PAD_CTRL_50MHZ	MX6DL_USDHC_PAD_CTRL
+#define MX6DL_PAD_SD3_CLK__USDHC3_CLK	MX6DL_PAD_SD3_CLK__USDHC3_CLK_50MHZ
+#define MX6DL_PAD_SD3_CMD__USDHC3_CMD	MX6DL_PAD_SD3_CMD__USDHC3_CMD_50MHZ
+#define MX6DL_PAD_SD3_DAT0__USDHC3_DAT0	MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
+#define MX6DL_PAD_SD3_DAT1__USDHC3_DAT1	MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
+#define MX6DL_PAD_SD3_DAT2__USDHC3_DAT2	MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
+#define MX6DL_PAD_SD3_DAT3__USDHC3_DAT3	MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
+#define MX6DL_PAD_SD3_DAT4__USDHC3_DAT4	MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
+#define MX6DL_PAD_SD3_DAT5__USDHC3_DAT5	MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
+#define MX6DL_PAD_SD3_DAT6__USDHC3_DAT6	MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
+#define MX6DL_PAD_SD3_DAT7__USDHC3_DAT7	MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
+#define MX6DL_PAD_SD4_CLK__USDHC4_CLK	MX6DL_PAD_SD4_CLK__USDHC4_CLK_50MHZ
+#define MX6DL_PAD_SD4_CMD__USDHC4_CMD	MX6DL_PAD_SD4_CMD__USDHC4_CMD_50MHZ
+#define MX6DL_PAD_SD4_DAT0__USDHC4_DAT0	MX6DL_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ
+#define MX6DL_PAD_SD4_DAT1__USDHC4_DAT1	MX6DL_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ
+#define MX6DL_PAD_SD4_DAT2__USDHC4_DAT2	MX6DL_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ
+#define MX6DL_PAD_SD4_DAT3__USDHC4_DAT3	MX6DL_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ
+
+#define NP(id, pin, pad_ctl) \
+	NEW_PAD_CTRL(MX6PAD(SD##id##_##pin##__USDHC##id##_##pin), MX6(pad_ctl))
+
+#define SD_PINS(id, pad_ctl) \
+	NP(id, CLK, pad_ctl),	\
+	NP(id, CMD, pad_ctl),	\
+	NP(id, DAT0, pad_ctl),	\
+	NP(id, DAT1, pad_ctl),	\
+	NP(id, DAT2, pad_ctl),	\
+	NP(id, DAT3, pad_ctl)
+
+static iomux_v3_cfg_t MX6NAME(nitrogen6x_pads)[] = {
+#ifdef TODO
+	NEW_PAD_CTRL(MX6PAD(NANDF_CS1__GPIO_6_14), N6_IRQ_PADCFG),	/* wl1271 wl_irq */
+#endif
+
+#ifdef TODO
+	MX6PAD(SD1_CLK__OSC32K_32K_OUT), /* wl1271 clock */
+
+	/* UART3 for wl1271 */
+	MX6PAD(EIM_D24__UART3_TXD),
+	MX6PAD(EIM_D25__UART3_RXD),
+	MX6PAD(EIM_D23__UART3_CTS),
+	MX6PAD(EIM_D31__UART3_RTS),
+#endif
+	/* End of list */
+	0
+};
+
+static iomux_v3_cfg_t MX6NAME(common_pads)[] = {
+#ifdef TODO
+	/* CAN1  */
+	MX6PAD(KEY_ROW2__CAN1_RXCAN),
+	MX6PAD(KEY_COL2__CAN1_TXCAN),
+	MX6PAD(GPIO_2__GPIO_1_2),		/* STNDBY */
+	MX6PAD(GPIO_7__GPIO_1_7),		/* NERR */
+	NEW_PAD_CTRL(MX6PAD(GPIO_7__GPIO_1_7), CAN1_ERR_TEST_PADCFG),
+	MX6PAD(GPIO_4__GPIO_1_4),		/* Enable */
+#endif
+	/* CCM  */
+	MX6PAD(GPIO_5__CCM_CLKO),		/* local AC97 sys_mclk */
+	MX6PAD(NANDF_CS2__CCM_CLKO2),		/* MXM193 CAM1_MCLK */
+
+#ifdef TODO
+	/* ECSPI1 */
+	MX6PAD(EIM_D17__ECSPI1_MISO),
+	MX6PAD(EIM_D18__ECSPI1_MOSI),
+	MX6PAD(EIM_D16__ECSPI1_SCLK),
+	MX6PAD(EIM_D19__GPIO_3_19),	/*SS1*/
+#endif
+	/* ENET */
+	MX6PAD(ENET_MDIO__ENET_MDIO),
+	MX6PAD(ENET_MDC__ENET_MDC),
+	MX6PAD(RGMII_TXC__ENET_RGMII_TXC),
+	MX6PAD(RGMII_TD0__ENET_RGMII_TD0),
+	MX6PAD(RGMII_TD1__ENET_RGMII_TD1),
+	MX6PAD(RGMII_TD2__ENET_RGMII_TD2),
+	MX6PAD(RGMII_TD3__ENET_RGMII_TD3),
+	MX6PAD(RGMII_TX_CTL__ENET_RGMII_TX_CTL),
+	MX6PAD(ENET_REF_CLK__ENET_TX_CLK),
+	MX6PAD(RGMII_RXC__ENET_RGMII_RXC),
+	MX6PAD(RGMII_RD0__ENET_RGMII_RD0),
+	MX6PAD(RGMII_RD1__ENET_RGMII_RD1),
+	MX6PAD(RGMII_RD2__ENET_RGMII_RD2),
+	MX6PAD(RGMII_RD3__ENET_RGMII_RD3),
+	MX6PAD(RGMII_RX_CTL__ENET_RGMII_RX_CTL),
+	MX6PAD(ENET_TXD0__GPIO_1_30),		/* Micrel RGMII Phy Interrupt */
+	MX6PAD(ENET_CRS_DV__GPIO_1_25),		/* Micrel RGMII Phy Reset */
+#ifdef TODO
+	/* GPIO1 */
+	MX6PAD(ENET_RX_ER__GPIO_1_24),		/* J9 - Microphone Detect */
+
+	/* GPIO2 */
+	MX6PAD(NANDF_D1__GPIO_2_1),	/* J14 - Menu Button */
+	MX6PAD(NANDF_D2__GPIO_2_2),	/* J14 - Back Button */
+	MX6PAD(NANDF_D3__GPIO_2_3),	/* J14 - Search Button */
+	MX6PAD(NANDF_D4__GPIO_2_4),	/* J14 - Home Button */
+
+	/* GPIO4 */
+	MX6PAD(GPIO_19__GPIO_4_5),	/* J14 - Volume Down */
+#endif
+
+	/* CSI1/Bootmode pins - J12 */
+#ifdef FOR_DL_SOLO
+	/* Dualite/Solo doesn't have IPU2 */
+	MX6PAD(EIM_EB2__IPU1_CSI1_D_19),	/* GPIO2[30] */
+	MX6PAD(EIM_A23__IPU1_CSI1_D_18),	/* GPIO6[6] */
+	MX6PAD(EIM_A22__IPU1_CSI1_D_17),	/* GPIO2[16] */
+	MX6PAD(EIM_A21__IPU1_CSI1_D_16),	/* GPIO2[17] */
+	MX6PAD(EIM_A20__IPU1_CSI1_D_15),	/* GPIO2[18] */
+	MX6PAD(EIM_A19__IPU1_CSI1_D_14),	/* GPIO2[19] */
+	MX6PAD(EIM_A18__IPU1_CSI1_D_13),	/* GPIO2[20] */
+	MX6PAD(EIM_A17__IPU1_CSI1_D_12),	/* GPIO2[21] */
+	MX6PAD(EIM_EB0__IPU1_CSI1_D_11),	/* GPIO2[28] */
+	MX6PAD(EIM_EB1__IPU1_CSI1_D_10),	/* GPIO2[29] */
+	MX6PAD(EIM_DA0__IPU1_CSI1_D_9),		/* GPIO3[0] */
+	MX6PAD(EIM_DA1__IPU1_CSI1_D_8),		/* GPIO3[1] */
+	MX6PAD(EIM_DA2__IPU1_CSI1_D_7),		/* GPIO3[2] */
+	MX6PAD(EIM_DA3__IPU1_CSI1_D_6),		/* GPIO3[3] */
+	MX6PAD(EIM_DA4__IPU1_CSI1_D_5),		/* GPIO3[4] */
+	MX6PAD(EIM_DA5__IPU1_CSI1_D_4),		/* GPIO3[5] */
+	MX6PAD(EIM_DA6__IPU1_CSI1_D_3),		/* GPIO3[6] */
+	MX6PAD(EIM_DA7__IPU1_CSI1_D_2),		/* GPIO3[7] */
+	MX6PAD(EIM_DA8__IPU1_CSI1_D_1),		/* GPIO3[8] */
+	MX6PAD(EIM_DA9__IPU1_CSI1_D_0),		/* GPIO3[9] */
+	MX6PAD(EIM_DA10__IPU1_CSI1_DATA_EN),	/* GPIO3[10] */
+	MX6PAD(EIM_DA11__IPU1_CSI1_HSYNC),	/* GPIO3[11] */
+	MX6PAD(EIM_DA12__IPU1_CSI1_VSYNC),	/* GPIO3[12] */
+	MX6PAD(EIM_A16__IPU1_CSI1_PIXCLK),	/* GPIO2[22] */
+#else
+	MX6PAD(EIM_EB2__IPU2_CSI1_D_19),	/* GPIO2[30] */
+#ifdef TODO
+	MX6PAD(EIM_A23__IPU2_CSI1_D_18),	/* GPIO6[6] */
+	MX6PAD(EIM_A22__IPU2_CSI1_D_17),	/* GPIO2[16] */
+	MX6PAD(EIM_A21__IPU2_CSI1_D_16),	/* GPIO2[17] */
+	MX6PAD(EIM_A20__IPU2_CSI1_D_15),	/* GPIO2[18] */
+	MX6PAD(EIM_A19__IPU2_CSI1_D_14),	/* GPIO2[19] */
+	MX6PAD(EIM_A18__IPU2_CSI1_D_13),	/* GPIO2[20] */
+	MX6PAD(EIM_A17__IPU2_CSI1_D_12),	/* GPIO2[21] */
+	MX6PAD(EIM_EB0__IPU2_CSI1_D_11),	/* GPIO2[28] */
+	MX6PAD(EIM_EB1__IPU2_CSI1_D_10),	/* GPIO2[29] */
+	MX6PAD(EIM_DA0__IPU2_CSI1_D_9),		/* GPIO3[0] */
+	MX6PAD(EIM_DA1__IPU2_CSI1_D_8),		/* GPIO3[1] */
+	MX6PAD(EIM_DA2__IPU2_CSI1_D_7),		/* GPIO3[2] */
+	MX6PAD(EIM_DA3__IPU2_CSI1_D_6),		/* GPIO3[3] */
+	MX6PAD(EIM_DA4__IPU2_CSI1_D_5),		/* GPIO3[4] */
+	MX6PAD(EIM_DA5__IPU2_CSI1_D_4),		/* GPIO3[5] */
+	MX6PAD(EIM_DA6__IPU2_CSI1_D_3),		/* GPIO3[6] */
+	MX6PAD(EIM_DA7__IPU2_CSI1_D_2),		/* GPIO3[7] */
+	MX6PAD(EIM_DA8__IPU2_CSI1_D_1),		/* GPIO3[8] */
+	MX6PAD(EIM_DA9__IPU2_CSI1_D_0),		/* GPIO3[9] */
+	MX6PAD(EIM_DA10__IPU2_CSI1_DATA_EN),	/* GPIO3[10] */
+	MX6PAD(EIM_DA11__IPU2_CSI1_HSYNC),	/* GPIO3[11] */
+	MX6PAD(EIM_DA12__IPU2_CSI1_VSYNC),	/* GPIO3[12] */
+	MX6PAD(EIM_A16__IPU2_CSI1_PIXCLK),	/* GPIO2[22] */
+#endif
+#endif
+	MX6PAD(EIM_DA13__GPIO_3_13),		/* Power */
+	MX6PAD(EIM_DA14__GPIO_3_14),		/* Reset */
+	MX6PAD(EIM_WAIT__GPIO_5_0),		/* Irq */
+#ifdef TODO
+	MX6PAD(EIM_A24__GPIO_5_4),		/* Field */
+#endif
+	MX6PAD(EIM_RW__GPIO_2_26),		/* GPIO2[26] - unused */
+	MX6PAD(EIM_LBA__GPIO_2_27),		/* GPIO2[27] - unused */
+#ifdef TODO
+	MX6PAD(EIM_EB3__GPIO_2_31),		/* GPIO2[31] - unused */
+#endif
+	MX6PAD(EIM_DA15__GPIO_3_15),		/* GPIO3[15] - unused */
+
+	/* NANDF_CS1/2/3 are unused for sabrelite */
+	NEW_PAD_CTRL(MX6PAD(NANDF_CS1__GPIO_6_14), N6_IRQ_TEST_PADCFG),	/* wl1271 wl_irq */
+	NEW_PAD_CTRL(MX6PAD(NANDF_CS3__GPIO_6_16), N6_EN_PADCFG),	/* wl1271 bt_en */
+
+	/* GPIO7 */
+	MX6PAD(GPIO_17__GPIO_7_12),	/* USB Hub Reset */
+	MX6PAD(GPIO_18__GPIO_7_13),	/* J14 - Volume Up */
+
+	/* I2C1, SGTL5000 */
+#ifdef TODO
+	MX6PAD(EIM_D21__I2C1_SCL),	/* GPIO3[21] */
+	MX6PAD(EIM_D28__I2C1_SDA),	/* GPIO3[28] */
+
+	/* I2C2 Camera, MIPI */
+	MX6PAD(KEY_COL3__I2C2_SCL),	/* GPIO4[12] */
+	MX6PAD(KEY_ROW3__I2C2_SDA),	/* GPIO4[13] */
+#endif
+	/* I2C3 */
+#ifdef TODO
+	MX6PAD(GPIO_5__I2C3_SCL),	/* GPIO1[5] - J7 - Display card */
+#endif
+#ifdef CONFIG_FEC_1588
+	MX6PAD(GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT),
+#else
+#ifdef TODO
+	MX6PAD(GPIO_16__I2C3_SDA),	/* GPIO7[11] - J15 - RGB connector */
+#endif
+#endif
+
+	/* DISPLAY */
+	NEW_PAD_CTRL(MX6PAD(DI0_PIN4__GPIO_4_20),
+		     WEAK_PULLUP),			/* I2C Touch IRQ */
+	MX6PAD(GPIO_7__GPIO_1_7),		/* J7 - Display Connector GP */
+	MX6PAD(GPIO_9__GPIO_1_9),		/* J7 - Display Connector GP */
+#ifdef TODO
+	MX6PAD(NANDF_D0__GPIO_2_0),		/* J6 - LVDS Display contrast */
+#endif
+
+#ifdef TODO
+	/* PWM1 */
+	MX6PAD(SD1_DAT3__PWM1_PWMO),		/* GPIO1[21] */
+
+	/* PWM2 */
+	MX6PAD(SD1_DAT2__PWM2_PWMO),		/* GPIO1[19] */
+
+	/* PWM3 */
+	MX6PAD(SD1_DAT1__PWM3_PWMO),		/* GPIO1[17] */
+
+	/* PWM4 */
+	MX6PAD(SD1_CMD__PWM4_PWMO),		/* GPIO1[18] */
+#endif
+	/* RTC ISL1208 irq*/
+	MX6PAD(NANDF_CLE__GPIO_6_7),
+
+	/* Apalis UART1 */
+#if 0 /* ONE_WIRE */
+	NEW_PAD_CTRL(MX6PAD(SD3_DAT7__UART1_TXD), 0x0001f8b1),
+	NEW_PAD_CTRL(MX6PAD(SD3_DAT6__UART1_RXD), 0x0001f0b1),
+#else
+	MX6PAD(CSI0_DAT10__UART1_TXD),
+	MX6PAD(CSI0_DAT11__UART1_RXD),
+	MX6PAD(EIM_D19__UART1_CTS),
+	MX6PAD(EIM_D20__UART1_RTS),
+	MX6PAD(EIM_D23__UART1_DCD),
+	MX6PAD(EIM_D24__UART1_DTR),
+	MX6PAD(EIM_D25__UART1_DSR),
+	MX6PAD(EIM_EB3__UART1_RI),
+#endif
+
+	/*Apalis UART2 */
+	MX6PAD(SD4_DAT4__UART2_RXD),
+	MX6PAD(SD4_DAT5__UART2_RTS),
+	MX6PAD(SD4_DAT6__UART2_CTS),
+	MX6PAD(SD4_DAT7__UART2_TXD),
+
+	/*Apalis UART3 */
+	MX6PAD(KEY_COL0__UART4_TXD),
+	MX6PAD(KEY_ROW0__UART4_RXD),
+
+	/*Apalis UART4 */
+	MX6PAD(KEY_COL1__UART5_TXD),
+	MX6PAD(KEY_ROW1__UART5_RXD),
+
+	/* Apalis, AUDMUX, local AC97 */
+	MX6PAD(DISP0_DAT23__AUDMUX_AUD4_RXD),
+	MX6PAD(DISP0_DAT20__AUDMUX_AUD4_TXC),
+	MX6PAD(DISP0_DAT21__AUDMUX_AUD4_TXD),
+	MX6PAD(DISP0_DAT22__AUDMUX_AUD4_TXFS),
+	/* Apalis MMC1 */
+	SD_PINS(1, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ),
+	NEW_PAD_CTRL(MX6PAD(NANDF_D0__USDHC1_DAT4), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)),
+	NEW_PAD_CTRL(MX6PAD(NANDF_D1__USDHC1_DAT5), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)),
+	NEW_PAD_CTRL(MX6PAD(NANDF_D2__USDHC1_DAT6), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)),
+	NEW_PAD_CTRL(MX6PAD(NANDF_D3__USDHC1_DAT7), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)),
+	/* Apalis eMMC */
+	SD_PINS(3, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ),
+	NEW_PAD_CTRL(MX6PAD(SD3_DAT4__USDHC3_DAT4), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)),
+	NEW_PAD_CTRL(MX6PAD(SD3_DAT5__USDHC3_DAT5), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)),
+	NEW_PAD_CTRL(MX6PAD(SD3_DAT6__USDHC3_DAT6), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)),
+	NEW_PAD_CTRL(MX6PAD(SD3_DAT7__USDHC3_DAT7), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)),
+	MX6PAD(SD3_RST__USDHC3_RST),
+	/* Apalis SD1 */
+	SD_PINS(2, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ),
+
+
+	/* USBOTG ID pin */
+	MX6PAD(ENET_RX_ER__ANATOP_USBOTG_ID),
+
+	/* USB OC pin */
+	MX6PAD(EIM_D21__USBOH3_USBOTG_OC),
+	MX6PAD(GPIO_3__USBOH3_USBH1_OC),
+	0
+};
+
+/* Apalis MXM LCD1 */
+static iomux_v3_cfg_t MX6NAME(lcd_pads_enable)[] = {
+	MX6PAD(EIM_A16__IPU1_DI1_DISP_CLK),
+	MX6PAD(EIM_DA10__IPU1_DI1_PIN15),		/* DE */
+	MX6PAD(EIM_DA11__IPU1_DI1_PIN2),		/* HSync */
+	MX6PAD(EIM_DA12__IPU1_DI1_PIN3),		/* VSync */
+	MX6PAD(EIM_DA9__IPU1_DISP1_DAT_0),
+	MX6PAD(EIM_DA8__IPU1_DISP1_DAT_1),
+	MX6PAD(EIM_DA7__IPU1_DISP1_DAT_2),
+	MX6PAD(EIM_DA6__IPU1_DISP1_DAT_3),
+	MX6PAD(EIM_DA5__IPU1_DISP1_DAT_4),
+	MX6PAD(EIM_DA4__IPU1_DISP1_DAT_5),
+	MX6PAD(EIM_DA3__IPU1_DISP1_DAT_6),
+	MX6PAD(EIM_DA2__IPU1_DISP1_DAT_7),
+	MX6PAD(EIM_DA1__IPU1_DISP1_DAT_8),
+	MX6PAD(EIM_DA0__IPU1_DISP1_DAT_9),
+	MX6PAD(EIM_EB1__IPU1_DISP1_DAT_10),
+	MX6PAD(EIM_EB0__IPU1_DISP1_DAT_11),
+	MX6PAD(EIM_A17__IPU1_DISP1_DAT_12),
+	MX6PAD(EIM_A18__IPU1_DISP1_DAT_13),
+	MX6PAD(EIM_A19__IPU1_DISP1_DAT_14),
+	MX6PAD(EIM_A20__IPU1_DISP1_DAT_15),
+	MX6PAD(EIM_A21__IPU1_DISP1_DAT_16),
+	MX6PAD(EIM_A22__IPU1_DISP1_DAT_17),
+	MX6PAD(EIM_A23__IPU1_DISP1_DAT_18),
+	MX6PAD(EIM_A24__IPU1_DISP1_DAT_19),
+	MX6PAD(EIM_D31__IPU1_DISP1_DAT_20),
+	MX6PAD(EIM_D30__IPU1_DISP1_DAT_21),
+	MX6PAD(EIM_D26__IPU1_DISP1_DAT_22),
+	MX6PAD(EIM_D27__IPU1_DISP1_DAT_23),
+	0
+};
+
+static iomux_v3_cfg_t MX6NAME(lcd_pads_disable)[] = {
+	MX6PAD(EIM_A16__GPIO_2_22),
+	MX6PAD(EIM_DA10__GPIO_3_10),		/* DE */
+	MX6PAD(EIM_DA11__GPIO_3_11),		/* HSync */
+	MX6PAD(EIM_DA12__GPIO_3_12),		/* VSync */
+	MX6PAD(EIM_DA9__GPIO_3_9),
+	MX6PAD(EIM_DA8__GPIO_3_8),
+	MX6PAD(EIM_DA7__GPIO_3_7),
+	MX6PAD(EIM_DA6__GPIO_3_6),
+	MX6PAD(EIM_DA5__GPIO_3_5),
+	MX6PAD(EIM_DA4__GPIO_3_4),
+	MX6PAD(EIM_DA3__GPIO_3_3),
+	MX6PAD(EIM_DA2__GPIO_3_2),
+	MX6PAD(EIM_DA1__GPIO_3_1),
+	MX6PAD(EIM_DA0__GPIO_3_0),
+	MX6PAD(EIM_EB1__GPIO_2_29),
+	MX6PAD(EIM_EB0__GPIO_2_28),
+	MX6PAD(EIM_A17__GPIO_2_21),
+	MX6PAD(EIM_A18__GPIO_2_20),
+	MX6PAD(EIM_A19__GPIO_2_19),
+	MX6PAD(EIM_A20__GPIO_2_18),
+	MX6PAD(EIM_A21__GPIO_2_17),
+	MX6PAD(EIM_A22__GPIO_2_16),
+	MX6PAD(EIM_A23__GPIO_6_6),
+	MX6PAD(EIM_A24__GPIO_5_4),
+	MX6PAD(EIM_D31__GPIO_3_31),
+	MX6PAD(EIM_D30__GPIO_3_30),
+	MX6PAD(EIM_D26__GPIO_3_26),
+	MX6PAD(EIM_D27__GPIO_3_27),
+	0
+};
+
+/* Apalis MXM VGA DAC */
+static iomux_v3_cfg_t MX6NAME(vga_dac_enable)[] = {
+	MX6PAD(DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
+	MX6PAD(DI0_PIN2__IPU1_DI0_PIN2),		/* HSync */
+	MX6PAD(DI0_PIN3__IPU1_DI0_PIN3),		/* VSync */
+	MX6PAD(DISP0_DAT0__IPU1_DISP0_DAT_0),
+	MX6PAD(DISP0_DAT1__IPU1_DISP0_DAT_1),
+	MX6PAD(DISP0_DAT2__IPU1_DISP0_DAT_2),
+	MX6PAD(DISP0_DAT3__IPU1_DISP0_DAT_3),
+	MX6PAD(DISP0_DAT4__IPU1_DISP0_DAT_4),
+	MX6PAD(DISP0_DAT5__IPU1_DISP0_DAT_5),
+	MX6PAD(DISP0_DAT6__IPU1_DISP0_DAT_6),
+	MX6PAD(DISP0_DAT7__IPU1_DISP0_DAT_7),
+	MX6PAD(DISP0_DAT8__IPU1_DISP0_DAT_8),
+	MX6PAD(DISP0_DAT9__IPU1_DISP0_DAT_9),
+	MX6PAD(DISP0_DAT10__IPU1_DISP0_DAT_10),
+	MX6PAD(DISP0_DAT11__IPU1_DISP0_DAT_11),
+	MX6PAD(DISP0_DAT12__IPU1_DISP0_DAT_12),
+	MX6PAD(DISP0_DAT13__IPU1_DISP0_DAT_13),
+	MX6PAD(DISP0_DAT14__IPU1_DISP0_DAT_14),
+	MX6PAD(DISP0_DAT15__IPU1_DISP0_DAT_15),
+	0
+};
+
+static iomux_v3_cfg_t MX6NAME(vga_dac_disable)[] = {
+	MX6PAD(DI0_DISP_CLK__GPIO_4_16),
+	MX6PAD(DI0_PIN2__GPIO_4_18),			/* HSync */
+	MX6PAD(DI0_PIN3__GPIO_4_19),			/* VSync */
+	MX6PAD(DISP0_DAT0__GPIO_4_21),
+	MX6PAD(DISP0_DAT1__GPIO_4_22),
+	MX6PAD(DISP0_DAT2__GPIO_4_23),
+	MX6PAD(DISP0_DAT3__GPIO_4_24),
+	MX6PAD(DISP0_DAT4__GPIO_4_25),
+	MX6PAD(DISP0_DAT5__GPIO_4_26),
+	MX6PAD(DISP0_DAT6__GPIO_4_27),
+	MX6PAD(DISP0_DAT7__GPIO_4_28),
+	MX6PAD(DISP0_DAT8__GPIO_4_29),
+	MX6PAD(DISP0_DAT9__GPIO_4_30),
+	MX6PAD(DISP0_DAT10__GPIO_4_31),
+	MX6PAD(DISP0_DAT11__GPIO_5_5),
+	MX6PAD(DISP0_DAT12__GPIO_5_6),
+	MX6PAD(DISP0_DAT13__GPIO_5_7),
+	MX6PAD(DISP0_DAT14__GPIO_5_8),
+	MX6PAD(DISP0_DAT15__GPIO_5_9),
+	0
+};
+
+#if defined(CONFIG_MXC_CAMERA_OV5640_MIPI) || defined(CONFIG_MXC_CAMERA_OV5640_MIPI_MODULE)
+static iomux_v3_cfg_t MX6NAME(mipi_pads)[] = {
+	MX6PAD(NANDF_WP_B__GPIO_6_9),		/* J16 - MIPI Powerdown - Nitrogen6x, SOM is NC */
+	MX6PAD(NANDF_D5__GPIO_2_5),		/* J16 - MIPI camera reset - Nitrogen6x/SOM */
+	MX6PAD(NANDF_CS0__GPIO_6_11),		/* Camera Reset, SOM jumpered */
+	MX6PAD(GPIO_6__GPIO_1_6),		/* Camera GP */
+	0
+};
+#endif
+
+#if defined(CSI0_CAMERA)
+static iomux_v3_cfg_t MX6NAME(csi0_sensor_pads)[] = {
+	/* IPU1 Camera */
+	MX6PAD(CSI0_DAT8__IPU1_CSI0_D_8),
+	MX6PAD(CSI0_DAT9__IPU1_CSI0_D_9),
+	MX6PAD(CSI0_DAT10__IPU1_CSI0_D_10),
+	MX6PAD(CSI0_DAT11__IPU1_CSI0_D_11),
+	MX6PAD(CSI0_DAT12__IPU1_CSI0_D_12),
+	MX6PAD(CSI0_DAT13__IPU1_CSI0_D_13),
+	MX6PAD(CSI0_DAT14__IPU1_CSI0_D_14),
+	MX6PAD(CSI0_DAT15__IPU1_CSI0_D_15),
+	MX6PAD(CSI0_DAT16__IPU1_CSI0_D_16),
+	MX6PAD(CSI0_DAT17__IPU1_CSI0_D_17),
+	MX6PAD(CSI0_DAT18__IPU1_CSI0_D_18),
+	MX6PAD(CSI0_DAT19__IPU1_CSI0_D_19),
+	MX6PAD(CSI0_DATA_EN__IPU1_CSI0_DATA_EN),
+	MX6PAD(CSI0_MCLK__IPU1_CSI0_HSYNC),
+	MX6PAD(CSI0_PIXCLK__IPU1_CSI0_PIXCLK),
+	MX6PAD(CSI0_VSYNC__IPU1_CSI0_VSYNC),
+	MX6PAD(GPIO_6__GPIO_1_6),		/* J5 - Camera GP */
+	MX6PAD(GPIO_8__GPIO_1_8),		/* J5 - Camera Reset */
+	MX6PAD(NANDF_CS0__GPIO_6_11),		/* J5 - Camera Reset */
+	MX6PAD(SD1_DAT0__GPIO_1_16),		/* J5 - Camera GP */
+	0
+};
+#endif
+
+static iomux_v3_cfg_t MX6NAME(hdmi_ddc_pads)[] = {
+	MX6PAD(KEY_COL3__HDMI_TX_DDC_SCL), /* HDMI DDC SCL */
+	MX6PAD(KEY_ROW3__HDMI_TX_DDC_SDA), /* HDMI DDC SDA */
+	0
+};
+/* TODO fix that i2c mess */
+static iomux_v3_cfg_t MX6NAME(i2c2_pads)[] = {
+#ifdef TODO
+	MX6PAD(KEY_COL3__I2C2_SCL),	/* I2C2 SCL */
+	MX6PAD(KEY_ROW3__I2C2_SDA),	/* I2C2 SDA */
+#endif
+	0
+};
+
+#ifdef TODO
+static iomux_v3_cfg_t MX6NAME(mc33902_flexcan_pads)[] = {
+	NEW_PAD_CTRL(MX6PAD(GPIO_7__GPIO_1_7), CAN1_ERR_PADCFG),
+	0
+};
+#endif
+#define MX6_USDHC_PAD_SETTING(id, speed, pad_ctl)	\
+		MX6NAME(sd##id##_##speed##mhz)[] = { SD_PINS(id, pad_ctl), 0 }
+
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 50, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ);
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 100, USDHC_PAD_CTRL_100MHZ);
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 200, USDHC_PAD_CTRL_200MHZ);
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(3, 50, USDHC_PAD_CTRL_50MHZ);
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(3, 100, USDHC_PAD_CTRL_100MHZ);
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(3, 200, USDHC_PAD_CTRL_200MHZ);
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(4, 50, USDHC_PAD_CTRL_50MHZ);
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(4, 100, USDHC_PAD_CTRL_100MHZ);
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(4, 200, USDHC_PAD_CTRL_200MHZ);
+
+#define _50MHZ 0
+#define _100MHZ 1
+#define _200MHZ 2
+#define SD_SPEED_CNT 3
+static iomux_v3_cfg_t * MX6NAME(sd_pads)[] =
+{
+	MX6NAME(sd2_50mhz),
+	MX6NAME(sd2_100mhz),
+	MX6NAME(sd2_200mhz),
+	MX6NAME(sd3_50mhz),
+	MX6NAME(sd3_100mhz),
+	MX6NAME(sd3_200mhz),
+	MX6NAME(sd4_50mhz),
+	MX6NAME(sd4_100mhz),
+	MX6NAME(sd4_200mhz),
+};