[arm/tegra] suspend: add more config for LP0

Following pmc registers configuration are added before entering
deep power down (LP0):
DPD_SAMPLE: Enabling sampling of pads before entering into LP0.
DPD_ORIDE: Providing api to configure the kbc pins override before
LP0.

After LP0 wakeup, clearing the DPD_SAMPLE as per programming
guidelines.

Cherry-picked change 65675bde4a20bbb8fde86d2629d125fcd084f8db

Change-Id: Ia3b5d6a29e626186315dfb199709b73099b04bfb
Reviewed-on: http://git-master/r/3533
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

2 files changed, 52 insertions, 1 deletions

diff --git a/arch/arm/mach-tegra/include/mach/pmc.h b/arch/arm/mach-tegra/include/mach/pmc.h
new file mode 100644
index 000000000000..986bde20f8b2
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pmc.h
@@ -0,0 +1,34 @@
+/*
+ * arch/arm/mach-tegra/include/mach/pmc.h
+ *
+ * Copyright (c) 2009-2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MACH_TEGRA_PMC_H
+#define __MACH_TEGRA_PMC_H
+
+/**
+ * Configure the kbc used pins for the deep power down mode.
+ * The enabled row and column will be passed as parameter.
+ * kbc_rows: The set bit position on this tells that corresponding row is
+ *           enabled. Bit 0 corresponds to row 0.
+ * kbc_cols: The set bit position on this tells that corresponding col is
+ *           enabled. Bit 0 corresponds to col 0.
+ */
+void tegra_configure_dpd_kbc(unsigned int kbc_rows, unsigned int kbc_cols);
+
+#endif
diff --git a/arch/arm/mach-tegra/suspend.c b/arch/arm/mach-tegra/suspend.c
index d40386313d01..132bc545365f 100644
--- a/arch/arm/mach-tegra/suspend.c
+++ b/arch/arm/mach-tegra/suspend.c
@@ -42,6 +42,7 @@
 #include <mach/iovmm.h>
 #include <mach/irqs.h>
 #include <mach/nvrm_linux.h>
+#include <mach/pmc.h>
 
 #include <nvrm_memmgr.h>
 #include <nvrm_power_private.h>
@@ -75,6 +76,9 @@ static void __iomem *tmrus = IO_ADDRESS(TEGRA_TMRUS_BASE);
 #define PMC_CTRL_LATCH_WAKEUPS	(1 << 5)
 #define PMC_WAKE_MASK		0xc
 #define PMC_WAKE_LEVEL		0x10
+#define PMC_DPAD_ORIDE		0x1C
+#define PMC_WAKE_DELAY		0xe0
+#define PMC_DPD_SAMPLE  	0x20
 
 #define PMC_SW_WAKE_STATUS	0x18
 #define PMC_COREPWRGOOD_TIMER	0x3c
@@ -82,7 +86,7 @@ static void __iomem *tmrus = IO_ADDRESS(TEGRA_TMRUS_BASE);
 #define PMC_SCRATCH1		0x54
 #define PMC_CPUPWRGOOD_TIMER	0xc8
 #define PMC_CPUPWROFF_TIMER	0xcc
-#define PMC_COREPWROFF_TIMER	0xe0
+#define PMC_COREPWROFF_TIMER	PMC_WAKE_DELAY
 #define PMC_SCRATCH38		0x134
 #define PMC_SCRATCH39		0x138
 
@@ -319,7 +323,12 @@ static void tegra_setup_wakepads(bool lp0_ok)
 	lvl ^= status;
 
 	writel(lvl, pmc + PMC_WAKE_LEVEL);
+	/* Enable DPD sample to trigger sampling pads data and direction
+	 * in which pad will be driven during lp0 mode*/
+	writel(0x1, pmc + PMC_DPD_SAMPLE);
+
 	writel(pdata->wake_enb, pmc + PMC_WAKE_MASK);
+
 }
 
 extern void __tegra_lp1_reset(void);
@@ -614,6 +623,9 @@ static int tegra_suspend_enter(suspend_state_t state)
 		}
 	}
 
+	/* Clear DPD sample */
+	writel(0x0, pmc + PMC_DPD_SAMPLE);
+
 	if (pdata->core_off) {
 		writel(mc_data[0], mc + MC_SECURITY_START);
 		writel(mc_data[1], mc + MC_SECURITY_SIZE);
@@ -686,3 +698,8 @@ void __init tegra_init_suspend(struct tegra_suspend_platform_data *plat)
 	suspend_set_ops(&tegra_suspend_ops);
 #endif
 }
+
+void tegra_configure_dpd_kbc(unsigned int kbc_rows, unsigned int kbc_cols)
+{
+	writel((kbc_rows & 0xFFFF), pmc + PMC_DPAD_ORIDE);
+}