diff options
| author | Fugang Duan <b38611@freescale.com> | 2015-04-23 17:43:43 +0800 |
|---|---|---|
| committer | Frank Li <Frank.Li@freescale.com> | 2015-04-24 23:04:20 +0800 |
| commit | 4a96730b90b8a61036d0a86ccaa458e0c1aa9212 (patch) | |
| tree | 48a60c26af180015e7cb7891b8be62d8a74fbf81 | |
| parent | 07e4deaa68e4f71de4a6cbb9c982f5da337dab7a (diff) | |
MLK-10735 ARM: dts: imx7d-sdb: add uart5 DTE pin setting
Add uart5 DTE pin setting.
Signed-off-by: Fugang Duan <B38611@freescale.com>
| -rw-r--r-- | arch/arm/boot/dts/imx7d-sdb.dts | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 91973adb98a7..1daa265d0eda 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -670,6 +670,15 @@ >; }; + pinctrl_uart5dte: uart5dtegrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x79 + MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x79 + MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS 0x79 + MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS 0x79 + >; + }; + pinctrl_uart6: uart6grp { fsl,pins = < MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 @@ -863,6 +872,9 @@ assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart5dte>; */ status = "okay"; }; |