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authorDiwakar Tundlam <dtundlam@nvidia.com>2011-08-08 11:55:15 -0700
committerRyan Wong <ryanw@nvidia.com>2011-08-10 18:37:02 -0700
commit0a7255bd9124cedf7522abda04b9381cb5dfcfbb (patch)
treeb3b0198dc513b1467d8d6392b67125ff2464e0ca
parent48e85f6bccf0ede895fd361a8268a88a32fd339e (diff)
ARM: Tegra: cpu: Set G-CPU L2 cache latency to 0x441/551
Experimental build using data/tag latency set to 0x441/0x551 Bugid 860893 Change-Id: I712603f3e5eaa9d32970c44da9ae2f5ff23ac620 Reviewed-on: http://git-master/r/46493 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Tested-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Ryan Wong <ryanw@nvidia.com> Tested-by: Ryan Wong <ryanw@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/common.c4
-rw-r--r--arch/arm/mach-tegra/cortex-a9.S4
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 3a148c2cb261..812374e7c7ac 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -194,8 +194,8 @@ void __init tegra_init_cache(void)
writel(0x221, p + L2X0_TAG_LATENCY_CTRL);
writel(0x221, p + L2X0_DATA_LATENCY_CTRL);
} else {
- writel(0x331, p + L2X0_TAG_LATENCY_CTRL);
- writel(0x441, p + L2X0_DATA_LATENCY_CTRL);
+ writel(0x441, p + L2X0_TAG_LATENCY_CTRL);
+ writel(0x551, p + L2X0_DATA_LATENCY_CTRL);
}
#else
writel(0x770, p + L2X0_TAG_LATENCY_CTRL);
diff --git a/arch/arm/mach-tegra/cortex-a9.S b/arch/arm/mach-tegra/cortex-a9.S
index 6a9d318b5fe9..4b0df3f9cbe7 100644
--- a/arch/arm/mach-tegra/cortex-a9.S
+++ b/arch/arm/mach-tegra/cortex-a9.S
@@ -661,8 +661,8 @@ ENTRY(__cortex_a9_l2x0_restart)
mov32 r5, (TEGRA_FLOW_CTRL_BASE-IO_PPSB_PHYS+IO_PPSB_VIRT)
ldr r5, [r5, #0x2C] @ FLOW_CTRL_CLUSTER_CONTROL
ands r5, r5, #1 @ 0 == G cluster, 1 == LP cluster
- movweq r5, #0x331 @ G tag
- movweq r6, #0x441 @ G data
+ movweq r5, #0x441 @ G tag
+ movweq r6, #0x551 @ G data
movwne r5, #0x221 @ LP tag
movwne r6, #0x221 @ LP data
#endif