diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2010-12-03 17:53:35 -0600 |
|---|---|---|
| committer | Ranjani Vaidyanathan <ra5478@freescale.com> | 2010-12-03 17:55:35 -0600 |
| commit | 35f5c2725c403bebfb41a39dd02d85a42cec9f7f (patch) | |
| tree | c4057f05aa2a73f63d34141866a2f2f973cd6e9d | |
| parent | 421b2eb47e3bf15973939d2906b8f1ac7b15c1a9 (diff) | |
ENGR000135959: MX50: Relock PLL1 to 160MHz in LPAPM mode.
In LPAPM mode, DDR is sourced from 24MHz OSC. Since only ARM clock is
sourced from PLL1, relock it to 160MHz to save some power.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx5/bus_freq.c | 26 | ||||
| -rw-r--r-- | arch/arm/mach-mx5/clock_mx50.c | 1 |
2 files changed, 26 insertions, 1 deletions
diff --git a/arch/arm/mach-mx5/bus_freq.c b/arch/arm/mach-mx5/bus_freq.c index 12d2e802d882..82f996aaf9a5 100644 --- a/arch/arm/mach-mx5/bus_freq.c +++ b/arch/arm/mach-mx5/bus_freq.c @@ -156,7 +156,7 @@ int set_low_bus_freq(void) if (bus_freq_scaling_initialized) { /* can not enter low bus freq, when cpu is in highest freq */ - if (clk_get_rate(cpu_clk) != + if (clk_get_rate(cpu_clk) > cpu_wp_tbl[cpu_wp_nr - 1].cpu_rate) { return 0; } @@ -305,6 +305,17 @@ void enter_lpapm_mode_mx50() queue_work(voltage_wq, &voltage_change_handler); spin_unlock_irqrestore(&voltage_lock, flags); + if (clk_get_usecount(pll1_sw_clk) == 1) { + /* Relock PLL1 to 160MHz. */ + clk_set_parent(pll1_sw_clk, pll2); + /* Set the divider to ARM_PODF to 3. */ + __raw_writel(0x02, MXC_CCM_CACRR); + + clk_set_rate(pll1, 160000000); + clk_set_parent(pll1_sw_clk, pll1); + /* Set the divider to ARM_PODF to 1. */ + __raw_writel(0x0, MXC_CCM_CACRR); + } udelay(100); } @@ -462,6 +473,18 @@ void exit_lpapm_mode_mx50() u32 reg; unsigned long flags; + if (clk_get_usecount(pll1_sw_clk) == 1) { + /* Relock PLL1 to 800MHz. */ + clk_set_parent(pll1_sw_clk, pll2); + /* Set the divider to ARM_PODF to 3, cpu is at 160MHz. */ + __raw_writel(0x02, MXC_CCM_CACRR); + + clk_set_rate(pll1, 800000000); + clk_set_parent(pll1_sw_clk, pll1); + /* Set the divider to ARM_PODF to 5. */ + __raw_writel(0x4, MXC_CCM_CACRR); + } + if (!completion_done(&voltage_change_cmpl)) wait_for_completion_interruptible(&voltage_change_cmpl); spin_lock_irqsave(&voltage_lock, flags); @@ -543,6 +566,7 @@ void exit_lpapm_mode_mx50() __raw_writel(reg, qosc_base + HW_QOS_DISABLE); spin_unlock_irqrestore(&ddr_freq_lock, flags); + udelay(100); } diff --git a/arch/arm/mach-mx5/clock_mx50.c b/arch/arm/mach-mx5/clock_mx50.c index d33a42e5db9f..0d2e472f7780 100644 --- a/arch/arm/mach-mx5/clock_mx50.c +++ b/arch/arm/mach-mx5/clock_mx50.c @@ -643,6 +643,7 @@ static void _clk_pll_disable(struct clk *clk) static struct clk pll1_main_clk = { .parent = &osc_clk, .get_rate = _clk_pll_get_rate, + .set_rate = _clk_pll_set_rate, .enable = _clk_pll_enable, .disable = _clk_pll_disable, .flags = RATE_PROPAGATES, |