diff options
| author | Luke Huang <lhuang@nvidia.com> | 2011-01-27 13:14:44 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:41:59 -0800 |
| commit | 673bb291bd7d06ccf4e5a6664bae4e9f32e18a99 (patch) | |
| tree | bdde786862cf4ccdb6dbef784e39ddfeb7642167 | |
| parent | daaab6fa879a5e1be302015c14d82e3d23023b94 (diff) | |
video: tegra: dsi: Added dsi support.
Bug 793366
Bug 794499
Original-Change-Id: Id49d86dd7760b75ef4947f5bdab9e37f0333391d
Reviewed-on: http://git-master/r/#change,18950
Reviewed-on: http://git-master/r/22508
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R968aab8a752d3d253216935839e94fdbd7fc6ba4
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/iomap.h | 3 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 19 |
2 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h index ac3eb87782aa..fa214ff94f4f 100644 --- a/arch/arm/mach-tegra/include/mach/iomap.h +++ b/arch/arm/mach-tegra/include/mach/iomap.h @@ -56,6 +56,9 @@ #define TEGRA_HDMI_BASE 0x54280000 #define TEGRA_HDMI_SIZE SZ_256K +#define TEGRA_DSI_BASE 0x54300000 +#define TEGRA_DSI_SIZE SZ_256K + #define TEGRA_GART_BASE 0x58000000 #define TEGRA_GART_SIZE SZ_32M diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index d1db92c466c9..8c1c45e36167 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -660,6 +660,12 @@ static int tegra2_pll_clk_enable(struct clk *c) val |= PLL_BASE_ENABLE; clk_writel(val, c->reg + PLL_BASE); + if (c->flags & PLLD) { + val = clk_readl(c->reg + PLL_MISC(c) + PLL_BASE); + val |= PLLD_MISC_CLKENABLE; + clk_writel(val, c->reg + PLL_MISC(c) + PLL_BASE); + } + tegra2_pll_clk_wait_for_lock(c); return 0; @@ -673,6 +679,12 @@ static void tegra2_pll_clk_disable(struct clk *c) val = clk_readl(c->reg); val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); clk_writel(val, c->reg); + + if (c->flags & PLLD) { + val = clk_readl(c->reg + PLL_MISC(c) + PLL_BASE); + val &= ~PLLD_MISC_CLKENABLE; + clk_writel(val, c->reg + PLL_MISC(c) + PLL_BASE); + } } static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate) @@ -1653,6 +1665,11 @@ static struct clk_pll_freq_table tegra_pll_d_freq_table[] = { { 19200000, 216000000, 135, 12, 1, 3}, { 26000000, 216000000, 216, 26, 1, 4}, + { 12000000, 5000000, 10, 24, 1, 4}, + { 12000000, 10000000, 10, 12, 1, 4}, + { 12000000, 161500000, 323, 24, 1, 4}, + { 12000000, 162000000, 162, 12, 1, 4}, + { 12000000, 594000000, 594, 12, 1, 8}, { 13000000, 594000000, 594, 13, 1, 8}, { 19200000, 594000000, 495, 16, 1, 8}, @@ -2251,6 +2268,8 @@ struct clk_duplicate tegra_clk_duplicates[] = { CLK_DUPLICATE("usbd", "tegra-otg", NULL), CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"), CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"), + CLK_DUPLICATE("dsi", "tegradc.0", "dsi"), + CLK_DUPLICATE("dsi", "tegradc.1", "dsi"), CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL), CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL), CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL), |