board-mx6_s: Add GPIO pins, CSPI2

1 files changed, 17 insertions, 53 deletions

diff --git a/arch/arm/mach-mx6/pads-mx6_s.h b/arch/arm/mach-mx6/pads-mx6_s.h
index c6d5e0ba926a..431e77801f73 100644
--- a/arch/arm/mach-mx6/pads-mx6_s.h
+++ b/arch/arm/mach-mx6/pads-mx6_s.h
@@ -126,59 +126,23 @@ static iomux_v3_cfg_t MX6NAME(common_pads)[] = {
 	MX6PAD(GPIO_19__GPIO_4_5),	/* J14 - Volume Down */
 
 
-	/* CSI1/Bootmode pins - J12 */
-#ifdef FOR_DL_SOLO
-	/* Dualite/Solo doesn't have IPU2 */
-	MX6PAD(EIM_EB2__IPU1_CSI1_D_19),	/* GPIO2[30] */
-	MX6PAD(EIM_A23__IPU1_CSI1_D_18),	/* GPIO6[6] */
-	MX6PAD(EIM_A22__IPU1_CSI1_D_17),	/* GPIO2[16] */
-	MX6PAD(EIM_A21__IPU1_CSI1_D_16),	/* GPIO2[17] */
-	MX6PAD(EIM_A20__IPU1_CSI1_D_15),	/* GPIO2[18] */
-	MX6PAD(EIM_A19__IPU1_CSI1_D_14),	/* GPIO2[19] */
-	MX6PAD(EIM_A18__IPU1_CSI1_D_13),	/* GPIO2[20] */
-	MX6PAD(EIM_A17__IPU1_CSI1_D_12),	/* GPIO2[21] */
-	MX6PAD(EIM_EB0__IPU1_CSI1_D_11),	/* GPIO2[28] */
-	MX6PAD(EIM_EB1__IPU1_CSI1_D_10),	/* GPIO2[29] */
-	MX6PAD(EIM_DA0__IPU1_CSI1_D_9),		/* GPIO3[0] */
-	MX6PAD(EIM_DA1__IPU1_CSI1_D_8),		/* GPIO3[1] */
-	MX6PAD(EIM_DA2__IPU1_CSI1_D_7),		/* GPIO3[2] */
-	MX6PAD(EIM_DA3__IPU1_CSI1_D_6),		/* GPIO3[3] */
-	MX6PAD(EIM_DA4__IPU1_CSI1_D_5),		/* GPIO3[4] */
-	MX6PAD(EIM_DA5__IPU1_CSI1_D_4),		/* GPIO3[5] */
-	MX6PAD(EIM_DA6__IPU1_CSI1_D_3),		/* GPIO3[6] */
-	MX6PAD(EIM_DA7__IPU1_CSI1_D_2),		/* GPIO3[7] */
-	MX6PAD(EIM_DA8__IPU1_CSI1_D_1),		/* GPIO3[8] */
-	MX6PAD(EIM_DA9__IPU1_CSI1_D_0),		/* GPIO3[9] */
-	MX6PAD(EIM_DA10__IPU1_CSI1_DATA_EN),	/* GPIO3[10] */
-	MX6PAD(EIM_DA11__IPU1_CSI1_HSYNC),	/* GPIO3[11] */
-	MX6PAD(EIM_DA12__IPU1_CSI1_VSYNC),	/* GPIO3[12] */
-	MX6PAD(EIM_A16__IPU1_CSI1_PIXCLK),	/* GPIO2[22] */
-#else
-	MX6PAD(EIM_EB2__IPU2_CSI1_D_19),	/* GPIO2[30] */
-	MX6PAD(EIM_A23__IPU2_CSI1_D_18),	/* GPIO6[6] */
-	MX6PAD(EIM_A22__IPU2_CSI1_D_17),	/* GPIO2[16] */
-	MX6PAD(EIM_A21__IPU2_CSI1_D_16),	/* GPIO2[17] */
-	MX6PAD(EIM_A20__IPU2_CSI1_D_15),	/* GPIO2[18] */
-	MX6PAD(EIM_A19__IPU2_CSI1_D_14),	/* GPIO2[19] */
-	MX6PAD(EIM_A18__IPU2_CSI1_D_13),	/* GPIO2[20] */
-	MX6PAD(EIM_A17__IPU2_CSI1_D_12),	/* GPIO2[21] */
-	MX6PAD(EIM_EB0__IPU2_CSI1_D_11),	/* GPIO2[28] */
-	MX6PAD(EIM_EB1__IPU2_CSI1_D_10),	/* GPIO2[29] */
-	MX6PAD(EIM_DA0__IPU2_CSI1_D_9),		/* GPIO3[0] */
-	MX6PAD(EIM_DA1__IPU2_CSI1_D_8),		/* GPIO3[1] */
-	MX6PAD(EIM_DA2__IPU2_CSI1_D_7),		/* GPIO3[2] */
-	MX6PAD(EIM_DA3__IPU2_CSI1_D_6),		/* GPIO3[3] */
-	MX6PAD(EIM_DA4__IPU2_CSI1_D_5),		/* GPIO3[4] */
-	MX6PAD(EIM_DA5__IPU2_CSI1_D_4),		/* GPIO3[5] */
-	MX6PAD(EIM_DA6__IPU2_CSI1_D_3),		/* GPIO3[6] */
-	MX6PAD(EIM_DA7__IPU2_CSI1_D_2),		/* GPIO3[7] */
-	MX6PAD(EIM_DA8__IPU2_CSI1_D_1),		/* GPIO3[8] */
-	MX6PAD(EIM_DA9__IPU2_CSI1_D_0),		/* GPIO3[9] */
-	MX6PAD(EIM_DA10__IPU2_CSI1_DATA_EN),	/* GPIO3[10] */
-	MX6PAD(EIM_DA11__IPU2_CSI1_HSYNC),	/* GPIO3[11] */
-	MX6PAD(EIM_DA12__IPU2_CSI1_VSYNC),	/* GPIO3[12] */
-	MX6PAD(EIM_A16__IPU2_CSI1_PIXCLK),	/* GPIO2[22] */
-#endif
+	/* CSPI2 */
+	MX6PAD(EIM_LBA__ECSPI2_SS1),
+	MX6PAD(EIM_OE__ECSPI2_MISO),
+	MX6PAD(EIM_CS0__ECSPI2_SCLK),
+	MX6PAD(EIM_CS1__ECSPI2_MOSI),
+
+	/* GPIO pins */
+	MX6PAD(EIM_A16__GPIO_2_22),
+	MX6PAD(EIM_A17__GPIO_2_21),
+	MX6PAD(EIM_A18__GPIO_2_20),
+	MX6PAD(EIM_A19__GPIO_2_19),
+	MX6PAD(EIM_A20__GPIO_2_18),
+	MX6PAD(EIM_A21__GPIO_2_17),
+	MX6PAD(EIM_A22__GPIO_2_16),
+	MX6PAD(EIM_A23__GPIO_6_6),
+	MX6PAD(EIM_A24__GPIO_5_4),
+
 	MX6PAD(EIM_DA13__GPIO_3_13),		/* Power */
 	MX6PAD(EIM_DA14__GPIO_3_14),		/* Reset */
 	MX6PAD(EIM_WAIT__GPIO_5_0),		/* Irq */