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authorBhuvanchandra DV <bhuvanchandra.dv@toradex.com>2017-02-20 22:49:34 +0530
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2017-04-03 15:10:43 +0200
commit9090b5b90ccc350611a769230eab3fbc20c9d302 (patch)
tree689c28e2143695c99f3a16f7eccf59170e66123e
parent8a098f2f1b8ae277a38ee0c5e0b974d5baa8dd01 (diff)
imx: Expose SoC unique ID
Expose SoC unique ID read from OCOTP registers. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
-rw-r--r--arch/arm/mach-imx/cpu.c37
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index a1cf27625c18..7b87e6208476 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -80,6 +80,35 @@ void __init imx_aips_allow_unprivileged_access(
}
}
+static unsigned long long __init imx_get_soc_uid(void)
+{
+ struct device_node *np;
+ void __iomem *ocotp_base;
+ u64 uid = 0ull;
+
+ if (__mxc_cpu_type == MXC_CPU_IMX6SL || __mxc_cpu_type == MXC_CPU_IMX6DL ||
+ __mxc_cpu_type == MXC_CPU_IMX6SX || __mxc_cpu_type == MXC_CPU_IMX6Q ||
+ __mxc_cpu_type == MXC_CPU_IMX6UL || __mxc_cpu_type == MXC_CPU_IMX6ULL) {
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
+ } else if (__mxc_cpu_type == MXC_CPU_IMX7D) {
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-ocotp");
+ } else {
+ return uid;
+ }
+
+ ocotp_base = of_iomap(np, 0);
+ WARN_ON(!ocotp_base);
+
+ uid = readl_relaxed(ocotp_base + 0x420);
+ uid = (uid << 0x20);
+ uid |= readl_relaxed(ocotp_base + 0x410);
+
+ iounmap(ocotp_base);
+ of_node_put(np);
+
+ return uid;
+}
+
struct device * __init imx_soc_device_init(void)
{
struct soc_device_attribute *soc_dev_attr;
@@ -126,27 +155,35 @@ struct device * __init imx_soc_device_init(void)
soc_id = "i.MX53";
break;
case MXC_CPU_IMX6SL:
+ soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid());
soc_id = "i.MX6SL";
break;
case MXC_CPU_IMX6DL:
+ soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid());
soc_id = "i.MX6DL";
break;
case MXC_CPU_IMX6SX:
+ soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid());
soc_id = "i.MX6SX";
break;
case MXC_CPU_IMX6Q:
+ soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid());
+
if (imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
soc_id = "i.MX6QP";
else
soc_id = "i.MX6Q";
break;
case MXC_CPU_IMX6UL:
+ soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid());
soc_id = "i.MX6UL";
break;
case MXC_CPU_IMX6ULL:
+ soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid());
soc_id = "i.MX6ULL";
break;
case MXC_CPU_IMX7D:
+ soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid());
soc_id = "i.MX7D";
break;
default: