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authorAlex Frid <afrid@nvidia.com>2010-10-21 20:16:39 -0700
committerNiket Sirsi <nsirsi@nvidia.com>2010-10-29 18:18:23 -0700
commita7e991c39be9ae27bce0ec8c96235c1863ebb9b4 (patch)
treef5a6445a5a0a2392bbab8c8c77f6a88dcde4ea9a
parentf29026d4d357ee1f1ec40df2d5b3673fc2bacf41 (diff)
[ARM/tegra] RM: Increased PLLC VCO for HDMI config.tegra-10.9.4
Increased PLLC VCO for HDMI configuration to reduce jitter. Bug 734868 Change-Id: Ie898b3806e4e3c69310e9ea7e45c45fa7862de80 Reviewed-on: http://git-master/r/9660 Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks.h
index b3db73d..dda343c 100644
--- a/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks.h
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks.h
@@ -203,10 +203,10 @@ typedef struct NvRmPllFixedConfigRec
#define NVRM_PLLHD_AT_19MHZ { 594000, 16, 495, 0, 0}
#define NVRM_PLLHD_AT_26MHZ { 594000, 13, 297, 0, 0}
-#define NVRM_PLLHC_AT_12MHZ { 594000, 04, 396, 1, 0}
+#define NVRM_PLLHC_AT_12MHZ { 445500, 04, 594, 2, 0}
#define NVRM_PLLHC_AT_13MHZ { 594000, 13, 594, 0, 0}
#define NVRM_PLLHC_AT_19MHZ { 594000, 16, 495, 0, 0}
-#define NVRM_PLLHC_AT_26MHZ { 594000, 13, 594, 1, 0}
+#define NVRM_PLLHC_AT_26MHZ { 445500, 13, 891, 2, 0}
// Display divider is part of the display module and it is not described
// in central module clock information table. Hence, need this define.