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authorGerrit Code Review <gerrit2@git-master.nvidia.com>2010-01-12 04:38:20 +0200
committerGerrit Code Review <gerrit2@git-master.nvidia.com>2010-01-12 04:38:20 +0200
commitb4507c60baeb4e9b973fe11413d46e7b5fef0f08 (patch)
treeb91023470694383e5f336d928573bb972fdd2ae7
parentee37dbc094501acbb5d3f14fdb87ab389a678051 (diff)
parente9ef83b5d6f7a8c367a3ff2a88f373c3bb9312c1 (diff)
Merge change I26e16e30 into android-tegra-2.6.29tegra-9.12.3
* changes: tegra RM: Init/restore DDR PD state machine.
-rw-r--r--arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c22
1 files changed, 21 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c
index 8ee8277..882d0c1 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c
@@ -45,6 +45,9 @@
// Enable CPU/EMC ratio policy
#define NVRM_LIMIT_CPU_EMC_RATIO (1)
+// Use DRAM power down mode with EMC clock change
+#define NVRM_EMC_CLKCHANGE_PD (1)
+
// Default CPU power good delay
#define NVRM_DEFAULT_CPU_PWRGOOD_US (2000)
@@ -238,6 +241,9 @@ static NvBool
Ap20EmcClkChangeConfig(
NvRmDeviceHandle hRmDevice)
{
+// NO-DEVICE for dummy MRW/MRS commands
+#define NULL_DEV_SELECTN (3)
+
NvU32 cfg2, cfg5;
cfg2 = NV_REGR(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
@@ -247,14 +253,28 @@ Ap20EmcClkChangeConfig(
switch (NV_DRF_VAL(EMC, FBIO_CFG5, DRAM_TYPE, cfg5))
{
- case EMC_FBIO_CFG5_0_DRAM_TYPE_DDR1:
case EMC_FBIO_CFG5_0_DRAM_TYPE_LPDDR2:
+#if NVRM_EMC_CLKCHANGE_PD
+ // Dummy mode control command to activate PD state machine
+ NV_REGW(hRmDevice,
+ NvRmPrivModuleID_ExternalMemoryController, 0, EMC_MRW_0,
+ NV_DRF_NUM(EMC, MRW, MRW_DEV_SELECTN, NULL_DEV_SELECTN));
+ NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+
cfg2 = NV_FLD_SET_DRF_DEF(
EMC, CFG_2, CLKCHANGE_PD_ENABLE, ENABLED, cfg2);
cfg2 = NV_FLD_SET_DRF_DEF(
EMC, CFG_2, CLKCHANGE_SR_ENABLE, DISABLED, cfg2);
break;
+#endif
case EMC_FBIO_CFG5_0_DRAM_TYPE_DDR2:
+#if NVRM_EMC_CLKCHANGE_PD
+ // Dummy mode control command to activate PD state machine
+ NV_REGW(hRmDevice,
+ NvRmPrivModuleID_ExternalMemoryController, 0, EMC_MRS_0,
+ NV_DRF_NUM(EMC, MRS, MRS_DEV_SELECTN, NULL_DEV_SELECTN));
+ NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+#endif
cfg2 = NV_FLD_SET_DRF_DEF(
EMC, CFG_2, CLKCHANGE_PD_ENABLE, DISABLED, cfg2);
cfg2 = NV_FLD_SET_DRF_DEF(