ARM: tegra: cardhu: update memory timings

Extend tick length to 60ns

Also add missed Cardhu SKU 1000 table

Bug 1001229
Bug 970610

Change-Id: I224158a88d02595d5b911f59b6920b9ed99481ab
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/113315
(cherry picked from commit 492193079047d9c5a4fff617a14191438f356e42)
Reviewed-on: http://git-master/r/116221
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

1 files changed, 694 insertions, 88 deletions

diff --git a/arch/arm/mach-tegra/board-cardhu-memory.c b/arch/arm/mach-tegra/board-cardhu-memory.c
index 1ed99a9fa1fa..33a66053ee45 100644
--- a/arch/arm/mach-tegra/board-cardhu-memory.c
+++ b/arch/arm/mach-tegra/board-cardhu-memory.c
@@ -705,7 +705,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x80000280, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00020001, /* MC_EMEM_ARB_CFG */
+			0x00030003, /* MC_EMEM_ARB_CFG */
 			0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -825,7 +825,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000001, /* MC_EMEM_ARB_CFG */
+			0x00010003, /* MC_EMEM_ARB_CFG */
 			0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -945,7 +945,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000001, /* MC_EMEM_ARB_CFG */
+			0x00000003, /* MC_EMEM_ARB_CFG */
 			0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -1065,7 +1065,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000003, /* MC_EMEM_ARB_CFG */
+			0x00000006, /* MC_EMEM_ARB_CFG */
 			0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -1185,8 +1185,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x8000174b, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000005, /* MC_EMEM_ARB_CFG */
-			0x80000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x0000000b, /* MC_EMEM_ARB_CFG */
+			0xc0000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
 			0x00000009, /* MC_EMEM_ARB_TIMING_RC */
@@ -1305,8 +1305,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x80001941, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000006, /* MC_EMEM_ARB_CFG */
-			0x8000004a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x0000000c, /* MC_EMEM_ARB_CFG */
+			0xc000004a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
 			0x0000000a, /* MC_EMEM_ARB_TIMING_RC */
@@ -1425,8 +1425,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x80001bc0, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000006, /* MC_EMEM_ARB_CFG */
-			0x80000051, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x0000000d, /* MC_EMEM_ARB_CFG */
+			0xc0000051, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000003, /* MC_EMEM_ARB_TIMING_RP */
 			0x0000000b, /* MC_EMEM_ARB_TIMING_RC */
@@ -1545,8 +1545,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x800020ae, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000008, /* MC_EMEM_ARB_CFG */
-			0x80000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x0000000f, /* MC_EMEM_ARB_CFG */
+			0xc0000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000003, /* MC_EMEM_ARB_TIMING_RP */
 			0x0000000d, /* MC_EMEM_ARB_TIMING_RC */
@@ -1665,8 +1665,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x800028a5, /* EMC_DYN_SELF_REF_CONTROL */
-			0x0000000a, /* MC_EMEM_ARB_CFG */
-			0x80000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000014, /* MC_EMEM_ARB_CFG */
+			0xc0000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000004, /* MC_EMEM_ARB_TIMING_RP */
 			0x00000010, /* MC_EMEM_ARB_TIMING_RC */
@@ -1785,8 +1785,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
-			0x0000000c, /* MC_EMEM_ARB_CFG */
-			0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000016, /* MC_EMEM_ARB_CFG */
+			0xc0000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000005, /* MC_EMEM_ARB_TIMING_RP */
 			0x00000013, /* MC_EMEM_ARB_TIMING_RC */
@@ -1905,8 +1905,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
-			0x0000000c, /* MC_EMEM_ARB_CFG */
-			0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000018, /* MC_EMEM_ARB_CFG */
+			0xc0000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000005, /* MC_EMEM_ARB_TIMING_RP */
 			0x00000013, /* MC_EMEM_ARB_TIMING_RC */
@@ -2025,8 +2025,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x8000367d, /* EMC_DYN_SELF_REF_CONTROL */
-			0x0000000d, /* MC_EMEM_ARB_CFG */
-			0x800000a2, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x0000001b, /* MC_EMEM_ARB_CFG */
+			0xc00000a2, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000005, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000006, /* MC_EMEM_ARB_TIMING_RP */
 			0x00000016, /* MC_EMEM_ARB_TIMING_RC */
@@ -2148,7 +2148,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00010001, /* MC_EMEM_ARB_CFG */
+			0x00010003, /* MC_EMEM_ARB_CFG */
 			0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -2268,7 +2268,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000001, /* MC_EMEM_ARB_CFG */
+			0x00000003, /* MC_EMEM_ARB_CFG */
 			0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -2388,7 +2388,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000003, /* MC_EMEM_ARB_CFG */
+			0x00000006, /* MC_EMEM_ARB_CFG */
 			0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -2508,8 +2508,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x8000174b, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000005, /* MC_EMEM_ARB_CFG */
-			0x80000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x0000000b, /* MC_EMEM_ARB_CFG */
+			0xc0000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
 			0x00000009, /* MC_EMEM_ARB_TIMING_RC */
@@ -2628,8 +2628,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x800018c8, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000006, /* MC_EMEM_ARB_CFG */
-			0x80000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x0000000c, /* MC_EMEM_ARB_CFG */
+			0xc0000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
 			0x00000009, /* MC_EMEM_ARB_TIMING_RC */
@@ -2748,8 +2748,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x80002d93, /* EMC_DYN_SELF_REF_CONTROL */
-			0x0000000b, /* MC_EMEM_ARB_CFG */
-			0x80000087, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000014, /* MC_EMEM_ARB_CFG */
+			0xc0000087, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000005, /* MC_EMEM_ARB_TIMING_RP */
 			0x00000012, /* MC_EMEM_ARB_TIMING_RC */
@@ -2868,8 +2868,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x80002d93, /* EMC_DYN_SELF_REF_CONTROL */
-			0x0000000b, /* MC_EMEM_ARB_CFG */
-			0x80000087, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000016, /* MC_EMEM_ARB_CFG */
+			0xc0000087, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000005, /* MC_EMEM_ARB_TIMING_RP */
 			0x00000012, /* MC_EMEM_ARB_TIMING_RC */
@@ -2988,8 +2988,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
-			0x0000000c, /* MC_EMEM_ARB_CFG */
-			0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000018, /* MC_EMEM_ARB_CFG */
+			0xc0000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000005, /* MC_EMEM_ARB_TIMING_RP */
 			0x00000013, /* MC_EMEM_ARB_TIMING_RC */
@@ -3111,7 +3111,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x80000287, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00020001, /* MC_EMEM_ARB_CFG */
+			0x00030003, /* MC_EMEM_ARB_CFG */
 			0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -3186,14 +3186,14 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = {
 			0x00004288, /* EMC_FBIO_CFG5 */
 			0x007800a4, /* EMC_CFG_DIG_DLL */
 			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x000fc000, /* EMC_DLL_XFORM_DQS0 */
-			0x000fc000, /* EMC_DLL_XFORM_DQS1 */
-			0x000fc000, /* EMC_DLL_XFORM_DQS2 */
-			0x000fc000, /* EMC_DLL_XFORM_DQS3 */
-			0x000fc000, /* EMC_DLL_XFORM_DQS4 */
-			0x000fc000, /* EMC_DLL_XFORM_DQS5 */
-			0x000fc000, /* EMC_DLL_XFORM_DQS6 */
-			0x000fc000, /* EMC_DLL_XFORM_DQS7 */
+			0x00080000, /* EMC_DLL_XFORM_DQS0 */
+			0x00080000, /* EMC_DLL_XFORM_DQS1 */
+			0x00080000, /* EMC_DLL_XFORM_DQS2 */
+			0x00080000, /* EMC_DLL_XFORM_DQS3 */
+			0x00080000, /* EMC_DLL_XFORM_DQS4 */
+			0x00080000, /* EMC_DLL_XFORM_DQS5 */
+			0x00080000, /* EMC_DLL_XFORM_DQS6 */
+			0x00080000, /* EMC_DLL_XFORM_DQS7 */
 			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
 			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
 			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -3210,10 +3210,10 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = {
 			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
 			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
 			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x000fc000, /* EMC_DLL_XFORM_DQ0 */
-			0x000fc000, /* EMC_DLL_XFORM_DQ1 */
-			0x000fc000, /* EMC_DLL_XFORM_DQ2 */
-			0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+			0x00080000, /* EMC_DLL_XFORM_DQ0 */
+			0x00080000, /* EMC_DLL_XFORM_DQ1 */
+			0x00080000, /* EMC_DLL_XFORM_DQ2 */
+			0x00080000, /* EMC_DLL_XFORM_DQ3 */
 			0x000002a0, /* EMC_XM2CMDPADCTRL */
 			0x0800211c, /* EMC_XM2DQSPADCTRL2 */
 			0x00000000, /* EMC_XM2DQPADCTRL2 */
@@ -3231,7 +3231,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00010001, /* MC_EMEM_ARB_CFG */
+			0x00010003, /* MC_EMEM_ARB_CFG */
 			0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -3306,14 +3306,14 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = {
 			0x00004288, /* EMC_FBIO_CFG5 */
 			0x007800a4, /* EMC_CFG_DIG_DLL */
 			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x000fc000, /* EMC_DLL_XFORM_DQS0 */
-			0x000fc000, /* EMC_DLL_XFORM_DQS1 */
-			0x000fc000, /* EMC_DLL_XFORM_DQS2 */
-			0x000fc000, /* EMC_DLL_XFORM_DQS3 */
-			0x000fc000, /* EMC_DLL_XFORM_DQS4 */
-			0x000fc000, /* EMC_DLL_XFORM_DQS5 */
-			0x000fc000, /* EMC_DLL_XFORM_DQS6 */
-			0x000fc000, /* EMC_DLL_XFORM_DQS7 */
+			0x00080000, /* EMC_DLL_XFORM_DQS0 */
+			0x00080000, /* EMC_DLL_XFORM_DQS1 */
+			0x00080000, /* EMC_DLL_XFORM_DQS2 */
+			0x00080000, /* EMC_DLL_XFORM_DQS3 */
+			0x00080000, /* EMC_DLL_XFORM_DQS4 */
+			0x00080000, /* EMC_DLL_XFORM_DQS5 */
+			0x00080000, /* EMC_DLL_XFORM_DQS6 */
+			0x00080000, /* EMC_DLL_XFORM_DQS7 */
 			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
 			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
 			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -3330,10 +3330,10 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = {
 			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
 			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
 			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x000fc000, /* EMC_DLL_XFORM_DQ0 */
-			0x000fc000, /* EMC_DLL_XFORM_DQ1 */
-			0x000fc000, /* EMC_DLL_XFORM_DQ2 */
-			0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+			0x00080000, /* EMC_DLL_XFORM_DQ0 */
+			0x00080000, /* EMC_DLL_XFORM_DQ1 */
+			0x00080000, /* EMC_DLL_XFORM_DQ2 */
+			0x00080000, /* EMC_DLL_XFORM_DQ3 */
 			0x000002a0, /* EMC_XM2CMDPADCTRL */
 			0x0800211c, /* EMC_XM2DQSPADCTRL2 */
 			0x00000000, /* EMC_XM2DQPADCTRL2 */
@@ -3351,7 +3351,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000001, /* MC_EMEM_ARB_CFG */
+			0x00000003, /* MC_EMEM_ARB_CFG */
 			0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -3471,7 +3471,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000003, /* MC_EMEM_ARB_CFG */
+			0x00000006, /* MC_EMEM_ARB_CFG */
 			0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -3591,8 +3591,8 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x8000174b, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000005, /* MC_EMEM_ARB_CFG */
-			0x80000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x0000000b, /* MC_EMEM_ARB_CFG */
+			0xc0000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
 			0x00000009, /* MC_EMEM_ARB_TIMING_RC */
@@ -3711,8 +3711,8 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x800018c8, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000006, /* MC_EMEM_ARB_CFG */
-			0x80000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x0000000c, /* MC_EMEM_ARB_CFG */
+			0xc0000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
 			0x00000009, /* MC_EMEM_ARB_TIMING_RC */
@@ -3831,8 +3831,8 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x80002d93, /* EMC_DYN_SELF_REF_CONTROL */
-			0x0000000b, /* MC_EMEM_ARB_CFG */
-			0x80000087, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000016, /* MC_EMEM_ARB_CFG */
+			0xc0000087, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000005, /* MC_EMEM_ARB_TIMING_RP */
 			0x00000012, /* MC_EMEM_ARB_TIMING_RC */
@@ -3951,8 +3951,8 @@ static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
-			0x0000000c, /* MC_EMEM_ARB_CFG */
-			0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000018, /* MC_EMEM_ARB_CFG */
+			0xc0000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000005, /* MC_EMEM_ARB_TIMING_RP */
 			0x00000013, /* MC_EMEM_ARB_TIMING_RC */
@@ -4194,7 +4194,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4p8g304eb[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x800001c2, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00020001, /* MC_EMEM_ARB_CFG */
+			0x00030003, /* MC_EMEM_ARB_CFG */
 			0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -4314,7 +4314,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4p8g304eb[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x80000287, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00010001, /* MC_EMEM_ARB_CFG */
+			0x00010003, /* MC_EMEM_ARB_CFG */
 			0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -4434,7 +4434,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4p8g304eb[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000001, /* MC_EMEM_ARB_CFG */
+			0x00000003, /* MC_EMEM_ARB_CFG */
 			0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -4554,7 +4554,7 @@ static const struct tegra_emc_table cardhu_emc_tables_k4p8g304eb[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000003, /* MC_EMEM_ARB_CFG */
+			0x00000006, /* MC_EMEM_ARB_CFG */
 			0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -4914,8 +4914,8 @@ static const struct tegra_emc_table cardhu_emc_tables_k4p8g304eb[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x800010d9, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000008, /* MC_EMEM_ARB_CFG */
-			0x80000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x0000000f, /* MC_EMEM_ARB_CFG */
+			0xc0000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000004, /* MC_EMEM_ARB_TIMING_RP */
 			0x00000010, /* MC_EMEM_ARB_TIMING_RC */
@@ -5037,7 +5037,7 @@ static const struct tegra_emc_table cardhu_emc_tables_edb8132b2ma[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x800001c5, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00020001, /* MC_EMEM_ARB_CFG */
+			0x00030003, /* MC_EMEM_ARB_CFG */
 			0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -5157,7 +5157,7 @@ static const struct tegra_emc_table cardhu_emc_tables_edb8132b2ma[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x80000287, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00010001, /* MC_EMEM_ARB_CFG */
+			0x00010003, /* MC_EMEM_ARB_CFG */
 			0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -5277,7 +5277,7 @@ static const struct tegra_emc_table cardhu_emc_tables_edb8132b2ma[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000001, /* MC_EMEM_ARB_CFG */
+			0x00000003, /* MC_EMEM_ARB_CFG */
 			0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -5397,7 +5397,7 @@ static const struct tegra_emc_table cardhu_emc_tables_edb8132b2ma[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000003, /* MC_EMEM_ARB_CFG */
+			0x00000006, /* MC_EMEM_ARB_CFG */
 			0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -5517,8 +5517,8 @@ static const struct tegra_emc_table cardhu_emc_tables_edb8132b2ma[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x800010d9, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000008, /* MC_EMEM_ARB_CFG */
-			0x80000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x0000000f, /* MC_EMEM_ARB_CFG */
+			0xc0000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000004, /* MC_EMEM_ARB_TIMING_RP */
 			0x00000010, /* MC_EMEM_ARB_TIMING_RC */
@@ -5640,7 +5640,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_pm311[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00010001, /* MC_EMEM_ARB_CFG */
+			0x00010003, /* MC_EMEM_ARB_CFG */
 			0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -5760,7 +5760,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_pm311[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000001, /* MC_EMEM_ARB_CFG */
+			0x00000003, /* MC_EMEM_ARB_CFG */
 			0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -5880,7 +5880,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_pm311[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000003, /* MC_EMEM_ARB_CFG */
+			0x00000006, /* MC_EMEM_ARB_CFG */
 			0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
@@ -6000,8 +6000,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_pm311[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x800014d4, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000005, /* MC_EMEM_ARB_CFG */
-			0x8000003d, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x0000000a, /* MC_EMEM_ARB_CFG */
+			0xc000003d, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
 			0x00000008, /* MC_EMEM_ARB_TIMING_RC */
@@ -6120,8 +6120,8 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_pm311[] = {
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
 			0x800028a5, /* EMC_DYN_SELF_REF_CONTROL */
-			0x0000000a, /* MC_EMEM_ARB_CFG */
-			0x80000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000014, /* MC_EMEM_ARB_CFG */
+			0xc0000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000004, /* MC_EMEM_ARB_TIMING_RP */
 			0x00000010, /* MC_EMEM_ARB_TIMING_RC */
@@ -6151,6 +6151,609 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_pm311[] = {
 	},
 };
 
+static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2g2r[] = {
+	{
+		0x32,       /* Rev 3.2 */
+		25500,      /* SDRAM frequency */
+		{
+			0x00000001, /* EMC_RC */
+			0x00000004, /* EMC_RFC */
+			0x00000000, /* EMC_RAS */
+			0x00000000, /* EMC_RP */
+			0x00000002, /* EMC_R2W */
+			0x0000000a, /* EMC_W2R */
+			0x00000003, /* EMC_R2P */
+			0x0000000b, /* EMC_W2P */
+			0x00000000, /* EMC_RD_RCD */
+			0x00000000, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_QUSE */
+			0x00000004, /* EMC_QRST */
+			0x00000007, /* EMC_QSAFE */
+			0x0000000c, /* EMC_RDV */
+			0x000000c0, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x00000030, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x00000002, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000007, /* EMC_AR2PDEN */
+			0x0000000f, /* EMC_RW2PDEN */
+			0x00000005, /* EMC_TXSR */
+			0x00000005, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000001, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x000000c7, /* EMC_TREFBW */
+			0x00000000, /* EMC_QUSE_EXTRA */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00006288, /* EMC_FBIO_CFG5 */
+			0x007800a4, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x000fc000, /* EMC_DLL_XFORM_DQS0 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS1 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS2 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS3 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS4 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS5 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS6 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+			0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+			0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+			0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0800211c, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x01f1f108, /* EMC_XM2COMPPADCTRL */
+			0x05057404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+			0x08000168, /* EMC_XM2QUSEPADCTRL */
+			0x08000000, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00000000, /* EMC_ZCAL_INTERVAL */
+			0x00000040, /* EMC_ZCAL_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x80000287, /* EMC_DYN_SELF_REF_CONTROL */
+			0x00030003, /* MC_EMEM_ARB_CFG */
+			0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06020102, /* MC_EMEM_ARB_DA_TURNS */
+			0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+			0x74830303, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xd8000000, /* EMC_FBIO_SPARE */
+			0xff00ff00, /* EMC_CFG_RSV */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000000, /* EMC_CFG.PERIODIC_QRST */
+		0x00001221, /* Mode Register 0 */
+		0x00100003, /* Mode Register 1 */
+		0x00200008, /* Mode Register 2 */
+		0x00000001, /* EMC_CFG.DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
+		51000,      /* SDRAM frequency */
+		{
+			0x00000002, /* EMC_RC */
+			0x00000008, /* EMC_RFC */
+			0x00000001, /* EMC_RAS */
+			0x00000000, /* EMC_RP */
+			0x00000002, /* EMC_R2W */
+			0x0000000a, /* EMC_W2R */
+			0x00000003, /* EMC_R2P */
+			0x0000000b, /* EMC_W2P */
+			0x00000000, /* EMC_RD_RCD */
+			0x00000000, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_QUSE */
+			0x00000004, /* EMC_QRST */
+			0x00000007, /* EMC_QSAFE */
+			0x0000000c, /* EMC_RDV */
+			0x00000181, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x00000002, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000007, /* EMC_AR2PDEN */
+			0x0000000f, /* EMC_RW2PDEN */
+			0x00000009, /* EMC_TXSR */
+			0x00000009, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000002, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x0000018e, /* EMC_TREFBW */
+			0x00000000, /* EMC_QUSE_EXTRA */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00006288, /* EMC_FBIO_CFG5 */
+			0x007800a4, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x000fc000, /* EMC_DLL_XFORM_DQS0 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS1 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS2 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS3 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS4 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS5 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS6 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+			0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+			0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+			0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0800211c, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x01f1f108, /* EMC_XM2COMPPADCTRL */
+			0x05057404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+			0x08000168, /* EMC_XM2QUSEPADCTRL */
+			0x08000000, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00000000, /* EMC_ZCAL_INTERVAL */
+			0x00000040, /* EMC_ZCAL_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
+			0x00010003, /* MC_EMEM_ARB_CFG */
+			0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06020102, /* MC_EMEM_ARB_DA_TURNS */
+			0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+			0x73430303, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xd8000000, /* EMC_FBIO_SPARE */
+			0xff00ff00, /* EMC_CFG_RSV */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000000, /* EMC_CFG.PERIODIC_QRST */
+		0x00001221, /* Mode Register 0 */
+		0x00100003, /* Mode Register 1 */
+		0x00200008, /* Mode Register 2 */
+		0x00000001, /* EMC_CFG.DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
+		102000,     /* SDRAM frequency */
+		{
+			0x00000004, /* EMC_RC */
+			0x00000010, /* EMC_RFC */
+			0x00000003, /* EMC_RAS */
+			0x00000001, /* EMC_RP */
+			0x00000002, /* EMC_R2W */
+			0x0000000a, /* EMC_W2R */
+			0x00000003, /* EMC_R2P */
+			0x0000000b, /* EMC_W2P */
+			0x00000001, /* EMC_RD_RCD */
+			0x00000001, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_QUSE */
+			0x00000004, /* EMC_QRST */
+			0x00000007, /* EMC_QSAFE */
+			0x0000000c, /* EMC_RDV */
+			0x00000303, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x00000002, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000007, /* EMC_AR2PDEN */
+			0x0000000f, /* EMC_RW2PDEN */
+			0x00000012, /* EMC_TXSR */
+			0x00000012, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000004, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x0000031c, /* EMC_TREFBW */
+			0x00000000, /* EMC_QUSE_EXTRA */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00006288, /* EMC_FBIO_CFG5 */
+			0x007800a4, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x000fc000, /* EMC_DLL_XFORM_DQS0 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS1 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS2 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS3 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS4 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS5 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS6 */
+			0x000fc000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+			0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+			0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+			0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0800211c, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x01f1f108, /* EMC_XM2COMPPADCTRL */
+			0x05057404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+			0x08000168, /* EMC_XM2QUSEPADCTRL */
+			0x08000000, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00000000, /* EMC_ZCAL_INTERVAL */
+			0x00000040, /* EMC_ZCAL_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
+			0x00000003, /* MC_EMEM_ARB_CFG */
+			0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06020102, /* MC_EMEM_ARB_DA_TURNS */
+			0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
+			0x72830504, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xd8000000, /* EMC_FBIO_SPARE */
+			0xff00ff00, /* EMC_CFG_RSV */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000000, /* EMC_CFG.PERIODIC_QRST */
+		0x00001221, /* Mode Register 0 */
+		0x00100003, /* Mode Register 1 */
+		0x00200008, /* Mode Register 2 */
+		0x00000001, /* EMC_CFG.DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
+		333500,     /* SDRAM frequency */
+		{
+			0x0000000f, /* EMC_RC */
+			0x00000034, /* EMC_RFC */
+			0x0000000a, /* EMC_RAS */
+			0x00000003, /* EMC_RP */
+			0x00000003, /* EMC_R2W */
+			0x00000008, /* EMC_W2R */
+			0x00000002, /* EMC_R2P */
+			0x00000009, /* EMC_W2P */
+			0x00000003, /* EMC_RD_RCD */
+			0x00000003, /* EMC_WR_RCD */
+			0x00000002, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000004, /* EMC_WDV */
+			0x00000006, /* EMC_QUSE */
+			0x00000004, /* EMC_QRST */
+			0x0000000a, /* EMC_QSAFE */
+			0x0000000c, /* EMC_RDV */
+			0x000009e9, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x0000027a, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000001, /* EMC_PDEX2WR */
+			0x00000008, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000007, /* EMC_AR2PDEN */
+			0x0000000e, /* EMC_RW2PDEN */
+			0x00000039, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x0000000a, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x00000a2a, /* EMC_TREFBW */
+			0x00000000, /* EMC_QUSE_EXTRA */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00007088, /* EMC_FBIO_CFG5 */
+			0x00260084, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00028000, /* EMC_DLL_XFORM_DQS0 */
+			0x00028000, /* EMC_DLL_XFORM_DQS1 */
+			0x00028000, /* EMC_DLL_XFORM_DQS2 */
+			0x00028000, /* EMC_DLL_XFORM_DQS3 */
+			0x00028000, /* EMC_DLL_XFORM_DQS4 */
+			0x00028000, /* EMC_DLL_XFORM_DQS5 */
+			0x00028000, /* EMC_DLL_XFORM_DQS6 */
+			0x00028000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x0004c000, /* EMC_DLL_XFORM_DQ0 */
+			0x0004c000, /* EMC_DLL_XFORM_DQ1 */
+			0x0004c000, /* EMC_DLL_XFORM_DQ2 */
+			0x0004c000, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0800013d, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x01f1f508, /* EMC_XM2COMPPADCTRL */
+			0x05057404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+			0x080001e8, /* EMC_XM2QUSEPADCTRL */
+			0x08000021, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x014b000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x800014d4, /* EMC_DYN_SELF_REF_CONTROL */
+			0x0000000a, /* MC_EMEM_ARB_CFG */
+			0xc000003d, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000008, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000004, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06030202, /* MC_EMEM_ARB_DA_TURNS */
+			0x000b0608, /* MC_EMEM_ARB_DA_COVERS */
+			0x70850f09, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xe8000000, /* EMC_FBIO_SPARE */
+			0xff00ff88, /* EMC_CFG_RSV */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000000, /* EMC_CFG.PERIODIC_QRST */
+		0x00000321, /* Mode Register 0 */
+		0x00100002, /* Mode Register 1 */
+		0x00200000, /* Mode Register 2 */
+		0x00000000, /* EMC_CFG.DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
+		667000,     /* SDRAM frequency */
+		{
+			0x0000001f, /* EMC_RC */
+			0x00000069, /* EMC_RFC */
+			0x00000016, /* EMC_RAS */
+			0x00000008, /* EMC_RP */
+			0x00000005, /* EMC_R2W */
+			0x0000000c, /* EMC_W2R */
+			0x00000003, /* EMC_R2P */
+			0x00000011, /* EMC_W2P */
+			0x00000008, /* EMC_RD_RCD */
+			0x00000008, /* EMC_WR_RCD */
+			0x00000002, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000007, /* EMC_WDV */
+			0x0000000b, /* EMC_QUSE */
+			0x00000009, /* EMC_QRST */
+			0x0000000c, /* EMC_QSAFE */
+			0x00000011, /* EMC_RDV */
+			0x00001412, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x00000504, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x0000000e, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x0000000c, /* EMC_AR2PDEN */
+			0x00000016, /* EMC_RW2PDEN */
+			0x00000072, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000005, /* EMC_TCKE */
+			0x00000015, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000006, /* EMC_TCLKSTABLE */
+			0x00000007, /* EMC_TCLKSTOP */
+			0x00001453, /* EMC_TREFBW */
+			0x0000000c, /* EMC_QUSE_EXTRA */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00005088, /* EMC_FBIO_CFG5 */
+			0xf00b0191, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00000008, /* EMC_DLL_XFORM_DQS0 */
+			0x00000008, /* EMC_DLL_XFORM_DQS1 */
+			0x00000008, /* EMC_DLL_XFORM_DQS2 */
+			0x00000008, /* EMC_DLL_XFORM_DQS3 */
+			0x00000008, /* EMC_DLL_XFORM_DQS4 */
+			0x00000008, /* EMC_DLL_XFORM_DQS5 */
+			0x00000008, /* EMC_DLL_XFORM_DQS6 */
+			0x00000008, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00000008, /* EMC_DLL_XFORM_DQ0 */
+			0x00000008, /* EMC_DLL_XFORM_DQ1 */
+			0x00000008, /* EMC_DLL_XFORM_DQ2 */
+			0x00000008, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0600013d, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x01f1f508, /* EMC_XM2COMPPADCTRL */
+			0x07077404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
+			0x080001e8, /* EMC_XM2QUSEPADCTRL */
+			0x07000021, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x0116000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x800028a5, /* EMC_DYN_SELF_REF_CONTROL */
+			0x00000014, /* MC_EMEM_ARB_CFG */
+			0xc0000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000004, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000010, /* MC_EMEM_ARB_TIMING_RC */
+			0x0000000a, /* MC_EMEM_ARB_TIMING_RAS */
+			0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
+			0x08040202, /* MC_EMEM_ARB_DA_TURNS */
+			0x00140c10, /* MC_EMEM_ARB_DA_COVERS */
+			0x70ea1f11, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xf8000000, /* EMC_FBIO_SPARE */
+			0xff00ff01, /* EMC_CFG_RSV */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000001, /* EMC_CFG.PERIODIC_QRST */
+		0x00000b71, /* Mode Register 0 */
+		0x00100002, /* Mode Register 1 */
+		0x00200018, /* Mode Register 2 */
+		0x00000000, /* EMC_CFG.DYN_SELF_REF */
+	},
+};
+
 static const u32 pm269_bit_swap_map[32] = {
       /* DDR bit #    SoC bit # */
 	[0]  = 0x1 << 1,
@@ -6231,6 +6834,9 @@ int cardhu_emc_init(void)
 				SKU_MEMORY_CARDHU_2GB_1R_HYNIX)
 			tegra_init_emc(cardhu_emc_tables_h5tc2g_a2_2GB1R,
 				ARRAY_SIZE(cardhu_emc_tables_h5tc2g_a2_2GB1R));
+		else if (MEMORY_TYPE(board.sku) == SKU_MEMORY_CARDHU_2GB_2R)
+			tegra_init_emc(cardhu_emc_tables_h5tc2g_a2_2g2r,
+				ARRAY_SIZE(cardhu_emc_tables_h5tc2g_a2_2g2r));
 		break;
 	}