mx3: Add Core Support for the i.MX31 LiteKit

This patch is from http://www.lysator.liu.se/~lilja/linux/2007-10-19/ and
was forward ported from the 2.6.19 patch for the MX31 LiteKit.  It is a
fairly hasty job, but it seems to work fine.

These were originally posted to the LogicPD forums.

Signed-off-by: Justin Waters <justin.waters@timesys.com>

6 files changed, 2230 insertions, 0 deletions

diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 042feba3aebd..50f73a410b49 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -1,6 +1,13 @@
 menu "MX3 Options"
 	depends on ARCH_MX3
 
+config MACH_MX31LITE
+	bool "Support MX31LITE (logicpd lite kit) platforms"
+	default y
+	help
+	  Include support for MX31LITE platform from logicpd. This includes
+	  specific configurations for the board and its peripherals.
+
 config MACH_MX31ADS
 	bool "Support MX31ADS platforms"
 	default y
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 8be4b946999b..861ad6ee36d2 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -6,6 +6,7 @@
 
 obj-y			:= system.o iomux.o cpu.o mm.o clock.o usb.o dptc.o devices.o serial.o dma.o mxc_pm.o dvfs_v2.o
 obj-$(CONFIG_MACH_MX31ADS)	+= mx31ads.o mx31ads_gpio.o
+obj-$(CONFIG_MACH_MX31LITE)	+= mx31lite.o mx31lite_gpio.o usb_lite.o
 
 # power management
 obj-$(CONFIG_MXC_DVFS)  += dvfs.o
diff --git a/arch/arm/mach-mx3/board-mx31lite.h b/arch/arm/mach-mx3/board-mx31lite.h
new file mode 100644
index 000000000000..e2d84e3c6f38
--- /dev/null
+++ b/arch/arm/mach-mx3/board-mx31lite.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright 2005-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARM_ARCH_BOARD_MX31LITE_H_
+#define __ASM_ARM_ARCH_BOARD_MX31LITE_H_
+
+/*
+ * Include Files
+ */
+/*#include <linux/config.h>*/
+/*#include <asm/arch/board.h>*/
+#include <asm/arch/mxc_uart.h>
+
+/* Start of physical RAM */
+//#define PHYS_OFFSET	        UL(0x80000000)
+
+/* Size of contiguous memory for DMA and other h/w blocks */
+#define CONSISTENT_DMA_SIZE	SZ_8M
+
+/* I2C configuration */
+/*!
+ * This defines the number of I2C modules in the MXC platform
+ * Defined as 1, as MC13783 on ADS uses the other pins
+ */
+#define I2C_NR                  1
+/*!
+ * This define specifies the frequency divider value to be written into
+ * the I2C \b IFDR register.
+ */
+#define I2C1_FRQ_DIV            0x17
+
+/*!
+ * @name MXC UART EVB board level configurations
+ */
+/*! @{ */
+/*!
+ * Specify the max baudrate for the MXC UARTs for your board, do not specify a max
+ * baudrate greater than 1500000. This is used while specifying the UART Power
+ * management constraints.
+ */
+#define MAX_UART_BAUDRATE       1500000
+/*!
+ * Specifies if the Irda transmit path is inverting
+ */
+#define MXC_IRDA_TX_INV         0
+/*!
+ * Specifies if the Irda receive path is inverting
+ */
+#define MXC_IRDA_RX_INV         0
+/* UART 1 configuration */
+/*!
+ * This define specifies if the UART port is configured to be in DTE or
+ * DCE mode. There exists a define like this for each UART port. Valid
+ * values that can be used are \b MODE_DTE or \b MODE_DCE.
+ */
+#define UART1_MODE              MODE_DCE
+/*!
+ * This define specifies if the UART is to be used for IRDA. There exists a
+ * define like this for each UART port. Valid values that can be used are
+ * \b IRDA or \b NO_IRDA.
+ */
+#define UART1_IR                NO_IRDA
+/*!
+ * This define is used to enable or disable a particular UART port. If
+ * disabled, the UART will not be registered in the file system and the user
+ * will not be able to access it. There exists a define like this for each UART
+ * port. Specify a value of 1 to enable the UART and 0 to disable it.
+ */
+#define UART1_ENABLED           1
+/*! @} */
+/* UART 2 configuration */
+#define UART2_MODE              MODE_DCE
+#define UART2_IR                IRDA
+#define UART2_ENABLED           1
+/* UART 3 configuration */
+#define UART3_MODE              MODE_DTE
+#define UART3_IR                NO_IRDA
+#define UART3_ENABLED           1
+/* UART 4 configuration */
+#define UART4_MODE              MODE_DTE
+#define UART4_IR                NO_IRDA
+#define UART4_ENABLED           0	/* Disable UART 4 as its pins are shared with ATA */
+/* UART 5 configuration */
+#define UART5_MODE              MODE_DTE
+#define UART5_IR                NO_IRDA
+#define UART5_ENABLED           1
+
+#define MXC_LL_EXTUART_PADDR	(CS4_BASE_ADDR + 0x10000)
+#define MXC_LL_EXTUART_VADDR	CS4_IO_ADDRESS(MXC_LL_EXTUART_PADDR)
+#undef  MXC_LL_EXTUART_16BIT_BUS
+
+#define MXC_LL_UART_PADDR	UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR	AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+
+/*!
+ * @name Memory Size parameters
+ */
+/*! @{ */
+/*!
+ * Size of SDRAM memory
+ */
+/* #define SDRAM_MEM_SIZE          SZ_64M*/
+/*!
+ * Size of IPU buffer memory
+ */
+#define MXCIPU_MEM_SIZE         SZ_8M
+/*!
+ * Size of MBX buffer memory
+ */
+#define MXC_MBX_MEM_SIZE        SZ_16M
+/*!
+ * Size of memory available to kernel
+ */
+/*#define MEM_SIZE                (SDRAM_MEM_SIZE - MXCIPU_MEM_SIZE - MXC_MBX_MEM_SIZE)*/
+/*!
+ * Physical address start of IPU buffer memory
+ */
+#define MXCIPU_MEM_ADDRESS      (PHYS_OFFSET + MEM_SIZE)
+/*! @} */
+
+/*!
+ * @name Keypad Configurations FIXME
+ */
+/*! @{ */
+/*!
+ * Maximum number of rows (0 to 7)
+ */
+#define MAXROW                  8
+/*!
+ * Maximum number of columns (0 to 7)
+ */
+#define MAXCOL                  8
+/*! @} */
+
+
+
+#define IO_CS4_BASE_ADDRESS        IO_ADDRESS(CS4_BASE_ADDR)
+#define IO_FAST_CS_BASE_ADDRESS    (IO_CS4_BASE_ADDRESS|(1<<23))
+
+ /*!
+  * @name  Defines Base address and IRQ used for Ethernet Controller
+ MXC Boards
+  */
+ /*! @{*/
+
+ /*! This is I/O Base address used to access registers of SMC9117 on
+MXC lite */
+#define SMC9117_INT     IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
+#define SMC9117_BASE_ADDRESS    (CS4_BASE_ADDR)
+#define SMC9117_IOBASE_ADDRESS    (IO_CS4_BASE_ADDRESS)
+
+
+#define MXC_PMIC_INT_LINE	IOMUX_TO_IRQ(MX31_PIN_GPIO1_3)
+
+#define AHB_FREQ                133000000
+#define IPG_FREQ                66500000
+
+
+
+
+
+#endif				/* __ASM_ARM_ARCH_BOARD_MX31LITE_H_ */
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c
new file mode 100644
index 000000000000..23ee6ab96a1e
--- /dev/null
+++ b/arch/arm/mach-mx3/mx31lite.c
@@ -0,0 +1,561 @@
+/*
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2005-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/serial_8250.h>
+#include <linux/input.h>
+#include <linux/nodemask.h>
+#include <linux/clk.h>
+#if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE)
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach/flash.h>
+#endif
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/keypad.h>
+#include <asm/arch/memory.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clock.h>
+
+#include "board-mx31lite.h"
+#include "crm_regs.h"
+#include "iomux.h"
+/*!
+ * @file mx31lite.c
+ *
+ * @brief This file contains the board specific initialization routines.
+ *
+ * @ingroup System
+ */
+
+extern void mxc_map_io(void);
+extern void mxc_init_irq(void);
+extern void mxc_cpu_init(void) __init;
+extern void mx31lite_gpio_init(void) __init;
+extern struct sys_timer mxc_timer;
+extern void mxc_cpu_common_init(void);
+extern int mxc_clocks_init(void);
+extern void __init early_console_setup(char *);
+
+static void mxc_nop_release(struct device *dev)
+{
+	/* Nothing */
+}
+
+unsigned long board_get_ckih_rate(void)
+{
+  return 26000000;
+}
+
+#if defined(CONFIG_KEYBOARD_MXC) || defined(CONFIG_KEYBOARD_MXC_MODULE)
+
+/* Keypad keycodes for the EVB 8x8
+ * keypad.  POWER and PTT keys don't generate
+ * any interrupts via this driver so they are
+ * not support. Change any keys as u like!
+ */
+static u16 keymapping[64] = {
+	KEY_SELECT, KEY_LEFT, KEY_DOWN, KEY_RIGHT,
+	KEY_UP, KEY_F12, KEY_END, KEY_BACK,
+	KEY_F1, KEY_SENDFILE, KEY_HOME, KEY_F6,
+	KEY_VOLUMEUP, KEY_F8, KEY_F9, KEY_F10,
+	KEY_3, KEY_2, KEY_1, KEY_4,
+	KEY_VOLUMEDOWN, KEY_7, KEY_5, KEY_6,
+	KEY_9, KEY_LEFTSHIFT, KEY_8, KEY_0,
+	KEY_KPASTERISK, KEY_RECORD, KEY_Q, KEY_W,
+	KEY_A, KEY_S, KEY_D, KEY_E,
+	KEY_F, KEY_R, KEY_T, KEY_Y,
+	KEY_TAB, KEY_F7, KEY_CAPSLOCK, KEY_Z,
+	KEY_X, KEY_C, KEY_V, KEY_G,
+	KEY_B, KEY_H, KEY_N, KEY_M,
+	KEY_J, KEY_K, KEY_U, KEY_I,
+	KEY_SPACE, KEY_F2, KEY_DOT, KEY_ENTER,
+	KEY_L, KEY_BACKSPACE, KEY_P, KEY_O,
+};
+
+static struct resource mxc_kpp_resources[] = {
+	[0] = {
+		.start	= INT_KPP,
+		.end	= INT_KPP,
+		.flags	= IORESOURCE_IRQ,
+	}
+};
+
+static struct keypad_data evb_8_by_8_keypad = {
+	.rowmax = 8,
+	.colmax = 8,
+	.irq = INT_KPP,
+	.learning = 0,
+	.delay = 2,
+	.matrix = keymapping,
+};
+
+/* mxc keypad driver */
+static struct platform_device mxc_keypad_device = {
+	.name = "mxc_keypad",
+	.id = 0,
+	.num_resources	= ARRAY_SIZE(mxc_kpp_resources),
+	.resource	= mxc_kpp_resources,
+	.dev = {
+		.release = mxc_nop_release,
+		.platform_data = &evb_8_by_8_keypad,
+		},
+};
+
+static void mxc_init_keypad(void)
+{
+	(void)platform_device_register(&mxc_keypad_device);
+}
+#else
+static inline void mxc_init_keypad(void)
+{
+}
+#endif
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+/*!
+ * The serial port definition structure. The fields contain:
+ * {UART, CLK, PORT, IRQ, FLAGS}
+ */
+static struct plat_serial8250_port serial_platform_data[] = {
+	{
+	 .membase = (void __iomem *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
+	 .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTA),
+	 .irq = EXPIO_INT_XUART_INTA,
+	 .uartclk = 14745600,
+	 .regshift = 0,
+	 .iotype = UPIO_MEM,
+	 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+	 },
+	{
+	 .membase = (void __iomem *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
+	 .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTB),
+	 .irq = EXPIO_INT_XUART_INTB,
+	 .uartclk = 14745600,
+	 .regshift = 0,
+	 .iotype = UPIO_MEM,
+	 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+	 },
+	{},
+};
+
+/*!
+ * REVISIT: document me
+ */
+static struct platform_device serial_device = {
+	.name = "serial8250",
+	.id = 0,
+	.dev = {
+		.platform_data = serial_platform_data,
+		},
+};
+
+/*!
+ * REVISIT: document me
+ */
+static int __init mxc_init_extuart(void)
+{
+	return platform_device_register(&serial_device);
+}
+#else
+static inline int mxc_init_extuart(void)
+{
+	return 0;
+}
+#endif
+/* MTD NOR flash */
+
+#if defined(CONFIG_MTD_MXC) || defined(CONFIG_MTD_MXC_MODULE)
+
+static struct mtd_partition mxc_nor_partitions[] = {
+	{
+	 .name = "Bootloader",
+	 .size = 512 * 1024,
+	 .offset = 0x00000000,
+	 .mask_flags = MTD_WRITEABLE	/* force read-only */
+	 },
+	{
+	 .name = "Kernel",
+	 .size = MTDPART_SIZ_FULL,
+	 .offset = MTDPART_OFS_APPEND,
+	 .mask_flags = 0},
+};
+
+static struct flash_platform_data mxc_flash_data = {
+	.map_name = "cfi_probe",
+	.width = 2,
+	.parts = mxc_nor_partitions,
+	.nr_parts = ARRAY_SIZE(mxc_nor_partitions),
+};
+
+static struct resource mxc_flash_resource = {
+	.start = 0xa0000000,
+	.end = 0xa0000000 + 0x02000000 - 1,
+	.flags = IORESOURCE_MEM,
+
+};
+
+static struct platform_device mxc_nor_mtd_device = {
+	.name = "mxc_nor_flash",
+	.id = 0,
+	.dev = {
+		.release = mxc_nop_release,
+		.platform_data = &mxc_flash_data,
+		},
+	.num_resources = 1,
+	.resource = &mxc_flash_resource,
+};
+
+static void mxc_init_nor_mtd(void)
+{
+	(void)platform_device_register(&mxc_nor_mtd_device);
+}
+#else
+static void mxc_init_nor_mtd(void)
+{
+}
+#endif
+
+/* MTD NAND flash */
+
+#if defined(CONFIG_MTD_NAND_MXC) || defined(CONFIG_MTD_NAND_MXC_MODULE) || \
+    defined(CONFIG_MTD_NAND_MXC_V2) || defined(CONFIG_MTG_NAND_MXC_V2_MODULE)
+
+static struct mtd_partition mxc_nand_partitions[4] = {
+	{
+	 .name = "nand.kernel",
+	 .offset = MTDPART_OFS_APPEND,
+	 .size = 2 * 1024 * 1024},
+	{
+	 .name = "nand.rootfs",
+	 .offset = MTDPART_OFS_APPEND,
+	 .size = MTDPART_SIZ_FULL},
+};
+
+static struct flash_platform_data mxc_nand_data = {
+	.parts = mxc_nand_partitions,
+	.nr_parts = ARRAY_SIZE(mxc_nand_partitions),
+	.width = 1,
+};
+
+static struct platform_device mxc_nand_mtd_device = {
+	.name = "mxc_nand_flash",
+	.id = 0,
+	.dev = {
+		.release = mxc_nop_release,
+		.platform_data = &mxc_nand_data,
+		},
+};
+
+static void mxc_init_nand_mtd(void)
+{
+	if (__raw_readl(MXC_CCM_RCSR) & MXC_CCM_RCSR_NF16B) {
+		mxc_nand_data.width = 2;
+	}
+	(void)platform_device_register(&mxc_nand_mtd_device);
+}
+#else
+static inline void mxc_init_nand_mtd(void)
+{
+}
+#endif
+
+#include <linux/spi/spi.h>
+
+static struct spi_board_info mxc_spi_board_info[] __initdata = {
+	{
+	 .modalias = "pmic_spi",
+	 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+	 .max_speed_hz = 4000000,
+	 .bus_num = 2,
+	 .chip_select = 0,
+	 },
+};
+
+/*!
+ * Board specific fixup function. It is called by \b setup_arch() in
+ * setup.c file very early on during kernel starts. It allows the user to
+ * statically fill in the proper values for the passed-in parameters. None of
+ * the parameters is used currently.
+ *
+ * @param  desc         pointer to \b struct \b machine_desc
+ * @param  tags         pointer to \b struct \b tag
+ * @param  cmdline      pointer to the command line
+ * @param  mi           pointer to \b struct \b meminfo
+ */
+static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
+				   char **cmdline, struct meminfo *mi)
+{
+	struct tag *t;
+#ifdef CONFIG_KGDB_8250
+	int i;
+	for (i = 0;
+	     i <
+	     (sizeof(serial_platform_data) / sizeof(serial_platform_data[0]));
+	     i += 1)
+		kgdb8250_add_platform_port(i, &serial_platform_data[i]);
+#endif
+
+	mxc_cpu_init();
+
+#ifdef CONFIG_DISCONTIGMEM
+	do {
+		int nid;
+		mi->nr_banks = MXC_NUMNODES;
+		for (nid = 0; nid < mi->nr_banks; nid++) {
+			SET_NODE(mi, nid);
+		}
+	} while (0);
+#endif
+}
+
+/* ethernet driver initialization */
+
+#if defined(CONFIG_SMC911X) || defined(CONFIG_SMSC911X)
+static struct resource smc911x_resources[] = {
+         [0] = {
+                 .start  = SMC9117_BASE_ADDRESS ,
+                 .end    = (SMC9117_BASE_ADDRESS + 0xfffff),
+                 .flags  = IORESOURCE_MEM,
+         },
+         [1] = {
+
+
+                 .start  = IOMUX_TO_IRQ(MX31_PIN_SFS6) ,
+                 .end    = IOMUX_TO_IRQ(MX31_PIN_SFS6) ,
+                 .flags  = IORESOURCE_IRQ,
+         },
+};
+
+static struct platform_device smc911x_device = {
+#ifdef CONFIG_SMSC911X
+         .name           = "smsc911x", /* official driver from smsc */
+#else
+         .name           = "smc911x", /* driver from stock linux kernel
+                                         this driver does not work
+for now
+                                         with 16BIT interface */
+#endif
+         .id             = 0,
+         .num_resources  = ARRAY_SIZE(smc911x_resources),
+         .resource       = smc911x_resources,
+};
+
+static void mxc_init_eth(void)
+{
+         /* init irq gpio */
+         printk("Irq init for eth0\n");
+
+         mxc_request_iomux(MX31_PIN_SFS6, OUTPUTCONFIG_GPIO,
+                           INPUTCONFIG_GPIO);
+         mxc_set_gpio_direction(MX31_PIN_SFS6, 1);
+
+        /* disable interrupts */
+
+        (void)platform_device_register(&smc911x_device);
+}
+#else
+
+static void mxc_init_eth(void)
+{
+}
+#endif
+
+
+#if defined(CONFIG_MXC_PMIC_MC13783) && defined(CONFIG_SND_MXC_PMIC)
+extern void gpio_activate_audio_ports(void);
+
+static void __init mxc_init_pmic_audio(void)
+{
+	struct clk *pll_clk;
+	struct clk *ssi_clk;
+	struct clk *ckih_clk;
+	struct clk *cko_clk;
+
+	/* Enable 26 mhz clock on CKO1 for PMIC audio */
+	ckih_clk = clk_get(NULL, "ckih");
+	cko_clk = clk_get(NULL, "cko1_clk");
+	if (IS_ERR(ckih_clk) || IS_ERR(cko_clk)) {
+		printk(KERN_ERR "Unable to set CKO1 output to CKIH\n");
+	} else {
+		clk_set_parent(cko_clk, ckih_clk);
+		clk_set_rate(cko_clk, clk_get_rate(ckih_clk));
+		clk_enable(cko_clk);
+	}
+	clk_put(ckih_clk);
+	clk_put(cko_clk);
+
+	/* Assign USBPLL to be used by SSI1/2 */
+	pll_clk = clk_get(NULL, "usb_pll");
+	ssi_clk = clk_get(NULL, "ssi_clk.0");
+	clk_set_parent(ssi_clk, pll_clk);
+	clk_enable(ssi_clk);
+	clk_put(ssi_clk);
+
+	ssi_clk = clk_get(NULL, "ssi_clk.1");
+	clk_set_parent(ssi_clk, pll_clk);
+	clk_enable(ssi_clk);
+	clk_put(ssi_clk);
+	clk_put(pll_clk);
+
+	gpio_activate_audio_ports();
+}
+#else
+static void __inline mxc_init_pmic_audio(void)
+{
+}
+#endif
+
+/*!
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+	mxc_cpu_common_init();
+
+	mxc_clocks_init();
+	early_console_setup(saved_command_line);
+
+	mxc_init_pmic_audio();
+
+	/* Enable 26 MHz clock on CKO1 for MC13783 audio */
+	mxc_ccm_modify_reg(MXC_CCM_COSR, 0x00000fff, 0x00000208);
+
+	mxc_gpio_init();
+
+	mx31lite_gpio_init();
+
+	mxc_init_keypad();
+	mxc_init_nor_mtd();
+	mxc_init_nand_mtd();
+	mxc_init_eth();
+
+	spi_register_board_info(mxc_spi_board_info,
+				ARRAY_SIZE(mxc_spi_board_info));
+
+	/* mxc_init_fb(); */
+	/* mxc_init_ir(); */
+}
+
+#define PLL_PCTL_REG(pd, mfd, mfi, mfn)		\
+	((((pd) - 1) << 26) + (((mfd) - 1) << 16) + ((mfi)  << 10) + mfn)
+
+/* For 26MHz input clock */
+#define PLL_532MHZ		PLL_PCTL_REG(1, 13, 10, 3)
+#define PLL_399MHZ		PLL_PCTL_REG(1, 52, 7, 35)
+#define PLL_133MHZ		PLL_PCTL_REG(2, 26, 5, 3)
+
+/* For 27MHz input clock */
+#define PLL_532_8MHZ		PLL_PCTL_REG(1, 15, 9, 13)
+#define PLL_399_6MHZ		PLL_PCTL_REG(1, 18, 7, 7)
+#define PLL_133_2MHZ		PLL_PCTL_REG(3, 5, 7, 2)
+
+#define PDR0_REG(mcu, max, hsp, ipg, nfc)	\
+	(MXC_CCM_PDR0_MCU_DIV_##mcu | MXC_CCM_PDR0_MAX_DIV_##max | \
+	 MXC_CCM_PDR0_HSP_DIV_##hsp | MXC_CCM_PDR0_IPG_DIV_##ipg | \
+	 MXC_CCM_PDR0_NFC_DIV_##nfc)
+
+/* working point(wp): 0 - 133MHz; 1 - 266MHz; 2 - 399MHz; 3 - 532MHz */
+/* 26MHz input clock table */
+static struct cpu_wp cpu_wp_26[] = {
+	{
+	 .pll_reg = PLL_532MHZ,
+	 .pll_rate = 532000000,
+	 .cpu_rate = 133000000,
+	 .pdr0_reg = PDR0_REG(4, 4, 4, 2, 6),},
+	{
+	 .pll_reg = PLL_532MHZ,
+	 .pll_rate = 532000000,
+	 .cpu_rate = 266000000,
+	 .pdr0_reg = PDR0_REG(2, 4, 4, 2, 6),},
+	{
+	 .pll_reg = PLL_399MHZ,
+	 .pll_rate = 399000000,
+	 .cpu_rate = 399000000,
+	 .pdr0_reg = PDR0_REG(1, 3, 3, 2, 6),},
+	{
+	 .pll_reg = PLL_532MHZ,
+	 .pll_rate = 532000000,
+	 .cpu_rate = 532000000,
+	 .pdr0_reg = PDR0_REG(1, 4, 4, 2, 6),},
+};
+
+/* 27MHz input clock table */
+static struct cpu_wp cpu_wp_27[] = {
+	{
+	 .pll_reg = PLL_532_8MHZ,
+	 .pll_rate = 532800000,
+	 .cpu_rate = 133200000,
+	 .pdr0_reg = PDR0_REG(4, 4, 4, 2, 6),},
+	{
+	 .pll_reg = PLL_532_8MHZ,
+	 .pll_rate = 532800000,
+	 .cpu_rate = 266400000,
+	 .pdr0_reg = PDR0_REG(2, 4, 4, 2, 6),},
+	{
+	 .pll_reg = PLL_399_6MHZ,
+	 .pll_rate = 399600000,
+	 .cpu_rate = 399600000,
+	 .pdr0_reg = PDR0_REG(1, 3, 3, 2, 6),},
+	{
+	 .pll_reg = PLL_532_8MHZ,
+	 .pll_rate = 532800000,
+	 .cpu_rate = 532800000,
+	 .pdr0_reg = PDR0_REG(1, 4, 4, 2, 6),},
+};
+
+struct cpu_wp *get_cpu_wp(int *wp)
+{
+	*wp = 4;
+	return cpu_wp_26;
+}
+
+/*
+ * The following uses standard kernel macros define in arch.h in order to
+ * initialize __mach_desc_MX31LITE data structure.
+ */
+/* *INDENT-OFF* */
+MACHINE_START(MX31LITE, "Freescale i.MX31 litekit")
+	//.phys_ram       = PHYS_OFFSET_ASM,
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+	.phys_io        = CS4_BASE_ADDR,
+	.io_pg_offst    = ((CS4_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+#else
+	.phys_io        = AIPS1_BASE_ADDR,
+	.io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+#endif
+	.boot_params    = PHYS_OFFSET + 0x100,
+	.fixup          = fixup_mxc_board,
+	.map_io         = mxc_map_io,
+	.init_irq       = mxc_init_irq,
+	.init_machine   = mxc_board_init,
+	.timer          = &mxc_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31lite_gpio.c b/arch/arm/mach-mx3/mx31lite_gpio.c
new file mode 100644
index 000000000000..f23b5d8b20b8
--- /dev/null
+++ b/arch/arm/mach-mx3/mx31lite_gpio.c
@@ -0,0 +1,1453 @@
+/*
+ * Copyright 2005-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include "board-mx31lite.h"
+#include "iomux.h"
+
+/*!
+ * @file mx31lite_gpio.c
+ *
+ * @brief This file contains all the GPIO setup functions for the board.
+ *
+ * @ingroup GPIO
+ */
+
+void gpio_activate_audio_ports(void);
+
+/*!
+ * This system-wise GPIO function initializes the pins during system startup.
+ * All the statically linked device drivers should put the proper GPIO initialization
+ * code inside this function. It is called by \b fixup_mx31lite() during
+ * system startup. This function is board specific.
+ */
+void mx31lite_gpio_init(void)
+{
+	/* config CS4 */
+	mxc_request_iomux(MX31_PIN_CS4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+
+	/* Connect DAM ports 4 & 5 to enable audio I/O */
+	gpio_activate_audio_ports();
+}
+
+/*!
+ * This function configures the IOMux block for MC13783 standard operations.
+ *
+ */
+void gpio_mc13783_active(void)
+{
+	mxc_request_iomux(MX31_PIN_GPIO1_3, OUTPUTCONFIG_GPIO,
+			  INPUTCONFIG_GPIO);
+	mxc_set_gpio_direction(MX31_PIN_GPIO1_3, 1);
+	/* mxc_set_gpio_edge_ctrl(MX31_PIN_GPIO1_3, GPIO_INT_RISE_EDGE); */
+}
+
+/*!
+ * This function clears the MC13783 intrrupt.
+ *
+ */
+void gpio_mc13783_clear_int(void)
+{
+}
+
+/*!
+ * This function return the SPI connected to MC13783.
+ *
+ */
+int gpio_mc13783_get_spi(void)
+{
+	return 1;
+}
+
+/*!
+ * This function return the SPI smave select for MC13783.
+ *
+ */
+int gpio_mc13783_get_ss(void)
+{
+	return 0;
+}
+
+
+/*!
+ * Setup GPIO for a UART port to be active
+ *
+ * @param  port         a UART port
+ * @param  no_irda      indicates if the port is used for SIR
+ */
+void gpio_uart_active(int port, int no_irda)
+{
+	/*
+	 * Configure the IOMUX control registers for the UART signals
+	 */
+	switch (port) {
+		/* UART 1 IOMUX Configs */
+	case 0:
+		mxc_request_iomux(MX31_PIN_RXD1, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_TXD1, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_RTS1, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_CTS1, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_DTR_DCE1, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_DSR_DCE1, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_RI_DCE1, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_DCD_DCE1, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+
+		break;
+		/* UART 2 IOMUX Configs */
+	case 1:
+		mxc_request_iomux(MX31_PIN_TXD2, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_RXD2, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+
+		if (no_irda == 1) {
+			mxc_request_iomux(MX31_PIN_RTS2, OUTPUTCONFIG_FUNC,
+					  INPUTCONFIG_FUNC);
+			mxc_request_iomux(MX31_PIN_CTS2, OUTPUTCONFIG_FUNC,
+					  INPUTCONFIG_FUNC);
+			mxc_request_iomux(MX31_PIN_DTR_DCE2, OUTPUTCONFIG_FUNC,
+					  INPUTCONFIG_FUNC);
+		} else {
+		}
+
+		break;
+		/* UART 3 IOMUX Configs */
+	case 2:
+		mxc_request_iomux(MX31_PIN_CSPI3_MOSI, OUTPUTCONFIG_ALT1,
+				  INPUTCONFIG_ALT1);
+		mxc_request_iomux(MX31_PIN_CSPI3_MISO, OUTPUTCONFIG_ALT1,
+				  INPUTCONFIG_ALT1);
+		mxc_request_iomux(MX31_PIN_CSPI3_SCLK, OUTPUTCONFIG_ALT1,
+				  INPUTCONFIG_ALT1);
+		mxc_request_iomux(MX31_PIN_CSPI3_SPI_RDY, OUTPUTCONFIG_ALT1,
+				  INPUTCONFIG_ALT1);
+
+		break;
+		/* UART 4 IOMUX Configs */
+	case 3:
+		mxc_request_iomux(MX31_PIN_ATA_CS0, OUTPUTCONFIG_ALT1,
+				  INPUTCONFIG_ALT1);
+		mxc_request_iomux(MX31_PIN_ATA_CS1, OUTPUTCONFIG_ALT1,
+				  INPUTCONFIG_ALT1);
+		mxc_request_iomux(MX31_PIN_ATA_DIOR, OUTPUTCONFIG_ALT1,
+				  INPUTCONFIG_ALT1);
+		mxc_request_iomux(MX31_PIN_ATA_DIOW, OUTPUTCONFIG_ALT1,
+				  INPUTCONFIG_ALT1);
+
+		break;
+		/* UART 5 IOMUX Configs */
+	case 4:
+		mxc_request_iomux(MX31_PIN_PC_VS2, OUTPUTCONFIG_ALT2,
+				  INPUTCONFIG_ALT2);
+		mxc_request_iomux(MX31_PIN_PC_RST, OUTPUTCONFIG_ALT2,
+				  INPUTCONFIG_ALT2);
+		mxc_request_iomux(MX31_PIN_PC_BVD1, OUTPUTCONFIG_ALT2,
+				  INPUTCONFIG_ALT2);
+		mxc_request_iomux(MX31_PIN_PC_BVD2, OUTPUTCONFIG_ALT2,
+				  INPUTCONFIG_ALT2);
+
+		break;
+	default:
+		break;
+	}
+
+	/*
+	 * TODO: Configure the Pad registers for the UART pins
+	 */
+}
+
+/*!
+ * Setup GPIO for a UART port to be inactive
+ *
+ * @param  port         a UART port
+ * @param  no_irda      indicates if the port is used for SIR
+ */
+void gpio_uart_inactive(int port, int no_irda)
+{
+	switch (port) {
+	case 0:
+		mxc_request_gpio(MX31_PIN_RXD1);
+		mxc_request_gpio(MX31_PIN_TXD1);
+		mxc_request_gpio(MX31_PIN_RTS1);
+		mxc_request_gpio(MX31_PIN_CTS1);
+		mxc_request_gpio(MX31_PIN_DTR_DCE1);
+		mxc_request_gpio(MX31_PIN_DSR_DCE1);
+		mxc_request_gpio(MX31_PIN_RI_DCE1);
+		mxc_request_gpio(MX31_PIN_DCD_DCE1);
+
+		mxc_free_iomux(MX31_PIN_RXD1, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_GPIO);
+		mxc_free_iomux(MX31_PIN_TXD1, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_GPIO);
+		mxc_free_iomux(MX31_PIN_RTS1, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_GPIO);
+		mxc_free_iomux(MX31_PIN_CTS1, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_GPIO);
+		mxc_free_iomux(MX31_PIN_DTR_DCE1, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_GPIO);
+		mxc_free_iomux(MX31_PIN_DSR_DCE1, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_GPIO);
+		mxc_free_iomux(MX31_PIN_RI_DCE1, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_GPIO);
+		mxc_free_iomux(MX31_PIN_DCD_DCE1, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_GPIO);
+
+		break;
+	case 1:
+		mxc_request_gpio(MX31_PIN_TXD2);
+		mxc_request_gpio(MX31_PIN_RXD2);
+
+		mxc_free_iomux(MX31_PIN_TXD2, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_GPIO);
+		mxc_free_iomux(MX31_PIN_RXD2, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_GPIO);
+
+		if (no_irda == 1) {
+			mxc_request_gpio(MX31_PIN_DTR_DCE2);
+			mxc_free_iomux(MX31_PIN_DTR_DCE2, OUTPUTCONFIG_GPIO,
+				       INPUTCONFIG_GPIO);
+
+		} else {
+		}
+		break;
+	case 2:
+		break;
+	case 3:
+		mxc_request_gpio(MX31_PIN_ATA_CS0);
+		mxc_request_gpio(MX31_PIN_ATA_CS1);
+		mxc_request_gpio(MX31_PIN_ATA_DIOR);
+		mxc_request_gpio(MX31_PIN_ATA_DIOW);
+
+		mxc_free_iomux(MX31_PIN_ATA_CS0, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_GPIO);
+		mxc_free_iomux(MX31_PIN_ATA_CS1, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_GPIO);
+		mxc_free_iomux(MX31_PIN_ATA_DIOR, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_GPIO);
+		mxc_free_iomux(MX31_PIN_ATA_DIOW, OUTPUTCONFIG_GPIO,
+			       INPUTCONFIG_GPIO);
+
+		break;
+	case 4:
+		break;
+	default:
+		break;
+	}
+}
+
+/*!
+ * Configure the IOMUX GPR register to receive shared SDMA UART events
+ *
+ * @param  port         a UART port
+ */
+void config_uartdma_event(int port)
+{
+	switch (port) {
+	case 1:
+		/* Configure to receive UART 2 SDMA events */
+		mxc_iomux_set_gpr(MUX_PGP_FIRI, false);
+		break;
+	case 2:
+		/* Configure to receive UART 3 SDMA events */
+		mxc_iomux_set_gpr(MUX_CSPI1_UART3, true);
+		break;
+	case 4:
+		/* Configure to receive UART 5 SDMA events */
+		mxc_iomux_set_gpr(MUX_CSPI3_UART5_SEL, true);
+		break;
+	default:
+		break;
+	}
+}
+
+EXPORT_SYMBOL(gpio_uart_active);
+EXPORT_SYMBOL(gpio_uart_inactive);
+EXPORT_SYMBOL(config_uartdma_event);
+
+/*!
+ * Setup GPIO for Keypad  to be active
+ *
+ */
+void gpio_keypad_active(void)
+{
+	/*
+	 * Configure the IOMUX control register for keypad signals.
+	 */
+	mxc_request_iomux(MX31_PIN_KEY_COL0, OUTPUTCONFIG_FUNC,
+			  INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_KEY_COL1, OUTPUTCONFIG_FUNC,
+			  INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_KEY_COL2, OUTPUTCONFIG_FUNC,
+			  INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_KEY_COL3, OUTPUTCONFIG_FUNC,
+			  INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_KEY_COL4, OUTPUTCONFIG_FUNC,
+			  INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_KEY_COL5, OUTPUTCONFIG_FUNC,
+			  INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_KEY_COL6, OUTPUTCONFIG_FUNC,
+			  INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_KEY_COL7, OUTPUTCONFIG_FUNC,
+			  INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_KEY_ROW0, OUTPUTCONFIG_FUNC,
+			  INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_KEY_ROW1, OUTPUTCONFIG_FUNC,
+			  INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_KEY_ROW2, OUTPUTCONFIG_FUNC,
+			  INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_KEY_ROW3, OUTPUTCONFIG_FUNC,
+			  INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_KEY_ROW4, OUTPUTCONFIG_FUNC,
+			  INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_KEY_ROW5, OUTPUTCONFIG_FUNC,
+			  INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_KEY_ROW6, OUTPUTCONFIG_FUNC,
+			  INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_KEY_ROW7, OUTPUTCONFIG_FUNC,
+			  INPUTCONFIG_FUNC);
+}
+
+EXPORT_SYMBOL(gpio_keypad_active);
+
+/*!
+ * Setup GPIO for Keypad to be inactive
+ *
+ */
+void gpio_keypad_inactive(void)
+{
+	mxc_request_iomux(MX31_PIN_KEY_COL0, OUTPUTCONFIG_GPIO,
+			  INPUTCONFIG_GPIO);
+	mxc_request_iomux(MX31_PIN_KEY_COL1, OUTPUTCONFIG_GPIO,
+			  INPUTCONFIG_GPIO);
+	mxc_request_iomux(MX31_PIN_KEY_COL2, OUTPUTCONFIG_GPIO,
+			  INPUTCONFIG_GPIO);
+	mxc_request_iomux(MX31_PIN_KEY_COL3, OUTPUTCONFIG_GPIO,
+			  INPUTCONFIG_GPIO);
+	mxc_request_iomux(MX31_PIN_KEY_COL4, OUTPUTCONFIG_GPIO,
+			  INPUTCONFIG_GPIO);
+	mxc_request_iomux(MX31_PIN_KEY_COL5, OUTPUTCONFIG_GPIO,
+			  INPUTCONFIG_GPIO);
+	mxc_request_iomux(MX31_PIN_KEY_COL6, OUTPUTCONFIG_GPIO,
+			  INPUTCONFIG_GPIO);
+	mxc_request_iomux(MX31_PIN_KEY_COL7, OUTPUTCONFIG_GPIO,
+			  INPUTCONFIG_GPIO);
+	mxc_request_iomux(MX31_PIN_KEY_ROW0, OUTPUTCONFIG_GPIO,
+			  INPUTCONFIG_GPIO);
+	mxc_request_iomux(MX31_PIN_KEY_ROW1, OUTPUTCONFIG_GPIO,
+			  INPUTCONFIG_GPIO);
+	mxc_request_iomux(MX31_PIN_KEY_ROW2, OUTPUTCONFIG_GPIO,
+			  INPUTCONFIG_GPIO);
+	mxc_request_iomux(MX31_PIN_KEY_ROW3, OUTPUTCONFIG_GPIO,
+			  INPUTCONFIG_GPIO);
+	mxc_request_iomux(MX31_PIN_KEY_ROW4, OUTPUTCONFIG_GPIO,
+			  INPUTCONFIG_GPIO);
+	mxc_request_iomux(MX31_PIN_KEY_ROW5, OUTPUTCONFIG_GPIO,
+			  INPUTCONFIG_GPIO);
+	mxc_request_iomux(MX31_PIN_KEY_ROW6, OUTPUTCONFIG_GPIO,
+			  INPUTCONFIG_GPIO);
+	mxc_request_iomux(MX31_PIN_KEY_ROW7, OUTPUTCONFIG_GPIO,
+			  INPUTCONFIG_GPIO);
+}
+
+EXPORT_SYMBOL(gpio_keypad_inactive);
+
+/*!
+ * Setup GPIO for a CSPI device to be active
+ *
+ * @param  cspi_mod         an CSPI device
+ */
+void gpio_spi_active(int cspi_mod)
+{
+        printk("\n\nspi_active %d\n",cspi_mod);
+	switch (cspi_mod) {
+	case 0:
+		/* SPI1 */
+		mxc_request_iomux(MX31_PIN_CSPI1_MISO, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_CSPI1_MOSI, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_CSPI1_SCLK, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_CSPI1_SPI_RDY, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_CSPI1_SS0, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_CSPI1_SS1, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_CSPI1_SS2, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		break;
+	case 1:
+		/* SPI2 */
+		mxc_request_iomux(MX31_PIN_CSPI2_MISO, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_CSPI2_MOSI, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_CSPI2_SCLK, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_CSPI2_SPI_RDY, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_CSPI2_SS0, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_CSPI2_SS1, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_CSPI2_SS2, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		break;
+	case 2:
+		/* SPI3 */
+		/*
+		   mxc_request_iomux(MX31_PIN_CSPI2_MISO, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+		   mxc_request_iomux(MX31_PIN_CSPI2_MOSI, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+		   mxc_request_iomux(MX31_PIN_CSPI2_SCLK, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+		   mxc_request_iomux(MX31_PIN_CSPI2_SPI_RDY, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+		   mxc_request_iomux(MX31_PIN_CSPI2_SS0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+		   mxc_request_iomux(MX31_PIN_CSPI2_SS1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+		   mxc_request_iomux(MX31_PIN_CSPI2_SS2, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+		 */
+		break;
+	default:
+		break;
+	}
+}
+
+/*!
+ * Setup 1-Wire to be active
+ */
+void gpio_owire_active(void)
+{
+	/*
+	 * Configure the IOMUX control register for 1-wire signals.
+	 */
+	iomux_config_mux(MX31_PIN_BATT_LINE, OUTPUTCONFIG_FUNC,
+			 INPUTCONFIG_FUNC);
+	iomux_config_pad(MX31_PIN_BATT_LINE, PAD_CTL_LOOPBACK);
+}
+
+/*!
+ * Setup 1-Wire to be active
+ */
+void gpio_owire_inactive(void)
+{
+	/*
+	 * Configure the IOMUX control register for 1-wire signals.
+	 */
+	iomux_config_mux(MX31_PIN_BATT_LINE, OUTPUTCONFIG_GPIO,
+			 INPUTCONFIG_GPIO);
+}
+
+EXPORT_SYMBOL(gpio_owire_active);
+EXPORT_SYMBOL(gpio_owire_inactive);
+
+/*!
+ * Setup GPIO for a CSPI device to be inactive
+ *
+ * @param  cspi_mod         a CSPI device
+ */
+void gpio_spi_inactive(int cspi_mod)
+{
+  /* Do nothing as CSPI pins doesn't have/support GPIO mode */
+}
+
+/*!
+ * Setup GPIO for an I2C device to be active
+ *
+ * @param  i2c_num         an I2C device
+ */
+void gpio_i2c_active(int i2c_num)
+{
+	switch (i2c_num) {
+	case 0:
+		mxc_request_iomux(MX31_PIN_I2C_CLK, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_I2C_DAT, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		break;
+	case 1:
+		mxc_request_iomux(MX31_PIN_CSPI2_MOSI, OUTPUTCONFIG_ALT1,
+				  INPUTCONFIG_ALT1);
+		mxc_request_iomux(MX31_PIN_CSPI2_MISO, OUTPUTCONFIG_ALT1,
+				  INPUTCONFIG_ALT1);
+		break;
+	case 2:
+		mxc_request_iomux(MX31_PIN_CSPI2_SS2, OUTPUTCONFIG_ALT1,
+				  INPUTCONFIG_ALT1);
+		mxc_request_iomux(MX31_PIN_CSPI2_SCLK, OUTPUTCONFIG_ALT1,
+				  INPUTCONFIG_ALT1);
+		break;
+	default:
+		break;
+	}
+
+}
+
+/*!
+ * Setup GPIO for an I2C device to be inactive
+ *
+ * @param  i2c_num         an I2C device
+ */
+void gpio_i2c_inactive(int i2c_num)
+{
+	switch (i2c_num) {
+	case 0:
+		mxc_request_iomux(MX31_PIN_I2C_CLK, OUTPUTCONFIG_GPIO,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_I2C_DAT, OUTPUTCONFIG_GPIO,
+				  INPUTCONFIG_FUNC);
+		break;
+	case 1:
+		mxc_request_iomux(MX31_PIN_CSPI2_MOSI, OUTPUTCONFIG_GPIO,
+				  INPUTCONFIG_ALT1);
+		mxc_request_iomux(MX31_PIN_CSPI2_MISO, OUTPUTCONFIG_GPIO,
+				  INPUTCONFIG_ALT1);
+		break;
+	case 2:
+		mxc_request_iomux(MX31_PIN_CSPI2_SS2, OUTPUTCONFIG_GPIO,
+				  INPUTCONFIG_ALT1);
+		mxc_request_iomux(MX31_PIN_CSPI2_SCLK, OUTPUTCONFIG_GPIO,
+				  INPUTCONFIG_ALT1);
+		break;
+	default:
+		break;
+	}
+}
+
+/*!
+ * This function configures the IOMux block for PMIC standard operations.
+ *
+ */
+void gpio_pmic_active(void)
+{
+	mxc_request_iomux(MX31_PIN_GPIO1_3, OUTPUTCONFIG_GPIO,
+			  INPUTCONFIG_GPIO);
+	mxc_set_gpio_direction(MX31_PIN_GPIO1_3, 1);
+//      mxc_set_gpio_edge_ctrl(MX31_PIN_GPIO1_3, GPIO_INT_RISE_EDGE);
+}
+
+EXPORT_SYMBOL(gpio_pmic_active);
+
+/*!
+ * This function activates DAM ports 4 & 5 to enable
+ * audio I/O. Thsi function is called from mx31lite_gpio_init
+ * function, which is board-specific.
+ */
+void gpio_activate_audio_ports(void)
+{
+	/* config Audio ports (4 & 5) */
+	mxc_request_iomux(MX31_PIN_SCK4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_SRXD4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_STXD4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_SFS4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_SCK5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_SRXD5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_STXD5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_SFS5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+}
+
+/*!
+ * Setup GPIO for SDHC to be active
+ *
+ * @param module SDHC module number
+ */
+void gpio_sdhc_active(int module)
+{
+	switch (module) {
+	case 0:
+		mxc_request_iomux(MX31_PIN_SD1_CLK, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_SD1_CMD, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_SD1_DATA0, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_SD1_DATA1, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_SD1_DATA2, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+		mxc_request_iomux(MX31_PIN_SD1_DATA3, OUTPUTCONFIG_FUNC,
+				  INPUTCONFIG_FUNC);
+
+		mxc_iomux_set_pad(MX31_PIN_SD1_CLK,
+				  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+		mxc_iomux_set_pad(MX31_PIN_SD1_CMD,
+				  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+		mxc_iomux_set_pad(MX31_PIN_SD1_DATA0,
+				  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+		mxc_iomux_set_pad(MX31_PIN_SD1_DATA1,
+				  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+		mxc_iomux_set_pad(MX31_PIN_SD1_DATA2,
+				  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+		mxc_iomux_set_pad(MX31_PIN_SD1_DATA3,
+				  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+		break;
+	case 1:
+		mxc_request_iomux(MX31_PIN_PC_CD2_B, OUTPUTCONFIG_ALT1,
+				  INPUTCONFIG_ALT1);
+		mxc_request_iomux(MX31_PIN_PC_CD1_B, OUTPUTCONFIG_ALT1,
+				  INPUTCONFIG_ALT1);
+		mxc_request_iomux(MX31_PIN_PC_WAIT_B, OUTPUTCONFIG_ALT1,
+				  INPUTCONFIG_ALT1);
+		mxc_request_iomux(MX31_PIN_PC_READY, OUTPUTCONFIG_ALT1,
+				  INPUTCONFIG_ALT1);
+		mxc_request_iomux(MX31_PIN_PC_VS1, OUTPUTCONFIG_ALT1,
+				  INPUTCONFIG_ALT1);
+		mxc_request_iomux(MX31_PIN_PC_PWRON, OUTPUTCONFIG_ALT1,
+				  INPUTCONFIG_ALT1);
+		break;
+	default:
+		break;
+	}
+}
+
+EXPORT_SYMBOL(gpio_sdhc_active);
+
+/*!
+ * Setup GPIO for SDHC1 to be inactive
+ *
+ * @param module SDHC module number
+ */
+void gpio_sdhc_inactive(int module)
+{
+	switch (module) {
+	case 0:
+		mxc_request_iomux(MX31_PIN_SD1_CLK, OUTPUTCONFIG_GPIO,
+				  INPUTCONFIG_NONE);
+		mxc_request_iomux(MX31_PIN_SD1_CMD, OUTPUTCONFIG_GPIO,
+				  INPUTCONFIG_NONE);
+		mxc_request_iomux(MX31_PIN_SD1_DATA0, OUTPUTCONFIG_GPIO,
+				  INPUTCONFIG_NONE);
+		mxc_request_iomux(MX31_PIN_SD1_DATA1, OUTPUTCONFIG_GPIO,
+				  INPUTCONFIG_NONE);
+		mxc_request_iomux(MX31_PIN_SD1_DATA2, OUTPUTCONFIG_GPIO,
+				  INPUTCONFIG_NONE);
+		mxc_request_iomux(MX31_PIN_SD1_DATA3, OUTPUTCONFIG_GPIO,
+				  INPUTCONFIG_NONE);
+
+		mxc_iomux_set_pad(MX31_PIN_SD1_CLK,
+				  (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
+		mxc_iomux_set_pad(MX31_PIN_SD1_CMD,
+				  (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
+		mxc_iomux_set_pad(MX31_PIN_SD1_DATA0,
+				  (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
+		mxc_iomux_set_pad(MX31_PIN_SD1_DATA1,
+				  (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
+		mxc_iomux_set_pad(MX31_PIN_SD1_DATA2,
+				  (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
+		mxc_iomux_set_pad(MX31_PIN_SD1_DATA3,
+				  (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
+		break;
+	case 1:
+		/* TODO:what are the pins for SDHC2? */
+		mxc_request_iomux(MX31_PIN_PC_CD2_B, OUTPUTCONFIG_GPIO,
+				  INPUTCONFIG_NONE);
+		mxc_request_iomux(MX31_PIN_PC_CD1_B, OUTPUTCONFIG_GPIO,
+				  INPUTCONFIG_NONE);
+		mxc_request_iomux(MX31_PIN_PC_WAIT_B, OUTPUTCONFIG_GPIO,
+				  INPUTCONFIG_NONE);
+		mxc_request_iomux(MX31_PIN_PC_READY, OUTPUTCONFIG_GPIO,
+				  INPUTCONFIG_NONE);
+		mxc_request_iomux(MX31_PIN_PC_VS1, OUTPUTCONFIG_GPIO,
+				  INPUTCONFIG_NONE);
+		mxc_request_iomux(MX31_PIN_PC_PWRON, OUTPUTCONFIG_GPIO,
+				  INPUTCONFIG_NONE);
+		break;
+	default:
+		break;
+	}
+}
+
+EXPORT_SYMBOL(gpio_sdhc_inactive);
+
+/*
+ * Probe for the card. If present the GPIO data would be set.
+ */
+int sdhc_get_card_det_status(struct device *dev)
+{
+	if (to_platform_device(dev)->id == 0) {
+		return mxc_get_gpio_datain(MX31_PIN_GPIO1_1);
+	} else {
+		return mxc_get_gpio_datain(MX31_PIN_GPIO1_2);
+	}
+}
+
+EXPORT_SYMBOL(sdhc_get_card_det_status);
+
+/*
+ * Return the card detect pin.
+ */
+int sdhc_init_card_det(int id)
+{
+	if (id == 0) {
+		iomux_config_mux(MX31_PIN_GPIO1_1, OUTPUTCONFIG_GPIO,
+				 INPUTCONFIG_GPIO);
+		return IOMUX_TO_IRQ(MX31_PIN_GPIO1_1);
+	} else {
+		iomux_config_mux(MX31_PIN_GPIO1_2, OUTPUTCONFIG_GPIO,
+				 INPUTCONFIG_GPIO);
+		return IOMUX_TO_IRQ(MX31_PIN_GPIO1_2);
+	}
+}
+
+EXPORT_SYMBOL(sdhc_init_card_det);
+
+/*!
+ * Setup GPIO for LCD to be active
+ *
+ */
+void gpio_lcd_active(void)
+{
+	mxc_request_iomux(MX31_PIN_LD0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD2, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD7, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD8, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD9, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD10, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD11, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD12, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD13, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD14, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD15, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD16, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// LD16
+	mxc_request_iomux(MX31_PIN_LD17, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// LD17
+	mxc_request_iomux(MX31_PIN_VSYNC3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// VSYNC
+	mxc_request_iomux(MX31_PIN_HSYNC, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// HSYNC
+	mxc_request_iomux(MX31_PIN_FPSHIFT, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// CLK
+	mxc_request_iomux(MX31_PIN_DRDY0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// DRDY
+	mxc_request_iomux(MX31_PIN_D3_REV, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// REV
+	mxc_request_iomux(MX31_PIN_CONTRAST, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// CONTR
+	mxc_request_iomux(MX31_PIN_D3_SPL, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// SPL
+	mxc_request_iomux(MX31_PIN_D3_CLS, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// CLS
+
+}
+
+/*!
+ * Setup GPIO for LCD to be inactive
+ *
+ */
+void gpio_lcd_inactive(void)
+{
+}
+
+/*!
+ * Setup pins for SLCD to be active
+ *
+ */
+void slcd_gpio_config(void)
+{
+	mxc_request_iomux(MX31_PIN_LD0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD2, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD7, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD8, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD9, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD10, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD11, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD12, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD13, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD14, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD15, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD16, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_LD17, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+
+	mxc_request_iomux(MX31_PIN_READ, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	/* read */
+	mxc_request_iomux(MX31_PIN_WRITE, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	/* write */
+	mxc_request_iomux(MX31_PIN_PAR_RS, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	/* RS */
+	mxc_request_iomux(MX31_PIN_LCS0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	/* chip select */
+
+}
+
+/*!
+ * Switch to the specified sensor - MX31 SOM has none
+ *
+ */
+void gpio_sensor_select(int sensor)
+{
+}
+
+/*!
+ * Setup GPIO for sensor to be active
+ *
+ */
+void gpio_sensor_active(void)
+{
+
+}
+
+EXPORT_SYMBOL(gpio_sensor_active);
+
+/*!
+ * Setup GPIO for sensor to be inactive
+ *
+ */
+void gpio_sensor_inactive(void)
+{
+}
+
+EXPORT_SYMBOL(gpio_sensor_inactive);
+
+void gpio_sensor_reset(bool flag)
+{
+}
+
+EXPORT_SYMBOL(gpio_sensor_reset);
+
+/*!
+ * Setup GPIO for ATA interface
+ *
+ */
+void gpio_ata_active(void)
+{
+        /*
+         * Configure the GPR for ATA group B signals
+         */
+
+	mxc_iomux_set_gpr(MUX_PGP_ATA_5 | MUX_PGP_ATA_9, true);
+
+        /*
+         * Configure the IOMUX for ATA group B signals
+         */
+
+        mxc_request_iomux(MX31_PIN_ATA_CS0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_D0
+        mxc_request_iomux(MX31_PIN_ATA_CS1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_D1
+        mxc_request_iomux(MX31_PIN_ATA_DIOR, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_D2
+        mxc_request_iomux(MX31_PIN_ATA_DIOW, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_D3
+        mxc_request_iomux(MX31_PIN_CSI_D4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_D4
+        mxc_request_iomux(MX31_PIN_CSI_D5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_D5
+        mxc_request_iomux(MX31_PIN_CSI_D6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_D6
+        mxc_request_iomux(MX31_PIN_CSI_D7, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_D7
+        mxc_request_iomux(MX31_PIN_CSI_D8, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_D8
+        mxc_request_iomux(MX31_PIN_CSI_D9, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_D9
+        mxc_request_iomux(MX31_PIN_CSI_D10, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_D10
+        mxc_request_iomux(MX31_PIN_CSI_D11, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_D11
+        mxc_request_iomux(MX31_PIN_CSI_D12, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_D12
+        mxc_request_iomux(MX31_PIN_CSI_D13, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_D13
+        mxc_request_iomux(MX31_PIN_CSI_D14, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_D14
+        mxc_request_iomux(MX31_PIN_CSI_D15, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_D15
+
+        mxc_request_iomux(MX31_PIN_ATA_RESET_B, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_D4
+        mxc_request_iomux(MX31_PIN_ATA_DMACK, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_D5
+        mxc_request_iomux(MX31_PIN_ATA_RESET_B, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_DMARQ_B
+        mxc_request_iomux(MX31_PIN_ATA_DMACK, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);	// ATA_INTRQ_B
+
+	/* These ATA pins are common to Group A and Group B */
+        mxc_request_iomux(MX31_PIN_ATA_CS0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+        mxc_request_iomux(MX31_PIN_ATA_CS1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+        mxc_request_iomux(MX31_PIN_ATA_DIOR, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+        mxc_request_iomux(MX31_PIN_ATA_DIOW, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+        mxc_request_iomux(MX31_PIN_ATA_DMACK, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+        mxc_request_iomux(MX31_PIN_ATA_RESET_B, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+        mxc_request_iomux(MX31_PIN_PWMO, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+
+        /* Need fast slew rate for UDMA mode */
+        mxc_iomux_set_pad(MX31_PIN_ATA_CS0, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE);	// data 0
+        mxc_iomux_set_pad(MX31_PIN_ATA_CS1, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE);	// data 1
+        mxc_iomux_set_pad(MX31_PIN_ATA_DIOR, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE);	// data 2
+        mxc_iomux_set_pad(MX31_PIN_ATA_DIOW, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE);	// data 3
+        mxc_iomux_set_pad(MX31_PIN_ATA_RESET_B, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE);	// reset
+        mxc_iomux_set_pad(MX31_PIN_ATA_DMACK, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE);	// dma ack
+        mxc_iomux_set_pad(MX31_PIN_CSI_D4, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE);	// data 4
+        mxc_iomux_set_pad(MX31_PIN_CSI_D5, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE);	// data 5
+        mxc_iomux_set_pad(MX31_PIN_CSI_D6, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE);	// data 6
+        mxc_iomux_set_pad(MX31_PIN_CSI_D7, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE);	// data 7
+        mxc_iomux_set_pad(MX31_PIN_CSI_D8, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE);	// data 8
+        mxc_iomux_set_pad(MX31_PIN_CSI_D9, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE);	// data 9
+        mxc_iomux_set_pad(MX31_PIN_CSI_D10, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE);	// data 10
+        mxc_iomux_set_pad(MX31_PIN_CSI_D11, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE);	// data 11
+        mxc_iomux_set_pad(MX31_PIN_CSI_D12, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE);	// data 12
+        mxc_iomux_set_pad(MX31_PIN_CSI_D13, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE);	// data 13
+        mxc_iomux_set_pad(MX31_PIN_CSI_D14, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE);	// data 14
+        mxc_iomux_set_pad(MX31_PIN_CSI_D15, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE);	// data 15
+
+        /*
+         * Turn off default pullups on high asserted control signals.
+         * These are pulled down externally, so it will just waste
+         * power and create voltage divider action to pull them up
+         * on chip.
+         */
+        mxc_iomux_set_pad(MX31_PIN_KEY_COL4, PAD_CTL_PKE_NONE);        // ATA_DMARQ
+        mxc_iomux_set_pad(MX31_PIN_KEY_ROW6, PAD_CTL_PKE_NONE);        // ATA_INTRQ
+}
+
+EXPORT_SYMBOL(gpio_ata_active);
+
+/*!
+ * Restore ATA interface pins to reset values
+ *
+ */
+void gpio_ata_inactive(void)
+{
+  /* printk(KERN_DEBUG "gpio_ata_inactive: Disable clocks\n"); */
+  /* mxc_clks_disable(ATA_CLK); */
+
+        /*
+         * Turn off ATA group B signals
+         */
+        mxc_request_iomux(MX31_PIN_ATA_CS0, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_D0
+        mxc_request_iomux(MX31_PIN_ATA_CS1, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_D1
+        mxc_request_iomux(MX31_PIN_ATA_DIOR, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_D2
+        mxc_request_iomux(MX31_PIN_ATA_DIOW, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_D3
+        mxc_request_iomux(MX31_PIN_CSI_D4, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_D4
+        mxc_request_iomux(MX31_PIN_CSI_D5, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_D5
+        mxc_request_iomux(MX31_PIN_CSI_D6, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_D6
+        mxc_request_iomux(MX31_PIN_CSI_D7, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_D7
+        mxc_request_iomux(MX31_PIN_CSI_D8, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_D8
+        mxc_request_iomux(MX31_PIN_CSI_D9, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_D9
+        mxc_request_iomux(MX31_PIN_CSI_D10, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_D10
+        mxc_request_iomux(MX31_PIN_CSI_D11, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_D11
+        mxc_request_iomux(MX31_PIN_CSI_D12, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_D12
+        mxc_request_iomux(MX31_PIN_CSI_D13, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_D13
+        mxc_request_iomux(MX31_PIN_CSI_D14, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_D14
+        mxc_request_iomux(MX31_PIN_CSI_D15, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_D15
+
+        mxc_request_iomux(MX31_PIN_ATA_RESET_B, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_D4
+        mxc_request_iomux(MX31_PIN_ATA_DMACK, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_D5
+        mxc_request_iomux(MX31_PIN_ATA_RESET_B, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_DMARQ_B
+        mxc_request_iomux(MX31_PIN_ATA_DMACK, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);	// ATA_INTRQ_B
+
+	/* These ATA pins are common to Group A and Group B */
+        mxc_request_iomux(MX31_PIN_ATA_CS0, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+        mxc_request_iomux(MX31_PIN_ATA_CS1, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+        mxc_request_iomux(MX31_PIN_ATA_DIOR, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+        mxc_request_iomux(MX31_PIN_ATA_DIOW, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+        mxc_request_iomux(MX31_PIN_ATA_DMACK, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+        mxc_request_iomux(MX31_PIN_ATA_RESET_B, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+        mxc_request_iomux(MX31_PIN_PWMO, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+
+        /* Need fast slew rate for UDMA mode */
+        mxc_iomux_set_pad(MX31_PIN_ATA_CS0, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE);	// data 0
+        mxc_iomux_set_pad(MX31_PIN_ATA_CS1, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE);	// data 1
+        mxc_iomux_set_pad(MX31_PIN_ATA_DIOR, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE);	// data 2
+        mxc_iomux_set_pad(MX31_PIN_ATA_DIOW, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE);	// data 3
+        mxc_iomux_set_pad(MX31_PIN_ATA_RESET_B, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE);	// reset
+        mxc_iomux_set_pad(MX31_PIN_ATA_DMACK, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE);	// dma ack
+        mxc_iomux_set_pad(MX31_PIN_CSI_D4, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE);	// data 4
+        mxc_iomux_set_pad(MX31_PIN_CSI_D5, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE);	// data 5
+        mxc_iomux_set_pad(MX31_PIN_CSI_D6, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE);	// data 6
+        mxc_iomux_set_pad(MX31_PIN_CSI_D7, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE);	// data 7
+        mxc_iomux_set_pad(MX31_PIN_CSI_D8, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE);	// data 8
+        mxc_iomux_set_pad(MX31_PIN_CSI_D9, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE);	// data 9
+        mxc_iomux_set_pad(MX31_PIN_CSI_D10, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE);	// data 10
+        mxc_iomux_set_pad(MX31_PIN_CSI_D11, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE);	// data 11
+        mxc_iomux_set_pad(MX31_PIN_CSI_D12, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE);	// data 12
+        mxc_iomux_set_pad(MX31_PIN_CSI_D13, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE);	// data 13
+        mxc_iomux_set_pad(MX31_PIN_CSI_D14, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE);	// data 14
+        mxc_iomux_set_pad(MX31_PIN_CSI_D15, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE);	// data 15
+}
+
+EXPORT_SYMBOL(gpio_ata_inactive);
+
+/*!
+ * Setup EDIO/IOMUX for external UART.
+ *
+ * @param port UART port
+ * @param irq Interrupt line to allocate
+ * @param handler Function to be called when the IRQ occurs
+ * @param irq_flags Interrupt type flags
+ * @param devname An ascii name for the claiming device
+ * @param dev_id A cookie passed back to the handler function
+ * @return  Returns 0 if the interrupt was successfully requested,
+ *          otherwise returns an error code.
+ */
+int extuart_intr_setup(unsigned int port, unsigned int irq,
+		       irqreturn_t(*handler) (int, void *, struct pt_regs *),
+		       unsigned long irq_flags, const char *devname,
+		       void *dev_id)
+{
+	return 0;
+}
+
+/*!
+ * Get the EDIO interrupt, clear if set.
+ *
+ * @param port UART port
+ */
+void extuart_intr_clear(unsigned int port)
+{
+}
+
+/*!
+ * Do IOMUX configs required to put the
+ * pin back in low power mode.
+ *
+ * @param port UART port
+ * @param irq Interrupt line to free
+ * @param dev_id Device identity to free
+ * @return  Returns 0 if the interrupt was successfully freed,
+ *          otherwise returns an error code.
+ */
+int extuart_intr_cleanup(unsigned int port, unsigned int irq, void *dev_id)
+{
+	return 0;
+}
+
+/* *INDENT-OFF* */
+/*
+ * USB Host 1
+ * pins conflict with SPI1, ATA, UART3
+ */
+int gpio_usbh1_active(void)
+{
+	if (mxc_request_iomux(MX31_PIN_CSPI1_MOSI,	/* USBH1_RXDM */
+			      OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1) ||
+	    mxc_request_iomux(MX31_PIN_CSPI1_MISO,	/* USBH1_RXDP */
+			      OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1) ||
+	    mxc_request_iomux(MX31_PIN_CSPI1_SS0,	/* USBH1_TXDM */
+			      OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1) ||
+	    mxc_request_iomux(MX31_PIN_CSPI1_SS1,	/* USBH1_TXDP */
+			      OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1) ||
+	    mxc_request_iomux(MX31_PIN_CSPI1_SS2,	/* USBH1_RCV  */
+			      OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1) ||
+	    mxc_request_iomux(MX31_PIN_CSPI1_SCLK,	/* USBH1_OEB (_TXOE) */
+			      OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1) ||
+	    mxc_request_iomux(MX31_PIN_CSPI1_SPI_RDY,	/* USBH1_FS   */
+			      OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1)) {
+		return -EINVAL;
+	}
+
+	mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI,		/* USBH1_RXDM */
+			  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+
+	mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO,		/* USBH1_RXDP */
+			  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+
+	mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0,		/* USBH1_TXDM */
+			  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+
+	mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1,		/* USBH1_TXDP */
+			  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+
+	mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2,		/* USBH1_RCV  */
+			  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+
+	mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK,		/* USBH1_OEB (_TXOE) */
+			  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+
+	mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY,	/* USBH1_FS   */
+			  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+
+	/* USB_H1_SUSPEND collides with WRLAN INT# line */
+//	mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
+	return 0;
+}
+
+EXPORT_SYMBOL(gpio_usbh1_active);
+
+void gpio_usbh1_inactive(void)
+{
+}
+
+EXPORT_SYMBOL(gpio_usbh1_inactive);
+
+/*
+ * USB Host 2
+ * pins conflict with UART5, PCMCIA
+ */
+int gpio_usbh2_active(void)
+{
+	if (mxc_request_iomux(MX31_PIN_USBH2_CLK,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBH2_DIR,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBH2_NXT,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBH2_STP,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBH2_DATA0,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBH2_DATA1,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_STXD3,		/* USBH2_DATA2 */
+			      OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE) ||
+	    mxc_request_iomux(MX31_PIN_SRXD3,		/* USBH2_DATA3 */
+			      OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE) ||
+	    mxc_request_iomux(MX31_PIN_SCK3,		/* USBH2_DATA4 */
+			      OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE) ||
+	    mxc_request_iomux(MX31_PIN_SFS3,		/* USBH2_DATA5 */
+			      OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE) ||
+	    mxc_request_iomux(MX31_PIN_STXD6,		/* USBH2_DATA6 */
+			      OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE) ||
+	    mxc_request_iomux(MX31_PIN_SRXD6,		/* USBH2_DATA7 */
+			      OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE))
+		return -EINVAL;
+
+#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+	mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
+	mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
+	mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
+	mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
+	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG);
+	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG);
+	mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG);	/* USBH2_DATA2 */
+	mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG);	/* USBH2_DATA3 */
+	mxc_iomux_set_pad(MX31_PIN_SCK3,  H2_PAD_CFG);	/* USBH2_DATA4 */
+	mxc_iomux_set_pad(MX31_PIN_SFS3,  H2_PAD_CFG);	/* USBH2_DATA5 */
+	mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG);	/* USBH2_DATA6 */
+	mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG);	/* USBH2_DATA7 */
+#undef H2_PAD_CFG
+
+	mxc_iomux_set_gpr(MUX_PGP_UH2, true);
+	return 0;
+}
+
+EXPORT_SYMBOL(gpio_usbh2_active);
+
+void gpio_usbh2_inactive(void)
+{
+	iomux_config_gpr(MUX_PGP_UH2, false);
+
+	iomux_config_pad(MX31_PIN_USBH2_CLK,
+			 (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST));
+	iomux_config_pad(MX31_PIN_USBH2_DIR,
+			 (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST));
+	iomux_config_pad(MX31_PIN_USBH2_NXT,
+			 (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST));
+	iomux_config_pad(MX31_PIN_USBH2_STP,
+			 (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST));
+	iomux_config_pad(MX31_PIN_USBH2_DATA0,
+			 (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST));
+	iomux_config_pad(MX31_PIN_USBH2_DATA1,
+			 (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST));
+	iomux_config_pad(MX31_PIN_SRXD6,		/* USBH2_DATA2 */
+			 (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST));
+	iomux_config_pad(MX31_PIN_STXD6,		/* USBH2_DATA3 */
+			 (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST));
+	iomux_config_pad(MX31_PIN_SFS3,			/* USBH2_DATA4 */
+			 (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST));
+	iomux_config_pad(MX31_PIN_SCK3,			/* USBH2_DATA5 */
+			 (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST));
+	iomux_config_pad(MX31_PIN_SRXD3,		/* USBH2_DATA6 */
+			 (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST));
+	iomux_config_pad(MX31_PIN_STXD3,		/* USBH2_DATA7 */
+			 (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST));
+
+	mxc_free_iomux(MX31_PIN_USBH2_CLK,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBH2_DIR,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBH2_NXT,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBH2_STP,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBH2_DATA0,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBH2_DATA1,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+
+	mxc_free_iomux(MX31_PIN_PC_VS2,			/* USBH2_DATA2 */
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_PC_BVD1,		/* USBH2_DATA3 */
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_PC_BVD2,		/* USBH2_DATA4 */
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_PC_RST,			/* USBH2_DATA5 */
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_IOIS16,			/* USBH2_DATA6 */
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_PC_RW_B,		/* USBH2_DATA7 */
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+
+	mxc_free_iomux(MX31_PIN_NFWE_B,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_NFRE_B,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_NFALE,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_NFCLE,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_NFWP_B,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_NFCE_B,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+}
+
+EXPORT_SYMBOL(gpio_usbh2_inactive);
+
+/*
+ * USB OTG HS port
+ */
+int gpio_usbotg_hs_active(void)
+{
+	if (mxc_request_iomux(MX31_PIN_USBOTG_DATA0,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_DATA1,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_DATA2,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_DATA3,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_DATA4,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_DATA5,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_DATA6,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_DATA7,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_CLK,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_DIR,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_NXT,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_STP,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC)) {
+		return -EINVAL;
+	}
+
+
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0,
+			  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1,
+			  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2,
+			  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3,
+			  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4,
+			  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5,
+			  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6,
+			  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7,
+			  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK,
+			  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR,
+			  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT,
+			  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_STP,
+			  (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST));
+	return 0;
+}
+
+EXPORT_SYMBOL(gpio_usbotg_hs_active);
+
+void gpio_usbotg_hs_inactive(void)
+{
+	mxc_free_iomux(MX31_PIN_USBOTG_DATA0,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_DATA1,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_DATA2,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_DATA3,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_DATA4,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_DATA5,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_DATA6,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_DATA7,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_CLK,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_DIR,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_NXT,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_STP,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0,
+			  (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1,
+			  (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2,
+			  (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3,
+			  (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4,
+			  (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5,
+			  (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6,
+			  (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7,
+			  (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK,
+			  (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR,
+			  (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT,
+			  (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
+	mxc_iomux_set_pad(MX31_PIN_USBOTG_STP,
+			  (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
+}
+
+EXPORT_SYMBOL(gpio_usbotg_hs_inactive);
+
+/*
+ * USB OTG FS port
+ */
+int gpio_usbotg_fs_active(void)
+{
+	if (mxc_request_iomux(MX31_PIN_USBOTG_DATA0,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_DATA1,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_DATA2,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_DATA3,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_DATA4,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_DATA5,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_DATA6,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_DATA7,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_CLK,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_DIR,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_NXT,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USBOTG_STP,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) ||
+	    mxc_request_iomux(MX31_PIN_USB_PWR,
+			      OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC)) {
+		return -EINVAL;
+	}
+	return 0;
+
+}
+
+EXPORT_SYMBOL(gpio_usbotg_fs_active);
+
+void gpio_usbotg_fs_inactive(void)
+{
+	mxc_free_iomux(MX31_PIN_USBOTG_DATA0,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_DATA1,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_DATA2,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_DATA3,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_DATA4,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_DATA5,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_DATA6,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_DATA7,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_CLK,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_DIR,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_NXT,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USBOTG_STP,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_USB_PWR,
+		       OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+}
+
+EXPORT_SYMBOL(gpio_usbotg_fs_inactive);
+/* *INDENT-ON* */
+
+/*!
+ * Setup GPIO for PCMCIA interface
+ *
+ */
+void gpio_pcmcia_active(void)
+{
+	mxc_request_iomux(MX31_PIN_SDBA0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	mxc_request_iomux(MX31_PIN_SDBA1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+
+	iomux_config_mux(MX31_PIN_LBA, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	iomux_config_mux(MX31_PIN_RW, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	iomux_config_mux(MX31_PIN_EB0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	iomux_config_mux(MX31_PIN_EB1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	iomux_config_mux(MX31_PIN_OE, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+
+	iomux_config_mux(MX31_PIN_IOIS16, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	iomux_config_mux(MX31_PIN_PC_BVD1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	iomux_config_mux(MX31_PIN_PC_BVD2, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	iomux_config_mux(MX31_PIN_PC_CD1_B, OUTPUTCONFIG_FUNC,
+			 INPUTCONFIG_FUNC);
+	iomux_config_mux(MX31_PIN_PC_CD2_B, OUTPUTCONFIG_FUNC,
+			 INPUTCONFIG_FUNC);
+	iomux_config_mux(MX31_PIN_PC_POE, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	iomux_config_mux(MX31_PIN_PC_PWRON, OUTPUTCONFIG_FUNC,
+			 INPUTCONFIG_FUNC);
+	iomux_config_mux(MX31_PIN_PC_READY, OUTPUTCONFIG_FUNC,
+			 INPUTCONFIG_FUNC);
+	iomux_config_mux(MX31_PIN_PC_RST, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	iomux_config_mux(MX31_PIN_PC_RW_B, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	iomux_config_mux(MX31_PIN_PC_VS1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	iomux_config_mux(MX31_PIN_PC_VS2, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
+	iomux_config_mux(MX31_PIN_PC_WAIT_B, OUTPUTCONFIG_FUNC,
+			 INPUTCONFIG_FUNC);
+}
+
+EXPORT_SYMBOL(gpio_pcmcia_active);
+
+/*!
+ * Setup GPIO for pcmcia to be inactive
+ */
+void gpio_pcmcia_inactive(void)
+{
+	mxc_free_iomux(MX31_PIN_SDBA0, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_SDBA1, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+
+	mxc_free_iomux(MX31_PIN_LBA, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_RW, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_EB0, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_EB1, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_OE, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+
+	mxc_free_iomux(MX31_PIN_IOIS16, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_PC_BVD1, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_PC_BVD2, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_PC_CD1_B, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_PC_CD2_B, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_PC_POE, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_PC_PWRON, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_PC_READY, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_PC_RST, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_PC_RW_B, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_PC_VS1, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_PC_VS2, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+	mxc_free_iomux(MX31_PIN_PC_WAIT_B, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
+}
+
+EXPORT_SYMBOL(gpio_pcmcia_inactive);
diff --git a/arch/arm/mach-mx3/usb_lite.c b/arch/arm/mach-mx3/usb_lite.c
new file mode 100644
index 000000000000..1c36fd28c4dd
--- /dev/null
+++ b/arch/arm/mach-mx3/usb_lite.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2005-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+//#include <linux/usb_otg.h>
+#include <linux/delay.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+
+#include "board-mx31lite.h"
+
+static int __init mx3_usb_init(void)
+{
+
+}
+
+subsys_initcall(mx3_usb_init);