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authorEric Brower <ebrower@nvidia.com>2013-11-04 11:27:55 -0800
committerMatthew Pedro <mapedro@nvidia.com>2014-03-05 20:01:25 -0800
commit3f41b064189a7ee9d2d04b12ad3d15c416366f5d (patch)
tree66bb9de5f1f4fd5bb09cf27b283c6c82f59e8b1a
parentd283f029d9b971f93f6f4b0e62d3cacb2571a204 (diff)
ARM: tegra: pcie: Disable PCIe GEN2 capability
Disable PCIe Gen2 capability. This is not supported on Tegra 20/30 SOCs. Bug 1399592 Change-Id: I696a982b93d2e56a3b24379d38e51a5e93e4b7a1 Signed-off-by: Eric Brower <ebrower@nvidia.com> Reviewed-on: http://git-master/r/326195 Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/pcie.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 04d3a5db3f7e..dd6da2a7d965 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -825,7 +825,7 @@ static void tegra_pcie_enable_controller(void)
afi_writel(val, AFI_PCIE_CONFIG);
/* Disable Gen 2 capability of PCIE */
- val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS;
+ val = afi_readl(AFI_FUSE) | AFI_FUSE_PCIE_T0_GEN2_DIS;
afi_writel(val, AFI_FUSE);
/* Initialze internal PHY, enable up to 16 PCIE lanes */