staging: octeon-usb: cvmx-usbnx-defs.h: delete unused data types

Delete unused data types.

Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

1 files changed, 0 insertions, 863 deletions

diff --git a/drivers/staging/octeon-usb/cvmx-usbnx-defs.h b/drivers/staging/octeon-usb/cvmx-usbnx-defs.h
index 73ddee08edc1..4e446be0a134 100644
--- a/drivers/staging/octeon-usb/cvmx-usbnx-defs.h
+++ b/drivers/staging/octeon-usb/cvmx-usbnx-defs.h
@@ -77,43 +77,6 @@
 #define CVMX_USBNX_USBP_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180068000018ull) + ((block_id) & 1) * 0x10000000ull)
 
 /**
- * cvmx_usbn#_bist_status
- *
- * USBN_BIST_STATUS = USBN's Control and Status
- *
- * Contain general control bits and status information for the USBN.
- */
-union cvmx_usbnx_bist_status
-{
-	uint64_t u64;
-	struct cvmx_usbnx_bist_status_s
-	{
-	uint64_t reserved_7_63                : 57;
-	uint64_t u2nc_bis                     : 1;  /**< Bist status U2N CTL FIFO Memory. */
-	uint64_t u2nf_bis                     : 1;  /**< Bist status U2N FIFO Memory. */
-	uint64_t e2hc_bis                     : 1;  /**< Bist status E2H CTL FIFO Memory. */
-	uint64_t n2uf_bis                     : 1;  /**< Bist status N2U  FIFO Memory. */
-	uint64_t usbc_bis                     : 1;  /**< Bist status USBC FIFO Memory. */
-	uint64_t nif_bis                      : 1;  /**< Bist status for Inbound Memory. */
-	uint64_t nof_bis                      : 1;  /**< Bist status for Outbound Memory. */
-	} s;
-	struct cvmx_usbnx_bist_status_cn30xx
-	{
-	uint64_t reserved_3_63                : 61;
-	uint64_t usbc_bis                     : 1;  /**< Bist status USBC FIFO Memory. */
-	uint64_t nif_bis                      : 1;  /**< Bist status for Inbound Memory. */
-	uint64_t nof_bis                      : 1;  /**< Bist status for Outbound Memory. */
-	} cn30xx;
-	struct cvmx_usbnx_bist_status_cn30xx  cn31xx;
-	struct cvmx_usbnx_bist_status_s       cn50xx;
-	struct cvmx_usbnx_bist_status_s       cn52xx;
-	struct cvmx_usbnx_bist_status_s       cn52xxp1;
-	struct cvmx_usbnx_bist_status_s       cn56xx;
-	struct cvmx_usbnx_bist_status_s       cn56xxp1;
-};
-typedef union cvmx_usbnx_bist_status cvmx_usbnx_bist_status_t;
-
-/**
  * cvmx_usbn#_clk_ctl
  *
  * USBN_CLK_CTL = USBN's Clock Control
@@ -348,832 +311,6 @@ union cvmx_usbnx_clk_ctl
 typedef union cvmx_usbnx_clk_ctl cvmx_usbnx_clk_ctl_t;
 
 /**
- * cvmx_usbn#_ctl_status
- *
- * USBN_CTL_STATUS = USBN's Control And Status Register
- *
- * Contains general control and status information for the USBN block.
- */
-union cvmx_usbnx_ctl_status
-{
-	uint64_t u64;
-	struct cvmx_usbnx_ctl_status_s
-	{
-	uint64_t reserved_6_63                : 58;
-	uint64_t dma_0pag                     : 1;  /**< When '1' sets the DMA engine will set the zero-Page
-                                                         bit in the L2C store operation to the IOB. */
-	uint64_t dma_stt                      : 1;  /**< When '1' sets the DMA engine to use STT operations. */
-	uint64_t dma_test                     : 1;  /**< When '1' sets the DMA engine into Test-Mode.
-                                                         For normal operation this bit should be '0'. */
-	uint64_t inv_a2                       : 1;  /**< When '1' causes the address[2] driven on the AHB
-                                                         for USB-CORE FIFO access to be inverted. Also data
-                                                         writen to and read from the AHB will have it byte
-                                                         order swapped. If the orginal order was A-B-C-D the
-                                                         new byte order will be D-C-B-A. */
-	uint64_t l2c_emod                     : 2;  /**< Endian format for data from/to the L2C.
-                                                         IN:   A-B-C-D-E-F-G-H
-                                                         OUT0: A-B-C-D-E-F-G-H
-                                                         OUT1: H-G-F-E-D-C-B-A
-                                                         OUT2: D-C-B-A-H-G-F-E
-                                                         OUT3: E-F-G-H-A-B-C-D */
-	} s;
-	struct cvmx_usbnx_ctl_status_s        cn30xx;
-	struct cvmx_usbnx_ctl_status_s        cn31xx;
-	struct cvmx_usbnx_ctl_status_s        cn50xx;
-	struct cvmx_usbnx_ctl_status_s        cn52xx;
-	struct cvmx_usbnx_ctl_status_s        cn52xxp1;
-	struct cvmx_usbnx_ctl_status_s        cn56xx;
-	struct cvmx_usbnx_ctl_status_s        cn56xxp1;
-};
-typedef union cvmx_usbnx_ctl_status cvmx_usbnx_ctl_status_t;
-
-/**
- * cvmx_usbn#_dma0_inb_chn0
- *
- * USBN_DMA0_INB_CHN0 = USBN's Inbound DMA for USB0 Channel0
- *
- * Contains the starting address for use when USB0 writes to L2C via Channel0.
- * Writing of this register sets the base address.
- */
-union cvmx_usbnx_dma0_inb_chn0
-{
-	uint64_t u64;
-	struct cvmx_usbnx_dma0_inb_chn0_s
-	{
-	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
-	} s;
-	struct cvmx_usbnx_dma0_inb_chn0_s     cn30xx;
-	struct cvmx_usbnx_dma0_inb_chn0_s     cn31xx;
-	struct cvmx_usbnx_dma0_inb_chn0_s     cn50xx;
-	struct cvmx_usbnx_dma0_inb_chn0_s     cn52xx;
-	struct cvmx_usbnx_dma0_inb_chn0_s     cn52xxp1;
-	struct cvmx_usbnx_dma0_inb_chn0_s     cn56xx;
-	struct cvmx_usbnx_dma0_inb_chn0_s     cn56xxp1;
-};
-typedef union cvmx_usbnx_dma0_inb_chn0 cvmx_usbnx_dma0_inb_chn0_t;
-
-/**
- * cvmx_usbn#_dma0_inb_chn1
- *
- * USBN_DMA0_INB_CHN1 = USBN's Inbound DMA for USB0 Channel1
- *
- * Contains the starting address for use when USB0 writes to L2C via Channel1.
- * Writing of this register sets the base address.
- */
-union cvmx_usbnx_dma0_inb_chn1
-{
-	uint64_t u64;
-	struct cvmx_usbnx_dma0_inb_chn1_s
-	{
-	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
-	} s;
-	struct cvmx_usbnx_dma0_inb_chn1_s     cn30xx;
-	struct cvmx_usbnx_dma0_inb_chn1_s     cn31xx;
-	struct cvmx_usbnx_dma0_inb_chn1_s     cn50xx;
-	struct cvmx_usbnx_dma0_inb_chn1_s     cn52xx;
-	struct cvmx_usbnx_dma0_inb_chn1_s     cn52xxp1;
-	struct cvmx_usbnx_dma0_inb_chn1_s     cn56xx;
-	struct cvmx_usbnx_dma0_inb_chn1_s     cn56xxp1;
-};
-typedef union cvmx_usbnx_dma0_inb_chn1 cvmx_usbnx_dma0_inb_chn1_t;
-
-/**
- * cvmx_usbn#_dma0_inb_chn2
- *
- * USBN_DMA0_INB_CHN2 = USBN's Inbound DMA for USB0 Channel2
- *
- * Contains the starting address for use when USB0 writes to L2C via Channel2.
- * Writing of this register sets the base address.
- */
-union cvmx_usbnx_dma0_inb_chn2
-{
-	uint64_t u64;
-	struct cvmx_usbnx_dma0_inb_chn2_s
-	{
-	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
-	} s;
-	struct cvmx_usbnx_dma0_inb_chn2_s     cn30xx;
-	struct cvmx_usbnx_dma0_inb_chn2_s     cn31xx;
-	struct cvmx_usbnx_dma0_inb_chn2_s     cn50xx;
-	struct cvmx_usbnx_dma0_inb_chn2_s     cn52xx;
-	struct cvmx_usbnx_dma0_inb_chn2_s     cn52xxp1;
-	struct cvmx_usbnx_dma0_inb_chn2_s     cn56xx;
-	struct cvmx_usbnx_dma0_inb_chn2_s     cn56xxp1;
-};
-typedef union cvmx_usbnx_dma0_inb_chn2 cvmx_usbnx_dma0_inb_chn2_t;
-
-/**
- * cvmx_usbn#_dma0_inb_chn3
- *
- * USBN_DMA0_INB_CHN3 = USBN's Inbound DMA for USB0 Channel3
- *
- * Contains the starting address for use when USB0 writes to L2C via Channel3.
- * Writing of this register sets the base address.
- */
-union cvmx_usbnx_dma0_inb_chn3
-{
-	uint64_t u64;
-	struct cvmx_usbnx_dma0_inb_chn3_s
-	{
-	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
-	} s;
-	struct cvmx_usbnx_dma0_inb_chn3_s     cn30xx;
-	struct cvmx_usbnx_dma0_inb_chn3_s     cn31xx;
-	struct cvmx_usbnx_dma0_inb_chn3_s     cn50xx;
-	struct cvmx_usbnx_dma0_inb_chn3_s     cn52xx;
-	struct cvmx_usbnx_dma0_inb_chn3_s     cn52xxp1;
-	struct cvmx_usbnx_dma0_inb_chn3_s     cn56xx;
-	struct cvmx_usbnx_dma0_inb_chn3_s     cn56xxp1;
-};
-typedef union cvmx_usbnx_dma0_inb_chn3 cvmx_usbnx_dma0_inb_chn3_t;
-
-/**
- * cvmx_usbn#_dma0_inb_chn4
- *
- * USBN_DMA0_INB_CHN4 = USBN's Inbound DMA for USB0 Channel4
- *
- * Contains the starting address for use when USB0 writes to L2C via Channel4.
- * Writing of this register sets the base address.
- */
-union cvmx_usbnx_dma0_inb_chn4
-{
-	uint64_t u64;
-	struct cvmx_usbnx_dma0_inb_chn4_s
-	{
-	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
-	} s;
-	struct cvmx_usbnx_dma0_inb_chn4_s     cn30xx;
-	struct cvmx_usbnx_dma0_inb_chn4_s     cn31xx;
-	struct cvmx_usbnx_dma0_inb_chn4_s     cn50xx;
-	struct cvmx_usbnx_dma0_inb_chn4_s     cn52xx;
-	struct cvmx_usbnx_dma0_inb_chn4_s     cn52xxp1;
-	struct cvmx_usbnx_dma0_inb_chn4_s     cn56xx;
-	struct cvmx_usbnx_dma0_inb_chn4_s     cn56xxp1;
-};
-typedef union cvmx_usbnx_dma0_inb_chn4 cvmx_usbnx_dma0_inb_chn4_t;
-
-/**
- * cvmx_usbn#_dma0_inb_chn5
- *
- * USBN_DMA0_INB_CHN5 = USBN's Inbound DMA for USB0 Channel5
- *
- * Contains the starting address for use when USB0 writes to L2C via Channel5.
- * Writing of this register sets the base address.
- */
-union cvmx_usbnx_dma0_inb_chn5
-{
-	uint64_t u64;
-	struct cvmx_usbnx_dma0_inb_chn5_s
-	{
-	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
-	} s;
-	struct cvmx_usbnx_dma0_inb_chn5_s     cn30xx;
-	struct cvmx_usbnx_dma0_inb_chn5_s     cn31xx;
-	struct cvmx_usbnx_dma0_inb_chn5_s     cn50xx;
-	struct cvmx_usbnx_dma0_inb_chn5_s     cn52xx;
-	struct cvmx_usbnx_dma0_inb_chn5_s     cn52xxp1;
-	struct cvmx_usbnx_dma0_inb_chn5_s     cn56xx;
-	struct cvmx_usbnx_dma0_inb_chn5_s     cn56xxp1;
-};
-typedef union cvmx_usbnx_dma0_inb_chn5 cvmx_usbnx_dma0_inb_chn5_t;
-
-/**
- * cvmx_usbn#_dma0_inb_chn6
- *
- * USBN_DMA0_INB_CHN6 = USBN's Inbound DMA for USB0 Channel6
- *
- * Contains the starting address for use when USB0 writes to L2C via Channel6.
- * Writing of this register sets the base address.
- */
-union cvmx_usbnx_dma0_inb_chn6
-{
-	uint64_t u64;
-	struct cvmx_usbnx_dma0_inb_chn6_s
-	{
-	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
-	} s;
-	struct cvmx_usbnx_dma0_inb_chn6_s     cn30xx;
-	struct cvmx_usbnx_dma0_inb_chn6_s     cn31xx;
-	struct cvmx_usbnx_dma0_inb_chn6_s     cn50xx;
-	struct cvmx_usbnx_dma0_inb_chn6_s     cn52xx;
-	struct cvmx_usbnx_dma0_inb_chn6_s     cn52xxp1;
-	struct cvmx_usbnx_dma0_inb_chn6_s     cn56xx;
-	struct cvmx_usbnx_dma0_inb_chn6_s     cn56xxp1;
-};
-typedef union cvmx_usbnx_dma0_inb_chn6 cvmx_usbnx_dma0_inb_chn6_t;
-
-/**
- * cvmx_usbn#_dma0_inb_chn7
- *
- * USBN_DMA0_INB_CHN7 = USBN's Inbound DMA for USB0 Channel7
- *
- * Contains the starting address for use when USB0 writes to L2C via Channel7.
- * Writing of this register sets the base address.
- */
-union cvmx_usbnx_dma0_inb_chn7
-{
-	uint64_t u64;
-	struct cvmx_usbnx_dma0_inb_chn7_s
-	{
-	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 36; /**< Base address for DMA Write to L2C. */
-	} s;
-	struct cvmx_usbnx_dma0_inb_chn7_s     cn30xx;
-	struct cvmx_usbnx_dma0_inb_chn7_s     cn31xx;
-	struct cvmx_usbnx_dma0_inb_chn7_s     cn50xx;
-	struct cvmx_usbnx_dma0_inb_chn7_s     cn52xx;
-	struct cvmx_usbnx_dma0_inb_chn7_s     cn52xxp1;
-	struct cvmx_usbnx_dma0_inb_chn7_s     cn56xx;
-	struct cvmx_usbnx_dma0_inb_chn7_s     cn56xxp1;
-};
-typedef union cvmx_usbnx_dma0_inb_chn7 cvmx_usbnx_dma0_inb_chn7_t;
-
-/**
- * cvmx_usbn#_dma0_outb_chn0
- *
- * USBN_DMA0_OUTB_CHN0 = USBN's Outbound DMA for USB0 Channel0
- *
- * Contains the starting address for use when USB0 reads from L2C via Channel0.
- * Writing of this register sets the base address.
- */
-union cvmx_usbnx_dma0_outb_chn0
-{
-	uint64_t u64;
-	struct cvmx_usbnx_dma0_outb_chn0_s
-	{
-	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
-	} s;
-	struct cvmx_usbnx_dma0_outb_chn0_s    cn30xx;
-	struct cvmx_usbnx_dma0_outb_chn0_s    cn31xx;
-	struct cvmx_usbnx_dma0_outb_chn0_s    cn50xx;
-	struct cvmx_usbnx_dma0_outb_chn0_s    cn52xx;
-	struct cvmx_usbnx_dma0_outb_chn0_s    cn52xxp1;
-	struct cvmx_usbnx_dma0_outb_chn0_s    cn56xx;
-	struct cvmx_usbnx_dma0_outb_chn0_s    cn56xxp1;
-};
-typedef union cvmx_usbnx_dma0_outb_chn0 cvmx_usbnx_dma0_outb_chn0_t;
-
-/**
- * cvmx_usbn#_dma0_outb_chn1
- *
- * USBN_DMA0_OUTB_CHN1 = USBN's Outbound DMA for USB0 Channel1
- *
- * Contains the starting address for use when USB0 reads from L2C via Channel1.
- * Writing of this register sets the base address.
- */
-union cvmx_usbnx_dma0_outb_chn1
-{
-	uint64_t u64;
-	struct cvmx_usbnx_dma0_outb_chn1_s
-	{
-	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
-	} s;
-	struct cvmx_usbnx_dma0_outb_chn1_s    cn30xx;
-	struct cvmx_usbnx_dma0_outb_chn1_s    cn31xx;
-	struct cvmx_usbnx_dma0_outb_chn1_s    cn50xx;
-	struct cvmx_usbnx_dma0_outb_chn1_s    cn52xx;
-	struct cvmx_usbnx_dma0_outb_chn1_s    cn52xxp1;
-	struct cvmx_usbnx_dma0_outb_chn1_s    cn56xx;
-	struct cvmx_usbnx_dma0_outb_chn1_s    cn56xxp1;
-};
-typedef union cvmx_usbnx_dma0_outb_chn1 cvmx_usbnx_dma0_outb_chn1_t;
-
-/**
- * cvmx_usbn#_dma0_outb_chn2
- *
- * USBN_DMA0_OUTB_CHN2 = USBN's Outbound DMA for USB0 Channel2
- *
- * Contains the starting address for use when USB0 reads from L2C via Channel2.
- * Writing of this register sets the base address.
- */
-union cvmx_usbnx_dma0_outb_chn2
-{
-	uint64_t u64;
-	struct cvmx_usbnx_dma0_outb_chn2_s
-	{
-	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
-	} s;
-	struct cvmx_usbnx_dma0_outb_chn2_s    cn30xx;
-	struct cvmx_usbnx_dma0_outb_chn2_s    cn31xx;
-	struct cvmx_usbnx_dma0_outb_chn2_s    cn50xx;
-	struct cvmx_usbnx_dma0_outb_chn2_s    cn52xx;
-	struct cvmx_usbnx_dma0_outb_chn2_s    cn52xxp1;
-	struct cvmx_usbnx_dma0_outb_chn2_s    cn56xx;
-	struct cvmx_usbnx_dma0_outb_chn2_s    cn56xxp1;
-};
-typedef union cvmx_usbnx_dma0_outb_chn2 cvmx_usbnx_dma0_outb_chn2_t;
-
-/**
- * cvmx_usbn#_dma0_outb_chn3
- *
- * USBN_DMA0_OUTB_CHN3 = USBN's Outbound DMA for USB0 Channel3
- *
- * Contains the starting address for use when USB0 reads from L2C via Channel3.
- * Writing of this register sets the base address.
- */
-union cvmx_usbnx_dma0_outb_chn3
-{
-	uint64_t u64;
-	struct cvmx_usbnx_dma0_outb_chn3_s
-	{
-	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
-	} s;
-	struct cvmx_usbnx_dma0_outb_chn3_s    cn30xx;
-	struct cvmx_usbnx_dma0_outb_chn3_s    cn31xx;
-	struct cvmx_usbnx_dma0_outb_chn3_s    cn50xx;
-	struct cvmx_usbnx_dma0_outb_chn3_s    cn52xx;
-	struct cvmx_usbnx_dma0_outb_chn3_s    cn52xxp1;
-	struct cvmx_usbnx_dma0_outb_chn3_s    cn56xx;
-	struct cvmx_usbnx_dma0_outb_chn3_s    cn56xxp1;
-};
-typedef union cvmx_usbnx_dma0_outb_chn3 cvmx_usbnx_dma0_outb_chn3_t;
-
-/**
- * cvmx_usbn#_dma0_outb_chn4
- *
- * USBN_DMA0_OUTB_CHN4 = USBN's Outbound DMA for USB0 Channel4
- *
- * Contains the starting address for use when USB0 reads from L2C via Channel4.
- * Writing of this register sets the base address.
- */
-union cvmx_usbnx_dma0_outb_chn4
-{
-	uint64_t u64;
-	struct cvmx_usbnx_dma0_outb_chn4_s
-	{
-	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
-	} s;
-	struct cvmx_usbnx_dma0_outb_chn4_s    cn30xx;
-	struct cvmx_usbnx_dma0_outb_chn4_s    cn31xx;
-	struct cvmx_usbnx_dma0_outb_chn4_s    cn50xx;
-	struct cvmx_usbnx_dma0_outb_chn4_s    cn52xx;
-	struct cvmx_usbnx_dma0_outb_chn4_s    cn52xxp1;
-	struct cvmx_usbnx_dma0_outb_chn4_s    cn56xx;
-	struct cvmx_usbnx_dma0_outb_chn4_s    cn56xxp1;
-};
-typedef union cvmx_usbnx_dma0_outb_chn4 cvmx_usbnx_dma0_outb_chn4_t;
-
-/**
- * cvmx_usbn#_dma0_outb_chn5
- *
- * USBN_DMA0_OUTB_CHN5 = USBN's Outbound DMA for USB0 Channel5
- *
- * Contains the starting address for use when USB0 reads from L2C via Channel5.
- * Writing of this register sets the base address.
- */
-union cvmx_usbnx_dma0_outb_chn5
-{
-	uint64_t u64;
-	struct cvmx_usbnx_dma0_outb_chn5_s
-	{
-	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
-	} s;
-	struct cvmx_usbnx_dma0_outb_chn5_s    cn30xx;
-	struct cvmx_usbnx_dma0_outb_chn5_s    cn31xx;
-	struct cvmx_usbnx_dma0_outb_chn5_s    cn50xx;
-	struct cvmx_usbnx_dma0_outb_chn5_s    cn52xx;
-	struct cvmx_usbnx_dma0_outb_chn5_s    cn52xxp1;
-	struct cvmx_usbnx_dma0_outb_chn5_s    cn56xx;
-	struct cvmx_usbnx_dma0_outb_chn5_s    cn56xxp1;
-};
-typedef union cvmx_usbnx_dma0_outb_chn5 cvmx_usbnx_dma0_outb_chn5_t;
-
-/**
- * cvmx_usbn#_dma0_outb_chn6
- *
- * USBN_DMA0_OUTB_CHN6 = USBN's Outbound DMA for USB0 Channel6
- *
- * Contains the starting address for use when USB0 reads from L2C via Channel6.
- * Writing of this register sets the base address.
- */
-union cvmx_usbnx_dma0_outb_chn6
-{
-	uint64_t u64;
-	struct cvmx_usbnx_dma0_outb_chn6_s
-	{
-	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
-	} s;
-	struct cvmx_usbnx_dma0_outb_chn6_s    cn30xx;
-	struct cvmx_usbnx_dma0_outb_chn6_s    cn31xx;
-	struct cvmx_usbnx_dma0_outb_chn6_s    cn50xx;
-	struct cvmx_usbnx_dma0_outb_chn6_s    cn52xx;
-	struct cvmx_usbnx_dma0_outb_chn6_s    cn52xxp1;
-	struct cvmx_usbnx_dma0_outb_chn6_s    cn56xx;
-	struct cvmx_usbnx_dma0_outb_chn6_s    cn56xxp1;
-};
-typedef union cvmx_usbnx_dma0_outb_chn6 cvmx_usbnx_dma0_outb_chn6_t;
-
-/**
- * cvmx_usbn#_dma0_outb_chn7
- *
- * USBN_DMA0_OUTB_CHN7 = USBN's Outbound DMA for USB0 Channel7
- *
- * Contains the starting address for use when USB0 reads from L2C via Channel7.
- * Writing of this register sets the base address.
- */
-union cvmx_usbnx_dma0_outb_chn7
-{
-	uint64_t u64;
-	struct cvmx_usbnx_dma0_outb_chn7_s
-	{
-	uint64_t reserved_36_63               : 28;
-	uint64_t addr                         : 36; /**< Base address for DMA Read from L2C. */
-	} s;
-	struct cvmx_usbnx_dma0_outb_chn7_s    cn30xx;
-	struct cvmx_usbnx_dma0_outb_chn7_s    cn31xx;
-	struct cvmx_usbnx_dma0_outb_chn7_s    cn50xx;
-	struct cvmx_usbnx_dma0_outb_chn7_s    cn52xx;
-	struct cvmx_usbnx_dma0_outb_chn7_s    cn52xxp1;
-	struct cvmx_usbnx_dma0_outb_chn7_s    cn56xx;
-	struct cvmx_usbnx_dma0_outb_chn7_s    cn56xxp1;
-};
-typedef union cvmx_usbnx_dma0_outb_chn7 cvmx_usbnx_dma0_outb_chn7_t;
-
-/**
- * cvmx_usbn#_dma_test
- *
- * USBN_DMA_TEST = USBN's DMA TestRegister
- *
- * This register can cause the external DMA engine to the USB-Core to make transfers from/to L2C/USB-FIFOs
- */
-union cvmx_usbnx_dma_test
-{
-	uint64_t u64;
-	struct cvmx_usbnx_dma_test_s
-	{
-	uint64_t reserved_40_63               : 24;
-	uint64_t done                         : 1;  /**< This field is set when a DMA completes. Writing a
-                                                         '1' to this field clears this bit. */
-	uint64_t req                          : 1;  /**< DMA Request. Writing a 1 to this register
-                                                         will cause a DMA request as specified in the other
-                                                         fields of this register to take place. This field
-                                                         will always read as '0'. */
-	uint64_t f_addr                       : 18; /**< The address to read from in the Data-Fifo. */
-	uint64_t count                        : 11; /**< DMA Request Count. */
-	uint64_t channel                      : 5;  /**< DMA Channel/Enpoint. */
-	uint64_t burst                        : 4;  /**< DMA Burst Size. */
-	} s;
-	struct cvmx_usbnx_dma_test_s          cn30xx;
-	struct cvmx_usbnx_dma_test_s          cn31xx;
-	struct cvmx_usbnx_dma_test_s          cn50xx;
-	struct cvmx_usbnx_dma_test_s          cn52xx;
-	struct cvmx_usbnx_dma_test_s          cn52xxp1;
-	struct cvmx_usbnx_dma_test_s          cn56xx;
-	struct cvmx_usbnx_dma_test_s          cn56xxp1;
-};
-typedef union cvmx_usbnx_dma_test cvmx_usbnx_dma_test_t;
-
-/**
- * cvmx_usbn#_int_enb
- *
- * USBN_INT_ENB = USBN's Interrupt Enable
- *
- * The USBN's interrupt enable register.
- */
-union cvmx_usbnx_int_enb
-{
-	uint64_t u64;
-	struct cvmx_usbnx_int_enb_s
-	{
-	uint64_t reserved_38_63               : 26;
-	uint64_t nd4o_dpf                     : 1;  /**< When set (1) and bit 37 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t nd4o_dpe                     : 1;  /**< When set (1) and bit 36 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t nd4o_rpf                     : 1;  /**< When set (1) and bit 35 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t nd4o_rpe                     : 1;  /**< When set (1) and bit 34 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t ltl_f_pf                     : 1;  /**< When set (1) and bit 33 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t ltl_f_pe                     : 1;  /**< When set (1) and bit 32 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t u2n_c_pe                     : 1;  /**< When set (1) and bit 31 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t u2n_c_pf                     : 1;  /**< When set (1) and bit 30 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t u2n_d_pf                     : 1;  /**< When set (1) and bit 29 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t u2n_d_pe                     : 1;  /**< When set (1) and bit 28 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t n2u_pe                       : 1;  /**< When set (1) and bit 27 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t n2u_pf                       : 1;  /**< When set (1) and bit 26 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t uod_pf                       : 1;  /**< When set (1) and bit 25 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t uod_pe                       : 1;  /**< When set (1) and bit 24 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t rq_q3_e                      : 1;  /**< When set (1) and bit 23 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t rq_q3_f                      : 1;  /**< When set (1) and bit 22 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t rq_q2_e                      : 1;  /**< When set (1) and bit 21 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t rq_q2_f                      : 1;  /**< When set (1) and bit 20 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t rg_fi_f                      : 1;  /**< When set (1) and bit 19 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t rg_fi_e                      : 1;  /**< When set (1) and bit 18 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t l2_fi_f                      : 1;  /**< When set (1) and bit 17 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t l2_fi_e                      : 1;  /**< When set (1) and bit 16 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t l2c_a_f                      : 1;  /**< When set (1) and bit 15 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t l2c_s_e                      : 1;  /**< When set (1) and bit 14 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t dcred_f                      : 1;  /**< When set (1) and bit 13 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t dcred_e                      : 1;  /**< When set (1) and bit 12 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t lt_pu_f                      : 1;  /**< When set (1) and bit 11 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t lt_po_e                      : 1;  /**< When set (1) and bit 10 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t nt_pu_f                      : 1;  /**< When set (1) and bit 9 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t nt_po_e                      : 1;  /**< When set (1) and bit 8 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t pt_pu_f                      : 1;  /**< When set (1) and bit 7 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t pt_po_e                      : 1;  /**< When set (1) and bit 6 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t lr_pu_f                      : 1;  /**< When set (1) and bit 5 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t lr_po_e                      : 1;  /**< When set (1) and bit 4 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t nr_pu_f                      : 1;  /**< When set (1) and bit 3 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t nr_po_e                      : 1;  /**< When set (1) and bit 2 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t pr_pu_f                      : 1;  /**< When set (1) and bit 1 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t pr_po_e                      : 1;  /**< When set (1) and bit 0 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	} s;
-	struct cvmx_usbnx_int_enb_s           cn30xx;
-	struct cvmx_usbnx_int_enb_s           cn31xx;
-	struct cvmx_usbnx_int_enb_cn50xx
-	{
-	uint64_t reserved_38_63               : 26;
-	uint64_t nd4o_dpf                     : 1;  /**< When set (1) and bit 37 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t nd4o_dpe                     : 1;  /**< When set (1) and bit 36 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t nd4o_rpf                     : 1;  /**< When set (1) and bit 35 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t nd4o_rpe                     : 1;  /**< When set (1) and bit 34 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t ltl_f_pf                     : 1;  /**< When set (1) and bit 33 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t ltl_f_pe                     : 1;  /**< When set (1) and bit 32 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t reserved_26_31               : 6;
-	uint64_t uod_pf                       : 1;  /**< When set (1) and bit 25 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t uod_pe                       : 1;  /**< When set (1) and bit 24 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t rq_q3_e                      : 1;  /**< When set (1) and bit 23 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t rq_q3_f                      : 1;  /**< When set (1) and bit 22 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t rq_q2_e                      : 1;  /**< When set (1) and bit 21 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t rq_q2_f                      : 1;  /**< When set (1) and bit 20 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t rg_fi_f                      : 1;  /**< When set (1) and bit 19 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t rg_fi_e                      : 1;  /**< When set (1) and bit 18 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t l2_fi_f                      : 1;  /**< When set (1) and bit 17 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t l2_fi_e                      : 1;  /**< When set (1) and bit 16 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t l2c_a_f                      : 1;  /**< When set (1) and bit 15 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t l2c_s_e                      : 1;  /**< When set (1) and bit 14 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t dcred_f                      : 1;  /**< When set (1) and bit 13 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t dcred_e                      : 1;  /**< When set (1) and bit 12 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t lt_pu_f                      : 1;  /**< When set (1) and bit 11 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t lt_po_e                      : 1;  /**< When set (1) and bit 10 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t nt_pu_f                      : 1;  /**< When set (1) and bit 9 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t nt_po_e                      : 1;  /**< When set (1) and bit 8 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t pt_pu_f                      : 1;  /**< When set (1) and bit 7 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t pt_po_e                      : 1;  /**< When set (1) and bit 6 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t lr_pu_f                      : 1;  /**< When set (1) and bit 5 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t lr_po_e                      : 1;  /**< When set (1) and bit 4 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t nr_pu_f                      : 1;  /**< When set (1) and bit 3 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t nr_po_e                      : 1;  /**< When set (1) and bit 2 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t pr_pu_f                      : 1;  /**< When set (1) and bit 1 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	uint64_t pr_po_e                      : 1;  /**< When set (1) and bit 0 of the USBN_INT_SUM
-                                                         register is asserted the USBN will assert an
-                                                         interrupt. */
-	} cn50xx;
-	struct cvmx_usbnx_int_enb_cn50xx      cn52xx;
-	struct cvmx_usbnx_int_enb_cn50xx      cn52xxp1;
-	struct cvmx_usbnx_int_enb_cn50xx      cn56xx;
-	struct cvmx_usbnx_int_enb_cn50xx      cn56xxp1;
-};
-typedef union cvmx_usbnx_int_enb cvmx_usbnx_int_enb_t;
-
-/**
- * cvmx_usbn#_int_sum
- *
- * USBN_INT_SUM = USBN's Interrupt Summary Register
- *
- * Contains the diffrent interrupt summary bits of the USBN.
- */
-union cvmx_usbnx_int_sum
-{
-	uint64_t u64;
-	struct cvmx_usbnx_int_sum_s
-	{
-	uint64_t reserved_38_63               : 26;
-	uint64_t nd4o_dpf                     : 1;  /**< NCB DMA Out Data Fifo Push Full. */
-	uint64_t nd4o_dpe                     : 1;  /**< NCB DMA Out Data Fifo Pop Empty. */
-	uint64_t nd4o_rpf                     : 1;  /**< NCB DMA Out Request Fifo Push Full. */
-	uint64_t nd4o_rpe                     : 1;  /**< NCB DMA Out Request Fifo Pop Empty. */
-	uint64_t ltl_f_pf                     : 1;  /**< L2C Transfer Length Fifo Push Full. */
-	uint64_t ltl_f_pe                     : 1;  /**< L2C Transfer Length Fifo Pop Empty. */
-	uint64_t u2n_c_pe                     : 1;  /**< U2N Control Fifo Pop Empty. */
-	uint64_t u2n_c_pf                     : 1;  /**< U2N Control Fifo Push Full. */
-	uint64_t u2n_d_pf                     : 1;  /**< U2N Data Fifo Push Full. */
-	uint64_t u2n_d_pe                     : 1;  /**< U2N Data Fifo Pop Empty. */
-	uint64_t n2u_pe                       : 1;  /**< N2U Fifo Pop Empty. */
-	uint64_t n2u_pf                       : 1;  /**< N2U Fifo Push Full. */
-	uint64_t uod_pf                       : 1;  /**< UOD Fifo Push Full. */
-	uint64_t uod_pe                       : 1;  /**< UOD Fifo Pop Empty. */
-	uint64_t rq_q3_e                      : 1;  /**< Request Queue-3 Fifo Pushed When Full. */
-	uint64_t rq_q3_f                      : 1;  /**< Request Queue-3 Fifo Pushed When Full. */
-	uint64_t rq_q2_e                      : 1;  /**< Request Queue-2 Fifo Pushed When Full. */
-	uint64_t rq_q2_f                      : 1;  /**< Request Queue-2 Fifo Pushed When Full. */
-	uint64_t rg_fi_f                      : 1;  /**< Register Request Fifo Pushed When Full. */
-	uint64_t rg_fi_e                      : 1;  /**< Register Request Fifo Pushed When Full. */
-	uint64_t lt_fi_f                      : 1;  /**< L2C Request Fifo Pushed When Full. */
-	uint64_t lt_fi_e                      : 1;  /**< L2C Request Fifo Pushed When Full. */
-	uint64_t l2c_a_f                      : 1;  /**< L2C Credit Count Added When Full. */
-	uint64_t l2c_s_e                      : 1;  /**< L2C Credit Count Subtracted When Empty. */
-	uint64_t dcred_f                      : 1;  /**< Data CreditFifo Pushed When Full. */
-	uint64_t dcred_e                      : 1;  /**< Data Credit Fifo Pushed When Full. */
-	uint64_t lt_pu_f                      : 1;  /**< L2C Trasaction Fifo Pushed When Full. */
-	uint64_t lt_po_e                      : 1;  /**< L2C Trasaction Fifo Popped When Full. */
-	uint64_t nt_pu_f                      : 1;  /**< NPI Trasaction Fifo Pushed When Full. */
-	uint64_t nt_po_e                      : 1;  /**< NPI Trasaction Fifo Popped When Full. */
-	uint64_t pt_pu_f                      : 1;  /**< PP  Trasaction Fifo Pushed When Full. */
-	uint64_t pt_po_e                      : 1;  /**< PP  Trasaction Fifo Popped When Full. */
-	uint64_t lr_pu_f                      : 1;  /**< L2C Request Fifo Pushed When Full. */
-	uint64_t lr_po_e                      : 1;  /**< L2C Request Fifo Popped When Empty. */
-	uint64_t nr_pu_f                      : 1;  /**< NPI Request Fifo Pushed When Full. */
-	uint64_t nr_po_e                      : 1;  /**< NPI Request Fifo Popped When Empty. */
-	uint64_t pr_pu_f                      : 1;  /**< PP  Request Fifo Pushed When Full. */
-	uint64_t pr_po_e                      : 1;  /**< PP  Request Fifo Popped When Empty. */
-	} s;
-	struct cvmx_usbnx_int_sum_s           cn30xx;
-	struct cvmx_usbnx_int_sum_s           cn31xx;
-	struct cvmx_usbnx_int_sum_cn50xx
-	{
-	uint64_t reserved_38_63               : 26;
-	uint64_t nd4o_dpf                     : 1;  /**< NCB DMA Out Data Fifo Push Full. */
-	uint64_t nd4o_dpe                     : 1;  /**< NCB DMA Out Data Fifo Pop Empty. */
-	uint64_t nd4o_rpf                     : 1;  /**< NCB DMA Out Request Fifo Push Full. */
-	uint64_t nd4o_rpe                     : 1;  /**< NCB DMA Out Request Fifo Pop Empty. */
-	uint64_t ltl_f_pf                     : 1;  /**< L2C Transfer Length Fifo Push Full. */
-	uint64_t ltl_f_pe                     : 1;  /**< L2C Transfer Length Fifo Pop Empty. */
-	uint64_t reserved_26_31               : 6;
-	uint64_t uod_pf                       : 1;  /**< UOD Fifo Push Full. */
-	uint64_t uod_pe                       : 1;  /**< UOD Fifo Pop Empty. */
-	uint64_t rq_q3_e                      : 1;  /**< Request Queue-3 Fifo Pushed When Full. */
-	uint64_t rq_q3_f                      : 1;  /**< Request Queue-3 Fifo Pushed When Full. */
-	uint64_t rq_q2_e                      : 1;  /**< Request Queue-2 Fifo Pushed When Full. */
-	uint64_t rq_q2_f                      : 1;  /**< Request Queue-2 Fifo Pushed When Full. */
-	uint64_t rg_fi_f                      : 1;  /**< Register Request Fifo Pushed When Full. */
-	uint64_t rg_fi_e                      : 1;  /**< Register Request Fifo Pushed When Full. */
-	uint64_t lt_fi_f                      : 1;  /**< L2C Request Fifo Pushed When Full. */
-	uint64_t lt_fi_e                      : 1;  /**< L2C Request Fifo Pushed When Full. */
-	uint64_t l2c_a_f                      : 1;  /**< L2C Credit Count Added When Full. */
-	uint64_t l2c_s_e                      : 1;  /**< L2C Credit Count Subtracted When Empty. */
-	uint64_t dcred_f                      : 1;  /**< Data CreditFifo Pushed When Full. */
-	uint64_t dcred_e                      : 1;  /**< Data Credit Fifo Pushed When Full. */
-	uint64_t lt_pu_f                      : 1;  /**< L2C Trasaction Fifo Pushed When Full. */
-	uint64_t lt_po_e                      : 1;  /**< L2C Trasaction Fifo Popped When Full. */
-	uint64_t nt_pu_f                      : 1;  /**< NPI Trasaction Fifo Pushed When Full. */
-	uint64_t nt_po_e                      : 1;  /**< NPI Trasaction Fifo Popped When Full. */
-	uint64_t pt_pu_f                      : 1;  /**< PP  Trasaction Fifo Pushed When Full. */
-	uint64_t pt_po_e                      : 1;  /**< PP  Trasaction Fifo Popped When Full. */
-	uint64_t lr_pu_f                      : 1;  /**< L2C Request Fifo Pushed When Full. */
-	uint64_t lr_po_e                      : 1;  /**< L2C Request Fifo Popped When Empty. */
-	uint64_t nr_pu_f                      : 1;  /**< NPI Request Fifo Pushed When Full. */
-	uint64_t nr_po_e                      : 1;  /**< NPI Request Fifo Popped When Empty. */
-	uint64_t pr_pu_f                      : 1;  /**< PP  Request Fifo Pushed When Full. */
-	uint64_t pr_po_e                      : 1;  /**< PP  Request Fifo Popped When Empty. */
-	} cn50xx;
-	struct cvmx_usbnx_int_sum_cn50xx      cn52xx;
-	struct cvmx_usbnx_int_sum_cn50xx      cn52xxp1;
-	struct cvmx_usbnx_int_sum_cn50xx      cn56xx;
-	struct cvmx_usbnx_int_sum_cn50xx      cn56xxp1;
-};
-typedef union cvmx_usbnx_int_sum cvmx_usbnx_int_sum_t;
-
-/**
  * cvmx_usbn#_usbp_ctl_status
  *
  * USBN_USBP_CTL_STATUS = USBP Control And Status Register