summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorRanjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com>2009-12-11 10:58:00 -0600
committerRanjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com>2009-12-11 12:39:37 -0600
commit968baa74639773dc4a442846195b94f421c28b3f (patch)
treec646f1330b7a139334bdb0f43c768f8c97f44c6e
parent8fec138382a5faaec367d971620a9657e03e153d (diff)
ENGR00119263: MX51 : Fix pll_set_rate function
pll_set_rate function should only wait for PLL relock if PLL is enabled. Also add a timeout to the infinte loop. Signed-off-by: Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com>
-rw-r--r--arch/arm/mach-mx51/clock.c29
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_dvfs.h2
-rw-r--r--drivers/mxc/ipu3/ipu_common.c2
3 files changed, 21 insertions, 12 deletions
diff --git a/arch/arm/mach-mx51/clock.c b/arch/arm/mach-mx51/clock.c
index 5b053fc268e6..6a4f854c2b2c 100644
--- a/arch/arm/mach-mx51/clock.c
+++ b/arch/arm/mach-mx51/clock.c
@@ -320,8 +320,10 @@ static void _clk_pll_recalc(struct clk *clk)
static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
{
- u32 reg;
+ u32 reg, reg1;
u32 pllbase;
+ struct timespec nstimeofday;
+ struct timespec curtime;
long mfi, pdf, mfn, mfd = 999999;
s64 temp64;
@@ -357,19 +359,26 @@ static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
__raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
__raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
}
-
/* If auto restart is disabled, restart the PLL and
* wait for it to lock.
*/
- reg = __raw_readl(pllbase + MXC_PLL_DP_CONFIG);
- if (!reg & MXC_PLL_DP_CONFIG_AREN) {
- reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
- reg |= MXC_PLL_DP_CTL_RST;
- __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
+ reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+ if (reg & MXC_PLL_DP_CTL_UPEN) {
+ reg = __raw_readl(pllbase + MXC_PLL_DP_CONFIG);
+ if (!(reg & MXC_PLL_DP_CONFIG_AREN)) {
+ reg1 = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+ reg1 |= MXC_PLL_DP_CTL_RST;
+ __raw_writel(reg1, pllbase + MXC_PLL_DP_CTL);
+ }
+ /* Wait for lock */
+ getnstimeofday(&nstimeofday);
+ while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL)
+ & MXC_PLL_DP_CTL_LRF)) {
+ getnstimeofday(&curtime);
+ if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+ panic("pll_set_rate: pll relock failed\n");
+ }
}
- while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF))
- ;
-
clk->rate = rate;
return 0;
}
diff --git a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
index bc8904cf633f..8b9d6f7e9b6f 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
@@ -224,7 +224,7 @@ extern int start_dvfs_per(void);
extern void stop_dvfs_per(void);
extern int dvfs_per_active(void);
extern int dvfs_per_divider_active(void);
-extern int dvfs_per_pixel_clk_limit();
+extern int dvfs_per_pixel_clk_limit(void);
#else
static inline int start_dvfs_per(void)
{
diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c
index 5d90d47e34b9..56657b8f6ea1 100644
--- a/drivers/mxc/ipu3/ipu_common.c
+++ b/drivers/mxc/ipu3/ipu_common.c
@@ -212,7 +212,7 @@ static void _ipu_pixel_clk_disable(struct clk *clk)
static int _ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
{
- u32 di_gen = 0;/*__raw_readl(DI_GENERAL(clk->id));*/
+ u32 di_gen = __raw_readl(DI_GENERAL(clk->id));
if (parent == g_ipu_clk)
di_gen &= ~DI_GEN_DI_CLK_EXT;