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authorJason Liu <r64343@freescale.com>2012-02-09 14:09:58 +0800
committerJason Liu <r64343@freescale.com>2012-02-09 21:12:35 +0800
commitaadace1f91936e01604ba8310de63eac8f3d7eaf (patch)
tree6862f4f969749aab6c6e19338ef1395f29425a62
parent62ea60a0712052c43618d1cac968ccf51e3a4e5e (diff)
ENGR00174152 i.mx6/clock: set ddr clock parent to pll2_mfd_400M
on i.mx6dl, DDR clock is sourcing from pll2_mfd_400M, so, we need set DDR/periph_clk parent to pll2_mfd_400M during clock init, which will setup the clock usecount of pll2_mfd_400M correctly, otherwise, when all the child device with clock source from pll2_mfd_400M turn off, the pll2_mfd_400M will turns off automaticly, which will cause system hang due to DDR clock is off when code is runing on it. Signed-off-by: Jason Liu <r64343@freescale.com>
-rw-r--r--arch/arm/mach-mx6/clock.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index c508b41d4730..5e703a8c9153 100644
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -5083,7 +5083,8 @@ static void clk_tree_init(void)
reg = __raw_readl(MMDC_MDMISC_OFFSET);
if ((reg & MMDC_MDMISC_DDR_TYPE_MASK) ==
- (0x1 << MMDC_MDMISC_DDR_TYPE_OFFSET)) {
+ (0x1 << MMDC_MDMISC_DDR_TYPE_OFFSET) ||
+ cpu_is_mx6dl()) {
clk_set_parent(&periph_clk, &pll2_pfd_400M);
printk(KERN_INFO "Set periph_clk's parent to pll2_pfd_400M!\n");
}