ENGR00233366-2 mx6q_sabresd mx6sl_arm2 mx6sl_evk: config in LDO bypass

U-boot will not care about ldo bypass, move these code from u-boot to kernel.
Move the workaround for PFUZE1.0 to kernel too.
Signed-off-by: Robin Gong <b38343@freescale.com>

7 files changed, 224 insertions, 127 deletions

diff --git a/arch/arm/mach-mx6/board-mx6q_sabresd.c b/arch/arm/mach-mx6/board-mx6q_sabresd.c
index 86f1091cdcf1..69afc3576522 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabresd.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabresd.c
@@ -1586,14 +1586,8 @@ static struct platform_pwm_backlight_data mx6_sabresd_pwm_backlight_data = {
 };
 
 static struct mxc_dvfs_platform_data sabresd_dvfscore_data = {
-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	.reg_id = "VDDCORE",
 	.soc_id	= "VDDSOC",
-#else
-	.reg_id = "cpu_vddgp",
-	.soc_id = "cpu_vddsoc",
-	.pu_id = "cpu_vddvpu",
-#endif
 	.clk1_id = "cpu_clk",
 	.clk2_id = "gpc_dvfs_clk",
 	.gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
@@ -1691,7 +1685,6 @@ static void __init mx6_sabresd_board_init(void)
 
 	gp_reg_id = sabresd_dvfscore_data.reg_id;
 	soc_reg_id = sabresd_dvfscore_data.soc_id;
-	pu_reg_id = sabresd_dvfscore_data.pu_id;
 	mx6q_sabresd_init_uart();
 
 	/*
@@ -1815,9 +1808,6 @@ static void __init mx6_sabresd_board_init(void)
 	imx6q_add_dma();
 
 	imx6q_add_dvfs_core(&sabresd_dvfscore_data);
-#ifndef CONFIG_MX6_INTER_LDO_BYPASS
-	mx6_cpu_regulator_init();
-#endif
 	imx6q_add_device_buttons();
 
 	/* enable sensor 3v3 and 1v8 */
diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.c b/arch/arm/mach-mx6/board-mx6sl_arm2.c
index f62a97f5465e..d72fc63ebdc4 100755
--- a/arch/arm/mach-mx6/board-mx6sl_arm2.c
+++ b/arch/arm/mach-mx6/board-mx6sl_arm2.c
@@ -582,14 +582,8 @@ static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
 };
 
 static struct mxc_dvfs_platform_data mx6sl_arm2_dvfscore_data = {
-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	.reg_id			= "VDDCORE",
 	.soc_id			= "VDDSOC",
-#else
-	.reg_id			= "cpu_vddgp",
-	.soc_id			= "cpu_vddsoc",
-	.pu_id			= "cpu_vddvpu",
-#endif
 	.clk1_id		= "cpu_clk",
 	.clk2_id		= "gpc_dvfs_clk",
 	.gpc_cntr_offset	= MXC_GPC_CNTR_OFFSET,
@@ -1218,15 +1212,8 @@ static void __init mx6_arm2_init(void)
 
 	elan_ts_init();
 
-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
-	gp_reg_id = mx6sl_arm2_dvfscore_data.reg_id;
-	soc_reg_id = mx6sl_arm2_dvfscore_data.soc_id;
-#else
 	gp_reg_id = mx6sl_arm2_dvfscore_data.reg_id;
 	soc_reg_id = mx6sl_arm2_dvfscore_data.soc_id;
-	pu_reg_id = mx6sl_arm2_dvfscore_data.pu_id;
-	mx6_cpu_regulator_init();
-#endif
 
 	imx6q_add_imx_snvs_rtc();
 
diff --git a/arch/arm/mach-mx6/board-mx6sl_evk.c b/arch/arm/mach-mx6/board-mx6sl_evk.c
index 6836310b7d17..46bacc1dc457 100644
--- a/arch/arm/mach-mx6/board-mx6sl_evk.c
+++ b/arch/arm/mach-mx6/board-mx6sl_evk.c
@@ -758,14 +758,8 @@ static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
 };
 
 static struct mxc_dvfs_platform_data mx6sl_evk_dvfscore_data = {
-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	.reg_id			= "VDDCORE",
 	.soc_id			= "VDDSOC",
-#else
-	.reg_id			= "cpu_vddgp",
-	.soc_id			= "cpu_vddsoc",
-	.pu_id			= "cpu_vddvpu",
-#endif
 	.clk1_id		= "cpu_clk",
 	.clk2_id		= "gpc_dvfs_clk",
 	.gpc_cntr_offset	= MXC_GPC_CNTR_OFFSET,
@@ -1461,15 +1455,8 @@ static void __init mx6_evk_init(void)
 
 	elan_ts_init();
 
-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
-	gp_reg_id = mx6sl_evk_dvfscore_data.reg_id;
-	soc_reg_id = mx6sl_evk_dvfscore_data.soc_id;
-#else
 	gp_reg_id = mx6sl_evk_dvfscore_data.reg_id;
 	soc_reg_id = mx6sl_evk_dvfscore_data.soc_id;
-	pu_reg_id = mx6sl_evk_dvfscore_data.pu_id;
-	mx6_cpu_regulator_init();
-#endif
 
 	imx6q_add_imx_snvs_rtc();
 
diff --git a/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c
index 3987777d56ff..b0ca5a30de3e 100644
--- a/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c
+++ b/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c
@@ -26,6 +26,7 @@
 #include <linux/mfd/pfuze.h>
 #include <linux/io.h>
 #include <mach/irqs.h>
+#include <mach/system.h>
 #include "crm_regs.h"
 #include "regs-anadig.h"
 #include "cpu_op-mx6.h"
@@ -57,6 +58,7 @@
 #define PFUZE100_SW1CCON_SPEED_M	(0x3<<6)
 
 extern u32 arm_max_freq;
+extern u32 enable_ldo_mode;
 
 static struct regulator_consumer_supply sw1a_consumers[] = {
 	{
@@ -397,7 +399,6 @@ static struct regulator_init_data vgen6_init = {
 static int pfuze100_init(struct mc_pfuze *pfuze)
 {
 	int ret, i;
-	unsigned int reg;
 	unsigned char value;
 	/*read Device ID*/
 	ret = pfuze_reg_read(pfuze, PFUZE100_DEVICEID, &value);
@@ -441,39 +442,59 @@ static int pfuze100_init(struct mc_pfuze *pfuze)
 		}
 
 	}
+	/*use ldo active mode if use 1.2GHz,otherwise use ldo bypass mode*/
 	if (arm_max_freq == CPU_AT_1_2GHz) {
-		/*VDDARM_IN 1.475V*/
+			/*VDDARM_IN 1.425*/
 		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL,
 					PFUZE100_SW1AVOL_VSEL_M,
-					0x2f);
+					0x2d);
 		if (ret)
 			goto err;
-		/*VDDSOC_IN 1.475V*/
+		/*VDDSOC_IN 1.425V*/
 		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL,
 					PFUZE100_SW1CVOL_VSEL_M,
-					0x2f);
+					0x2d);
+		if (ret)
+			goto err;
+		enable_ldo_mode = LDO_MODE_ENABLED;
+	} else if (enable_ldo_mode == LDO_MODE_BYPASSED) {
+		/*decrease VDDARM_IN/VDDSOC_IN,since we will use ldo bypass mode*/
+		/*VDDARM_IN 1.3V*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL,
+					PFUZE100_SW1AVOL_VSEL_M,
+					0x28);
+		if (ret)
+			goto err;
+		/*VDDSOC_IN 1.3V*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL,
+					PFUZE100_SW1CVOL_VSEL_M,
+					0x28);
+		if (ret)
+			goto err;
+		/*set SW1AB/1C DVSPEED as 25mV step each 4us,quick than 16us before.*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
+				    PFUZE100_SW1ACON_SPEED_M,
+				    PFUZE100_SW1ACON_SPEED_VAL);
+		if (ret)
+			goto err;
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CCON,
+				    PFUZE100_SW1CCON_SPEED_M,
+				    PFUZE100_SW1CCON_SPEED_VAL);
+		if (ret)
+			goto err;
+	} else if (enable_ldo_mode != LDO_MODE_BYPASSED) {
+		/*Increase VDDARM_IN/VDDSOC_IN to 1.375V in ldo active mode*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL,
+					PFUZE100_SW1AVOL_VSEL_M,
+					0x2b);
+		if (ret)
+			goto err;
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL,
+					PFUZE100_SW1CVOL_VSEL_M,
+					0x2b);
 		if (ret)
 			goto err;
-		/*set VDDSOC&VDDPU to 1.25V*/
-		reg = __raw_readl(ANADIG_REG_CORE);
-		reg &= ~BM_ANADIG_REG_CORE_REG2_TRG;
-		reg |= BF_ANADIG_REG_CORE_REG2_TRG(0x16);
-		reg &= ~BM_ANADIG_REG_CORE_REG1_TRG;
-		reg |= BF_ANADIG_REG_CORE_REG1_TRG(0x16);
-		__raw_writel(reg, ANADIG_REG_CORE);
-
 	}
-	/*set SW1AB/1C DVSPEED as 25mV step each 4us,quick than 16us before.*/
-	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
-			    PFUZE100_SW1ACON_SPEED_M,
-			    PFUZE100_SW1ACON_SPEED_VAL);
-	if (ret)
-		goto err;
-	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CCON,
-			    PFUZE100_SW1CCON_SPEED_M,
-			    PFUZE100_SW1CCON_SPEED_VAL);
-	if (ret)
-		goto err;
 	return 0;
 err:
 	printk(KERN_ERR "pfuze100 init error!\n");
diff --git a/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c
index 6b38bd000bc0..c18a01433c4f 100644
--- a/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c
+++ b/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c
@@ -26,6 +26,7 @@
 #include <linux/mfd/pfuze.h>
 #include <linux/io.h>
 #include <mach/irqs.h>
+#include <mach/system.h>
 #include "crm_regs.h"
 #include "regs-anadig.h"
 #include "cpu_op-mx6.h"
@@ -57,8 +58,8 @@
 #define PFUZE100_SW1CCON_SPEED_M	(0x3<<6)
 
 extern u32 arm_max_freq;
+extern u32 enable_ldo_mode;
 
-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
 static struct regulator_consumer_supply sw1_consumers[] = {
 	{
 		.supply	   = "VDDCORE",
@@ -69,7 +70,6 @@ static struct regulator_consumer_supply sw1c_consumers[] = {
 		.supply	   = "VDDSOC",
 	},
 };
-#endif
 
 static struct regulator_consumer_supply sw2_consumers[] = {
 	{
@@ -152,10 +152,8 @@ static struct regulator_init_data sw1a_init = {
 			},
 	},
 
-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	.num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
 	.consumer_supplies = sw1_consumers,
-#endif
 };
 
 static struct regulator_init_data sw1b_init = {
@@ -186,10 +184,8 @@ static struct regulator_init_data sw1c_init = {
 				.enabled = 1,
 			},
 	},
-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	.num_consumer_supplies = ARRAY_SIZE(sw1c_consumers),
 	.consumer_supplies = sw1c_consumers,
-#endif
 };
 
 static struct regulator_init_data sw2_init = {
@@ -390,8 +386,10 @@ static struct regulator_init_data vgen6_init = {
 static int pfuze100_init(struct mc_pfuze *pfuze)
 {
 	int ret, i;
-	unsigned int reg;
 	unsigned char value;
+	/*use default mode(ldo bypass) if no param from cmdline*/
+	if (enable_ldo_mode == LDO_MODE_DEFAULT)
+		enable_ldo_mode = LDO_MODE_BYPASSED;
 	/*read Device ID*/
 	ret = pfuze_reg_read(pfuze, PFUZE100_DEVICEID, &value);
 	if (ret)
@@ -434,40 +432,59 @@ static int pfuze100_init(struct mc_pfuze *pfuze)
 		}
 
 	}
-
+	/*use ldo active mode if use 1.2GHz,otherwise use ldo bypass mode*/
 	if (arm_max_freq == CPU_AT_1_2GHz) {
-		/*VDDARM_IN 1.475V*/
+			/*VDDARM_IN 1.425*/
 		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL,
 					PFUZE100_SW1AVOL_VSEL_M,
-					0x2f);
+					0x2d);
 		if (ret)
 			goto err;
-		/*VDDSOC_IN 1.475V*/
+		/*VDDSOC_IN 1.425V*/
 		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL,
 					PFUZE100_SW1CVOL_VSEL_M,
-					0x2f);
+					0x2d);
+		if (ret)
+			goto err;
+		enable_ldo_mode = LDO_MODE_ENABLED;
+	} else if (enable_ldo_mode == LDO_MODE_BYPASSED) {
+		/*decrease VDDARM_IN/VDDSOC_IN,since we will use ldo bypass mode*/
+		/*VDDARM_IN 1.3V*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL,
+					PFUZE100_SW1AVOL_VSEL_M,
+					0x28);
+		if (ret)
+			goto err;
+		/*VDDSOC_IN 1.3V*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL,
+					PFUZE100_SW1CVOL_VSEL_M,
+					0x28);
+		if (ret)
+			goto err;
+		/*set SW1AB/1C DVSPEED as 25mV step each 4us,quick than 16us before.*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
+				    PFUZE100_SW1ACON_SPEED_M,
+				    PFUZE100_SW1ACON_SPEED_VAL);
+		if (ret)
+			goto err;
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CCON,
+				    PFUZE100_SW1CCON_SPEED_M,
+				    PFUZE100_SW1CCON_SPEED_VAL);
+		if (ret)
+			goto err;
+	} else if (enable_ldo_mode != LDO_MODE_BYPASSED) {
+		/*Increase VDDARM_IN/VDDSOC_IN to 1.375V in ldo active mode*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL,
+					PFUZE100_SW1AVOL_VSEL_M,
+					0x2b);
+		if (ret)
+			goto err;
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL,
+					PFUZE100_SW1CVOL_VSEL_M,
+					0x2b);
 		if (ret)
 			goto err;
-		/*set VDDSOC&VDDPU to 1.25V*/
-		reg = __raw_readl(ANADIG_REG_CORE);
-		reg &= ~BM_ANADIG_REG_CORE_REG2_TRG;
-		reg |= BF_ANADIG_REG_CORE_REG2_TRG(0x16);
-		reg &= ~BM_ANADIG_REG_CORE_REG1_TRG;
-		reg |= BF_ANADIG_REG_CORE_REG1_TRG(0x16);
-		__raw_writel(reg, ANADIG_REG_CORE);
-
 	}
-	/*set SW1AB/1C DVSPEED as 25mV step each 4us,quick than 16us before.*/
-	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
-			    PFUZE100_SW1ACON_SPEED_M,
-			    PFUZE100_SW1ACON_SPEED_VAL);
-	if (ret)
-		goto err;
-	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CCON,
-			    PFUZE100_SW1CCON_SPEED_M,
-			    PFUZE100_SW1CCON_SPEED_VAL);
-	if (ret)
-		goto err;
 	return 0;
 err:
 	printk(KERN_ERR "pfuze100 init error!\n");
diff --git a/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c
index 55a802b76b68..7cebb8f2fd3f 100644
--- a/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c
+++ b/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c
@@ -25,6 +25,8 @@
 #include <linux/regulator/machine.h>
 #include <linux/mfd/pfuze.h>
 #include <mach/irqs.h>
+#include <mach/system.h>
+#include "cpu_op-mx6.h"
 
 /*
  * Convenience conversion.
@@ -47,9 +49,14 @@
 #define PFUZE100_SW1CCON		49
 #define PFUZE100_SW1CCON_SPEED_VAL	(0x1<<6)	/*default */
 #define PFUZE100_SW1CCON_SPEED_M	(0x3<<6)
+#define PFUZE100_SW1AVOL       32
+#define PFUZE100_SW1AVOL_VSEL_M        (0x3f<<0)
+#define PFUZE100_SW1CVOL       46
+#define PFUZE100_SW1CVOL_VSEL_M        (0x3f<<0)
+extern u32 enable_ldo_mode;
+extern u32 arm_max_freq;
 
 
-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
 static struct regulator_consumer_supply sw1_consumers[] = {
 	{
 		.supply	   = "VDDCORE",
@@ -60,7 +67,6 @@ static struct regulator_consumer_supply sw1c_consumers[] = {
 		.supply	   = "VDDSOC",
 	},
 };
-#endif
 
 static struct regulator_consumer_supply sw2_consumers[] = {
 	{
@@ -143,10 +149,8 @@ static struct regulator_init_data sw1a_init = {
 				.enabled = 1,
 			},
 	},
-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	.num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
 	.consumer_supplies = sw1_consumers,
-#endif
 };
 
 static struct regulator_init_data sw1b_init = {
@@ -177,10 +181,8 @@ static struct regulator_init_data sw1c_init = {
 				.enabled = 1,
 			},
 	},
-	#ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	.num_consumer_supplies = ARRAY_SIZE(sw1c_consumers),
 	.consumer_supplies = sw1c_consumers,
-	#endif
 };
 
 static struct regulator_init_data sw2_init = {
@@ -383,8 +385,11 @@ static struct regulator_init_data vgen6_init = {
 static int pfuze100_init(struct mc_pfuze *pfuze)
 {
 	int ret, i;
-	unsigned int reg;
 	unsigned char value;
+
+	/*use default mode(ldo bypass) if no param from cmdline*/
+	if (enable_ldo_mode == LDO_MODE_DEFAULT)
+		enable_ldo_mode = LDO_MODE_BYPASSED;
 	/*read Device ID*/
 	ret = pfuze_reg_read(pfuze, PFUZE100_DEVICEID, &value);
 	if (ret)
@@ -427,17 +432,60 @@ static int pfuze100_init(struct mc_pfuze *pfuze)
 		}
 
 	}
-	/*set SW1AB/SW1C DVSPEED as 25mV step each 4us,quick than 16us before.*/
-	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
-			    PFUZE100_SW1ACON_SPEED_M,
-			    PFUZE100_SW1ACON_SPEED_VAL);
-	if (ret)
-		goto err;
-	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CCON,
-			    PFUZE100_SW1CCON_SPEED_M,
-			    PFUZE100_SW1CCON_SPEED_VAL);
-	if (ret)
-		goto err;
+	/*use ldo active mode if use 1.2GHz,otherwise use ldo bypass mode*/
+	if (arm_max_freq == CPU_AT_1_2GHz) {
+			/*VDDARM_IN 1.47*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL,
+					PFUZE100_SW1AVOL_VSEL_M,
+					0x2f);
+		if (ret)
+			goto err;
+		/*VDDSOC_IN 1.475V*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL,
+					PFUZE100_SW1CVOL_VSEL_M,
+					0x2f);
+		if (ret)
+			goto err;
+		enable_ldo_mode = LDO_MODE_ENABLED;
+	} else if (enable_ldo_mode == LDO_MODE_BYPASSED) {
+		/*decrease VDDARM_IN/VDDSOC_IN,since we will use dynamic ldo bypass
+		*mode or ldo bypass mode here.*/
+		/*VDDARM_IN 1.3V*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL,
+					PFUZE100_SW1AVOL_VSEL_M,
+					0x28);
+		if (ret)
+			goto err;
+		/*VDDSOC_IN 1.3V*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL,
+					PFUZE100_SW1CVOL_VSEL_M,
+					0x28);
+		if (ret)
+			goto err;
+		/*set SW1AB/SW1C DVSPEED as 25mV step each 4us,quick than 16us before.*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
+				    PFUZE100_SW1ACON_SPEED_M,
+				    PFUZE100_SW1ACON_SPEED_VAL);
+		if (ret)
+			goto err;
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CCON,
+				    PFUZE100_SW1CCON_SPEED_M,
+				    PFUZE100_SW1CCON_SPEED_VAL);
+		if (ret)
+			goto err;
+	} else if (enable_ldo_mode != LDO_MODE_BYPASSED) {
+		/*Increase VDDARM_IN/VDDSOC_IN to 1.375V in ldo active mode*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL,
+					PFUZE100_SW1AVOL_VSEL_M,
+					0x2b);
+		if (ret)
+			goto err;
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL,
+					PFUZE100_SW1CVOL_VSEL_M,
+					0x2b);
+		if (ret)
+			goto err;
+	}
 	return 0;
 err:
 	printk(KERN_ERR "pfuze100 init error!\n");
diff --git a/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c
index bfd5fafc1d1b..14bd33ffe00c 100644
--- a/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c
+++ b/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c
@@ -25,6 +25,8 @@
 #include <linux/regulator/machine.h>
 #include <linux/mfd/pfuze.h>
 #include <mach/irqs.h>
+#include <mach/system.h>
+#include "cpu_op-mx6.h"
 
 /*
  * Convenience conversion.
@@ -47,8 +49,13 @@
 #define PFUZE100_SW1CCON		49
 #define PFUZE100_SW1CCON_SPEED_VAL	(0x1<<6)	/*default */
 #define PFUZE100_SW1CCON_SPEED_M	(0x3<<6)
+#define PFUZE100_SW1AVOL       32
+#define PFUZE100_SW1AVOL_VSEL_M        (0x3f<<0)
+#define PFUZE100_SW1CVOL       46
+#define PFUZE100_SW1CVOL_VSEL_M        (0x3f<<0)
 
-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+extern u32 enable_ldo_mode;
+extern u32 arm_max_freq;
 static struct regulator_consumer_supply sw1_consumers[] = {
 	{
 		.supply	   = "VDDCORE",
@@ -59,7 +66,6 @@ static struct regulator_consumer_supply sw1c_consumers[] = {
 		.supply	   = "VDDSOC",
 	},
 };
-#endif
 
 static struct regulator_consumer_supply sw2_consumers[] = {
 	{
@@ -146,10 +152,8 @@ static struct regulator_init_data sw1a_init = {
 				.enabled = 1,
 			},
 	},
-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	.num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
 	.consumer_supplies = sw1_consumers,
-#endif
 };
 
 static struct regulator_init_data sw1b_init = {
@@ -180,10 +184,8 @@ static struct regulator_init_data sw1c_init = {
 				.enabled = 1,
 			},
 	},
-#ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	.num_consumer_supplies = ARRAY_SIZE(sw1c_consumers),
 	.consumer_supplies = sw1c_consumers,
-#endif
 };
 
 static struct regulator_init_data sw2_init = {
@@ -388,8 +390,10 @@ static struct regulator_init_data vgen6_init = {
 static int pfuze100_init(struct mc_pfuze *pfuze)
 {
 	int ret, i;
-	unsigned int reg;
 	unsigned char value;
+	/*use default mode(ldo bypass) if no param from cmdline*/
+	if (enable_ldo_mode == LDO_MODE_DEFAULT)
+		enable_ldo_mode = LDO_MODE_BYPASSED;
 	/*read Device ID*/
 	ret = pfuze_reg_read(pfuze, PFUZE100_DEVICEID, &value);
 	if (ret)
@@ -432,18 +436,61 @@ static int pfuze100_init(struct mc_pfuze *pfuze)
 		}
 
 	}
+	/*use ldo active mode if use 1.2GHz,otherwise use ldo bypass mode*/
+	if (arm_max_freq == CPU_AT_1_2GHz) {
+			/*VDDARM_IN 1.47*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL,
+					PFUZE100_SW1AVOL_VSEL_M,
+					0x2f);
+		if (ret)
+			goto err;
+		/*VDDSOC_IN 1.475V*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL,
+					PFUZE100_SW1CVOL_VSEL_M,
+					0x2f);
+		if (ret)
+			goto err;
+		enable_ldo_mode = LDO_MODE_ENABLED;
+	} else if (enable_ldo_mode == LDO_MODE_BYPASSED) {
+		/*decrease VDDARM_IN/VDDSOC_IN,since we will use dynamic ldo bypass
+		*mode or ldo bypass mode here.*/
+		/*VDDARM_IN 1.3V*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL,
+					PFUZE100_SW1AVOL_VSEL_M,
+					0x28);
+		if (ret)
+			goto err;
+		/*VDDSOC_IN 1.3V*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL,
+					PFUZE100_SW1CVOL_VSEL_M,
+					0x28);
+		if (ret)
+			goto err;
 
-	/*set SW1AB/SW1CDVSPEED as 25mV step each 4us,quick than 16us before.*/
-	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
-			    PFUZE100_SW1ACON_SPEED_M,
-			    PFUZE100_SW1ACON_SPEED_VAL);
-	if (ret)
-		goto err;
-	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CCON,
-			    PFUZE100_SW1CCON_SPEED_M,
-			    PFUZE100_SW1CCON_SPEED_VAL);
-	if (ret)
-		goto err;
+		/*set SW1AB/SW1CDVSPEED as 25mV step each 4us,quick than 16us before.*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
+				    PFUZE100_SW1ACON_SPEED_M,
+				    PFUZE100_SW1ACON_SPEED_VAL);
+		if (ret)
+			goto err;
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CCON,
+				    PFUZE100_SW1CCON_SPEED_M,
+				    PFUZE100_SW1CCON_SPEED_VAL);
+		if (ret)
+			goto err;
+	} else if (enable_ldo_mode != LDO_MODE_BYPASSED) {
+		/*Increase VDDARM_IN/VDDSOC_IN to 1.375V in ldo active mode*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL,
+					PFUZE100_SW1AVOL_VSEL_M,
+					0x2b);
+		if (ret)
+			goto err;
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL,
+					PFUZE100_SW1CVOL_VSEL_M,
+					0x2b);
+		if (ret)
+			goto err;
+	}
 	return 0;
 err:
 	printk(KERN_ERR "pfuze100 init error!\n");