diff options
| author | Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com> | 2015-01-30 13:41:28 -0600 |
|---|---|---|
| committer | Bai Ping <b51503@freescale.com> | 2015-02-11 18:46:41 +0800 |
| commit | 1794fd3c6a2586279a80d1aa580981cdc492ac38 (patch) | |
| tree | facd52d705abeb4f9261375179c90b94138fcb72 | |
| parent | eb98c3e690ea59da9b5c278fdfb9b96cade4a80c (diff) | |
MLK-9961-5 cpufreq:imx6x: Change PLL1 clock management.
Add support to leave PLL1 enabled since its required whenever ARM-PODF is
changed. With this patch PLL1 is set to bypassed mode (and enabled) whenever
ARM is sourced from step_clk.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
| -rw-r--r-- | drivers/cpufreq/imx6q-cpufreq.c | 25 |
1 files changed, 22 insertions, 3 deletions
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c index d16eeace746e..601326ca6408 100644 --- a/drivers/cpufreq/imx6q-cpufreq.c +++ b/drivers/cpufreq/imx6q-cpufreq.c @@ -32,6 +32,9 @@ static struct clk *pll1_sys_clk; static struct clk *pll1_sw_clk; static struct clk *step_clk; static struct clk *pll2_pfd2_396m_clk; +static struct clk *pll1_bypass; +static struct clk *pll1_bypass_src; +static struct clk *pll1; static struct device *cpu_dev; static struct cpufreq_frequency_table *freq_table; @@ -115,9 +118,19 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) clk_set_parent(step_clk, pll2_pfd2_396m_clk); clk_set_parent(pll1_sw_clk, step_clk); if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) { - clk_set_rate(pll1_sys_clk, new_freq * 1000); + clk_set_rate(pll1, new_freq * 1000); + /* + * Ensure pll1_bypass is set back to pll1. + */ + clk_set_parent(pll1_bypass, pll1); clk_set_parent(pll1_sw_clk, pll1_sys_clk); - } + } else + /* + * Need to ensure that PLL1 is bypassed and enabled + * before ARM-PODF is set. + */ + clk_set_parent(pll1_bypass, pll1_bypass_src); + /* Ensure the arm clock divider is what we expect */ ret = clk_set_rate(arm_clk, new_freq * 1000); @@ -253,8 +266,14 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw"); step_clk = devm_clk_get(cpu_dev, "step"); pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m"); + pll1_bypass = devm_clk_get(cpu_dev, "pll1_bypass"); + pll1 = devm_clk_get(cpu_dev, "pll1"); + pll1_bypass_src = devm_clk_get(cpu_dev, "pll1_bypass_src"); + if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) || - IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) { + IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk) || + IS_ERR(pll1_bypass) || IS_ERR(pll1) || + IS_ERR(pll1_bypass_src)) { dev_err(cpu_dev, "failed to get clocks\n"); ret = -ENOENT; goto put_node; |