diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2012-01-30 12:35:39 +0530 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-02-03 05:18:41 -0800 |
| commit | 13cc1a5d0c7e3f71eb36228f659a0c7cbe4b83f5 (patch) | |
| tree | 46f479ab49d502b16ee104d79aa6a6a7680bb168 | |
| parent | 3efb99cdbb351f014b7d521ede3a8988138ef231 (diff) | |
ARM: tegra: clock: Expand PLL usage restriction mechanism
Expand PLL usage restriction mechanism from Tegra3 only to common
tegra clock framework implementation: fail set parent API if new
parent is not allowed per usage policy.
Actual usage policy is architecture dependent and exists now only
on Tegra3.
Reviewed-on: http://git-master/r/77251
Change-Id: I2a8d60cc0ddfd2179961ef50418b193f2e1829c8
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78029
Reviewed-by: Automatic_Commit_Validation_User
| -rw-r--r-- | arch/arm/mach-tegra/clock.c | 5 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/clock.h | 6 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 6 |
3 files changed, 12 insertions, 5 deletions
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 0e650d7c85f9..f31da0bf1494 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -345,6 +345,11 @@ int clk_set_parent_locked(struct clk *c, struct clk *parent) goto out; } + if (!tegra_clk_is_parent_allowed(c, parent)) { + ret = -EINVAL; + goto out; + } + new_rate = clk_predict_rate_from_parent(c, parent); old_rate = clk_get_rate_locked(c); diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h index b47821e12274..36ca521fd2ce 100644 --- a/arch/arm/mach-tegra/clock.h +++ b/arch/arm/mach-tegra/clock.h @@ -247,6 +247,12 @@ int tegra_emc_set_rate(unsigned long rate); long tegra_emc_round_rate(unsigned long rate); struct clk *tegra_emc_predict_parent(unsigned long rate, u32 *div_value); void tegra_emc_timing_invalidate(void); +#ifdef CONFIG_ARCH_TEGRA_2x_SOC +static inline bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p) +{ return true; } +#else +bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p); +#endif static inline bool clk_is_auto_dvfs(struct clk *c) { diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 1298540c7d91..06335a7479d7 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -311,7 +311,6 @@ /* Threshold to engage CPU clock skipper during CPU rate change */ #define SKIPPER_ENGAGE_RATE 800000000 -static bool tegra3_clk_is_parent_allowed(struct clk *c, struct clk *p); static void tegra3_pllp_init_dependencies(unsigned long pllp_rate); static int tegra3_clk_shared_bus_update(struct clk *bus); @@ -2221,9 +2220,6 @@ static int tegra3_periph_clk_set_parent(struct clk *c, struct clk *p) if (!(c->flags & MUX)) return (p == c->parent) ? 0 : (-EINVAL); - if (!tegra3_clk_is_parent_allowed(c, p)) - return -EINVAL; - for (sel = c->inputs; sel->input != NULL; sel++) { if (sel->input == p) { val = clk_readl(c->reg); @@ -4493,7 +4489,7 @@ static void tegra3_pllp_init_dependencies(unsigned long pllp_rate) cpu_stay_on_backup_max = min(cpu_stay_on_backup_max, backup_rate); } -static bool tegra3_clk_is_parent_allowed(struct clk *c, struct clk *p) +bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p) { if (c->flags & PERIPH_ON_CBUS) return p != &tegra_pll_m; |