diff options
| author | Krishna Reddy <vdumpa@nvidia.com> | 2012-05-23 16:03:14 -0700 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-06-01 12:18:16 -0700 |
| commit | 4a014e2eb9109c7e1936ecb701de594a703712e1 (patch) | |
| tree | 4b9f27a854b03117f1a7e13f7f1129a00f6414af | |
| parent | eeb69dd3be1f25f0b51f72bf83564b5016ae3114 (diff) | |
arm: tegra: Enable config NVMAP_CACHE_MAINT_BY_SET_WAYS.
Change-Id: Ia6dccfbd0464bc088dfcb05cc16e7f2ad35a9783
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/104291
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/Kconfig | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 82306bc4aff5..441ce0964db1 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -24,6 +24,7 @@ config ARCH_TEGRA_2x_SOC select ARM_ERRATA_716044 select ARM_ERRATA_764369 if SMP select ARCH_HAS_SUSPEND_PAGETABLE + select NVMAP_CACHE_MAINT_BY_SET_WAYS help Support for NVIDIA Tegra AP20 and T20 processors, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller @@ -51,6 +52,7 @@ config ARCH_TEGRA_3x_SOC select TEGRA_LP2_ARM_TWD if HAVE_ARM_TWD && !TEGRA_RAIL_OFF_MULTIPLE_CPUS select CPA select ARCH_HAS_SUSPEND_PAGETABLE + select NVMAP_CACHE_MAINT_BY_SET_WAYS help Support for NVIDIA Tegra 3 family of SoCs, based upon the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller |