diff options
| author | Joseph Lehrer <jlehrer@nvidia.com> | 2011-06-22 13:58:28 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:48:00 -0800 |
| commit | 6bf73fb46cc8badcec1540da8ab5de9f06af97c3 (patch) | |
| tree | 9bdc81ac5f165e1e70f6b4098449c7e36a109a10 | |
| parent | d5506a49ce8b3e144375097d19494139488d15b5 (diff) | |
video: tegra: add 504MHz pll_d rate for HDMI
To support the 25.2MHz pixel clock frequency required for CEA-861-B format 1: 640x480p at 59.94Hz
bug 837571
(cherry picked from commit d03e629f3f428d0666a559e8a5c5f94419107ad3)
Original-Change-Id: I4f12b9333f31a2df6b1029acf5faffb7802f170c
Reviewed-on: http://git-master/r/40380
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Re7907dc7bb4b61cd1af284a722a2b208d34e4687
| -rw-r--r-- | drivers/video/tegra/dc/dc.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c index 6926b7bc2a0c..9910ef238373 100644 --- a/drivers/video/tegra/dc/dc.c +++ b/drivers/video/tegra/dc/dc.c @@ -1090,10 +1090,14 @@ void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk) clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0"); struct clk *base_clk = clk_get_parent(parent_clk); + /* needs to match tegra_dc_hdmi_supported_modes[] + and tegra_pll_d_freq_table[] */ if (dc->mode.pclk > 70000000) rate = 594000000; - else + else if (dc->mode.pclk > 25200000) rate = 216000000; + else + rate = 504000000; if (rate != clk_get_rate(base_clk)) clk_set_rate(base_clk, rate); |