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authorDan Williams <dan.j.williams@intel.com>2011-07-02 22:56:22 -0700
committerDan Williams <dan.j.williams@intel.com>2011-07-02 22:56:22 -0700
commit6f231dda68080759f1aed3769896e94c73099f0f (patch)
tree45b6ce02fa40e0e9c35526ac6c45950138387516
parent59c5f46fbe01a00eedf54a23789634438bb80603 (diff)
isci: Intel(R) C600 Series Chipset Storage Control Unit Driver
Support for the up to 2x4-port 6Gb/s SAS controllers embedded in the chipset. This is a snapshot of the first publicly available version of the driver, commit 4c1db2d0 in the 'historical' branch. git://git.kernel.org/pub/scm/linux/kernel/git/djbw/isci.git historical Signed-off-by: Maciej Trela <maciej.trela@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Edmund Nadolski <edmund.nadolski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
-rw-r--r--drivers/scsi/Kconfig34
-rw-r--r--drivers/scsi/Makefile1
-rw-r--r--drivers/scsi/isci/Makefile30
-rw-r--r--drivers/scsi/isci/core/intel_ata.h554
-rw-r--r--drivers/scsi/isci/core/intel_sas.h948
-rw-r--r--drivers/scsi/isci/core/intel_sat.h95
-rw-r--r--drivers/scsi/isci/core/intel_sata.h280
-rw-r--r--drivers/scsi/isci/core/intel_scsi.h474
-rw-r--r--drivers/scsi/isci/core/sati_device.h156
-rw-r--r--drivers/scsi/isci/core/sati_translator_sequence.h304
-rw-r--r--drivers/scsi/isci/core/sati_types.h145
-rw-r--r--drivers/scsi/isci/core/sci_base_controller.h306
-rw-r--r--drivers/scsi/isci/core/sci_base_memory_descriptor_list.c159
-rw-r--r--drivers/scsi/isci/core/sci_base_memory_descriptor_list.h155
-rw-r--r--drivers/scsi/isci/core/sci_base_phy.h205
-rw-r--r--drivers/scsi/isci/core/sci_base_port.h203
-rw-r--r--drivers/scsi/isci/core/sci_base_remote_device.h277
-rw-r--r--drivers/scsi/isci/core/sci_base_request.h195
-rw-r--r--drivers/scsi/isci/core/sci_base_state.h90
-rw-r--r--drivers/scsi/isci/core/sci_base_state_machine.c182
-rw-r--r--drivers/scsi/isci/core/sci_base_state_machine.h139
-rw-r--r--drivers/scsi/isci/core/sci_controller.h100
-rw-r--r--drivers/scsi/isci/core/sci_controller_constants.h215
-rw-r--r--drivers/scsi/isci/core/sci_memory_descriptor_list.h169
-rw-r--r--drivers/scsi/isci/core/sci_object.h99
-rw-r--r--drivers/scsi/isci/core/sci_pool.h199
-rw-r--r--drivers/scsi/isci/core/sci_status.h409
-rw-r--r--drivers/scsi/isci/core/sci_types.h88
-rw-r--r--drivers/scsi/isci/core/sci_util.c70
-rw-r--r--drivers/scsi/isci/core/sci_util.h138
-rw-r--r--drivers/scsi/isci/core/scic_config_parameters.h347
-rw-r--r--drivers/scsi/isci/core/scic_controller.h586
-rw-r--r--drivers/scsi/isci/core/scic_io_request.h512
-rw-r--r--drivers/scsi/isci/core/scic_phy.h303
-rw-r--r--drivers/scsi/isci/core/scic_port.h213
-rw-r--r--drivers/scsi/isci/core/scic_remote_device.h295
-rw-r--r--drivers/scsi/isci/core/scic_sds_controller.c4147
-rw-r--r--drivers/scsi/isci/core/scic_sds_controller.h706
-rw-r--r--drivers/scsi/isci/core/scic_sds_controller_registers.h463
-rw-r--r--drivers/scsi/isci/core/scic_sds_pci.h95
-rw-r--r--drivers/scsi/isci/core/scic_sds_phy.c2807
-rw-r--r--drivers/scsi/isci/core/scic_sds_phy.h491
-rw-r--r--drivers/scsi/isci/core/scic_sds_phy_registers.h187
-rw-r--r--drivers/scsi/isci/core/scic_sds_port.c2757
-rw-r--r--drivers/scsi/isci/core/scic_sds_port.h514
-rw-r--r--drivers/scsi/isci/core/scic_sds_port_configuration_agent.c851
-rw-r--r--drivers/scsi/isci/core/scic_sds_port_configuration_agent.h108
-rw-r--r--drivers/scsi/isci/core/scic_sds_port_registers.h223
-rw-r--r--drivers/scsi/isci/core/scic_sds_remote_device.c2252
-rw-r--r--drivers/scsi/isci/core/scic_sds_remote_device.h602
-rw-r--r--drivers/scsi/isci/core/scic_sds_remote_node_context.c1244
-rw-r--r--drivers/scsi/isci/core/scic_sds_remote_node_context.h342
-rw-r--r--drivers/scsi/isci/core/scic_sds_remote_node_table.c600
-rw-r--r--drivers/scsi/isci/core/scic_sds_remote_node_table.h196
-rw-r--r--drivers/scsi/isci/core/scic_sds_request.c2179
-rw-r--r--drivers/scsi/isci/core/scic_sds_request.h484
-rw-r--r--drivers/scsi/isci/core/scic_sds_smp_remote_device.c410
-rw-r--r--drivers/scsi/isci/core/scic_sds_smp_request.c669
-rw-r--r--drivers/scsi/isci/core/scic_sds_smp_request.h70
-rw-r--r--drivers/scsi/isci/core/scic_sds_ssp_request.c340
-rw-r--r--drivers/scsi/isci/core/scic_sds_stp_packet_request.c838
-rw-r--r--drivers/scsi/isci/core/scic_sds_stp_packet_request.h154
-rw-r--r--drivers/scsi/isci/core/scic_sds_stp_pio_request.h116
-rw-r--r--drivers/scsi/isci/core/scic_sds_stp_remote_device.c975
-rw-r--r--drivers/scsi/isci/core/scic_sds_stp_request.c2004
-rw-r--r--drivers/scsi/isci/core/scic_sds_stp_request.h221
-rw-r--r--drivers/scsi/isci/core/scic_sds_unsolicited_frame_control.c379
-rw-r--r--drivers/scsi/isci/core/scic_sds_unsolicited_frame_control.h286
-rw-r--r--drivers/scsi/isci/core/scic_task_request.h148
-rw-r--r--drivers/scsi/isci/core/scic_user_callback.h740
-rw-r--r--drivers/scsi/isci/core/scu_completion_codes.h280
-rw-r--r--drivers/scsi/isci/core/scu_constants.h151
-rw-r--r--drivers/scsi/isci/core/scu_event_codes.h336
-rw-r--r--drivers/scsi/isci/core/scu_registers.h1824
-rw-r--r--drivers/scsi/isci/core/scu_remote_node_context.h230
-rw-r--r--drivers/scsi/isci/core/scu_task_context.h943
-rw-r--r--drivers/scsi/isci/core/scu_unsolicited_frame.h117
-rw-r--r--drivers/scsi/isci/core/scu_viit_data.h179
-rw-r--r--drivers/scsi/isci/deprecated.c491
-rw-r--r--drivers/scsi/isci/events.c619
-rw-r--r--drivers/scsi/isci/firmware/Makefile19
-rw-r--r--drivers/scsi/isci/firmware/README36
-rw-r--r--drivers/scsi/isci/firmware/create_fw.c177
-rw-r--r--drivers/scsi/isci/host.c781
-rw-r--r--drivers/scsi/isci/host.h283
-rw-r--r--drivers/scsi/isci/init.c613
-rw-r--r--drivers/scsi/isci/isci.h138
-rw-r--r--drivers/scsi/isci/phy.c179
-rw-r--r--drivers/scsi/isci/phy.h104
-rw-r--r--drivers/scsi/isci/port.c484
-rw-r--r--drivers/scsi/isci/port.h153
-rw-r--r--drivers/scsi/isci/remote_device.c698
-rw-r--r--drivers/scsi/isci/remote_device.h154
-rw-r--r--drivers/scsi/isci/request.c1472
-rw-r--r--drivers/scsi/isci/request.h429
-rw-r--r--drivers/scsi/isci/sata.c356
-rw-r--r--drivers/scsi/isci/sata.h83
-rw-r--r--drivers/scsi/isci/sci_environment.h112
-rw-r--r--drivers/scsi/isci/task.c1691
-rw-r--r--drivers/scsi/isci/task.h368
-rw-r--r--drivers/scsi/isci/timers.c319
-rw-r--r--drivers/scsi/isci/timers.h126
-rw-r--r--firmware/Makefile1
-rw-r--r--firmware/isci/isci_firmware.bin.ihex11
104 files changed, 51230 insertions, 0 deletions
diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig
index 4a1f029c4fe9..3aa664fa892e 100644
--- a/drivers/scsi/Kconfig
+++ b/drivers/scsi/Kconfig
@@ -830,6 +830,40 @@ config SCSI_GDTH
To compile this driver as a module, choose M here: the
module will be called gdth.
+config SCSI_ISCI
+ tristate "Intel(R) C600 Series Chipset SAS Controller"
+ depends on PCI && SCSI
+ # little endian host assumptions
+ depends on X86
+ # (temporary): dma api misuse
+ depends on !DMAR
+ # (temporary): known alpha quality driver
+ depends on EXPERIMENTAL
+ select SCSI_SAS_LIBSAS
+ ---help---
+ This driver supports the 6Gb/s SAS capabilities of the storage
+ control unit found in the Intel(R) C600 series chipset.
+
+ The experimental tag will be removed after the driver exits alpha
+
+choice
+ prompt "Default Silicon Revision"
+ depends on SCSI_ISCI
+ default PBG_HBA_A2
+ # temporary A-step silicon is pre-production
+
+config PBG_HBA_BETA
+ bool "B0"
+
+config PBG_HBA_A2
+ bool "A2"
+
+config PBG_HBA_A0
+ bool "A0"
+
+endchoice
+
+
config SCSI_GENERIC_NCR5380
tristate "Generic NCR5380/53c400 SCSI PIO support"
depends on ISA && SCSI
diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile
index 7ad0b8a79ae8..3c08f5352b2d 100644
--- a/drivers/scsi/Makefile
+++ b/drivers/scsi/Makefile
@@ -73,6 +73,7 @@ obj-$(CONFIG_SCSI_AACRAID) += aacraid/
obj-$(CONFIG_SCSI_AIC7XXX_OLD) += aic7xxx_old.o
obj-$(CONFIG_SCSI_AIC94XX) += aic94xx/
obj-$(CONFIG_SCSI_PM8001) += pm8001/
+obj-$(CONFIG_SCSI_ISCI) += isci/
obj-$(CONFIG_SCSI_IPS) += ips.o
obj-$(CONFIG_SCSI_FD_MCS) += fd_mcs.o
obj-$(CONFIG_SCSI_FUTURE_DOMAIN)+= fdomain.o
diff --git a/drivers/scsi/isci/Makefile b/drivers/scsi/isci/Makefile
new file mode 100644
index 000000000000..34f7af3525f4
--- /dev/null
+++ b/drivers/scsi/isci/Makefile
@@ -0,0 +1,30 @@
+#TODO kill SCIC_SDS_4_ENABLED it is always true for this
+#generation of silicon
+EXTRA_CFLAGS += -DSCIC_SDS_4_ENABLED
+
+#temporary until atapi support ready
+EXTRA_CFLAGS += -DDISABLE_ATAPI
+
+EXTRA_CFLAGS += -Idrivers/scsi/isci/core/ -Idrivers/scsi/isci/
+obj-$(CONFIG_SCSI_ISCI) += isci.o
+isci-objs := init.o phy.o request.o sata.o \
+ remote_device.o port.o timers.o deprecated.o \
+ host.o task.o events.o \
+ core/scic_sds_controller.o \
+ core/scic_sds_remote_device.o \
+ core/scic_sds_request.o \
+ core/scic_sds_stp_request.o \
+ core/scic_sds_stp_packet_request.o \
+ core/scic_sds_stp_remote_device.o \
+ core/scic_sds_port.o \
+ core/scic_sds_port_configuration_agent.o \
+ core/scic_sds_phy.o \
+ core/scic_sds_ssp_request.o \
+ core/scic_sds_remote_node_context.o \
+ core/scic_sds_smp_request.o \
+ core/scic_sds_smp_remote_device.o \
+ core/scic_sds_remote_node_table.o \
+ core/scic_sds_unsolicited_frame_control.o \
+ core/sci_base_memory_descriptor_list.o \
+ core/sci_base_state_machine.o \
+ core/sci_util.o
diff --git a/drivers/scsi/isci/core/intel_ata.h b/drivers/scsi/isci/core/intel_ata.h
new file mode 100644
index 000000000000..48b297e50bd0
--- /dev/null
+++ b/drivers/scsi/isci/core/intel_ata.h
@@ -0,0 +1,554 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * This file defines all of the ATA related constants, enumerations, and types.
+ * Please note that this file does not necessarily contain an exhaustive
+ * list of all constants, commands, sub-commands, etc.
+ *
+ *
+ */
+
+#ifndef _ATA_H_
+#define _ATA_H_
+
+#include <linux/types.h>
+
+/**
+ *
+ *
+ * ATA_COMMAND_CODES These constants depict the various ATA command codes
+ * defined in the ATA/ATAPI specification.
+ */
+#define ATA_IDENTIFY_DEVICE 0xEC
+#define ATA_CHECK_POWER_MODE 0xE5
+#define ATA_STANDBY 0xE2
+#define ATA_STANDBY_IMMED 0xE0
+#define ATA_IDLE_IMMED 0xE1
+#define ATA_IDLE 0xE3
+#define ATA_FLUSH_CACHE 0xE7
+#define ATA_FLUSH_CACHE_EXT 0xEA
+#define ATA_READ_DMA_EXT 0x25
+#define ATA_READ_DMA 0xC8
+#define ATA_READ_SECTORS_EXT 0x24
+#define ATA_READ_SECTORS 0x20
+#define ATA_WRITE_DMA_EXT 0x35
+#define ATA_WRITE_DMA 0xCA
+#define ATA_WRITE_SECTORS_EXT 0x34
+#define ATA_WRITE_SECTORS 0x30
+#define ATA_WRITE_UNCORRECTABLE 0x45
+#define ATA_READ_VERIFY_SECTORS 0x40
+#define ATA_READ_VERIFY_SECTORS_EXT 0x42
+#define ATA_READ_BUFFER 0xE4
+#define ATA_WRITE_BUFFER 0xE8
+#define ATA_EXECUTE_DEVICE_DIAG 0x90
+#define ATA_SET_FEATURES 0xEF
+#define ATA_SMART 0xB0
+#define ATA_PACKET_IDENTIFY 0xA1
+#define ATA_PACKET 0xA0
+#define ATA_READ_FPDMA 0x60
+#define ATA_WRITE_FPDMA 0x61
+#define ATA_READ_LOG_EXT 0x2F
+#define ATA_NOP 0x00
+#define ATA_DEVICE_RESET 0x08
+#define ATA_MEDIA_EJECT 0xED
+
+/**
+ *
+ *
+ * ATA_SMART_SUB_COMMAND_CODES These constants define the ATA SMART command
+ * sub-codes that can be executed.
+ */
+#define ATA_SMART_SUB_CMD_ENABLE 0xD8
+#define ATA_SMART_SUB_CMD_DISABLE 0xD9
+#define ATA_SMART_SUB_CMD_RETURN_STATUS 0xDA
+#define ATA_SMART_SUB_CMD_READ_LOG 0xD5
+
+/**
+ *
+ *
+ * ATA_SET_FEATURES_SUB_COMMAND_CODES These constants define the ATA SET
+ * FEATURES command sub-codes that can be executed.
+ */
+#define ATA_SET_FEATURES_SUB_CMD_ENABLE_CACHE 0x02
+#define ATA_SET_FEATURES_SUB_CMD_DISABLE_CACHE 0x82
+#define ATA_SET_FEATURES_SUB_CMD_DISABLE_READ_AHEAD 0x55
+#define ATA_SET_FEATURES_SUB_CMD_ENABLE_READ_AHEAD 0xAA
+#define ATA_SET_FEATURES_SUB_CMD_SET_TRANSFER_MODE 0x3
+
+/**
+ *
+ *
+ * ATA_READ_LOG_EXT_PAGE_CODES This is a list of log page codes available for
+ * use.
+ */
+#define ATA_LOG_PAGE_NCQ_ERROR 0x10
+#define ATA_LOG_PAGE_SMART_SELF_TEST 0x06
+#define ATA_LOG_PAGE_EXTENDED_SMART_SELF_TEST 0x07
+
+/**
+ *
+ *
+ * ATA_LOG_PAGE_NCQ_ERROR_CONSTANTS These constants define standard values for
+ * use when requesting the NCQ error log page.
+ */
+#define ATA_LOG_PAGE_NCQ_ERROR_SECTOR 0
+#define ATA_LOG_PAGE_NCQ_ERROR_SECTOR_COUNT 1
+
+/**
+ *
+ *
+ * ATA_STATUS_REGISTER_BITS The following are status register bit definitions
+ * per ATA/ATAPI-7.
+ */
+#define ATA_STATUS_REG_BSY_BIT 0x80
+#define ATA_STATUS_REG_DEVICE_FAULT_BIT 0x20
+#define ATA_STATUS_REG_ERROR_BIT 0x01
+
+/**
+ *
+ *
+ * ATA_ERROR_REGISTER_BITS The following are error register bit definitions per
+ * ATA/ATAPI-7.
+ */
+#define ATA_ERROR_REG_NO_MEDIA_BIT 0x02
+#define ATA_ERROR_REG_ABORT_BIT 0x04
+#define ATA_ERROR_REG_MEDIA_CHANGE_REQUEST_BIT 0x08
+#define ATA_ERROR_REG_ID_NOT_FOUND_BIT 0x10
+#define ATA_ERROR_REG_MEDIA_CHANGE_BIT 0x20
+#define ATA_ERROR_REG_UNCORRECTABLE_BIT 0x40
+#define ATA_ERROR_REG_WRITE_PROTECTED_BIT 0x40
+#define ATA_ERROR_REG_ICRC_BIT 0x80
+
+/**
+ *
+ *
+ * ATA_CONTROL_REGISTER_BITS The following are control register bit definitions
+ * per ATA/ATAPI-7
+ */
+#define ATA_CONTROL_REG_INTERRUPT_ENABLE_BIT 0x02
+#define ATA_CONTROL_REG_SOFT_RESET_BIT 0x04
+#define ATA_CONTROL_REG_HIGH_ORDER_BYTE_BIT 0x80
+
+/**
+ *
+ *
+ * ATA_DEVICE_HEAD_REGISTER_BITS The following are device/head register bit
+ * definitions per ATA/ATAPI-7.
+ */
+#define ATA_DEV_HEAD_REG_LBA_MODE_ENABLE 0x40
+#define ATA_DEV_HEAD_REG_FUA_ENABLE 0x80
+
+/**
+ *
+ *
+ * ATA_IDENTIFY_DEVICE_FIELD_LENGTHS The following constants define the number
+ * of bytes contained in various fields found in the IDENTIFY DEVICE data
+ * structure.
+ */
+#define ATA_IDENTIFY_SERIAL_NUMBER_LEN 20
+#define ATA_IDENTIFY_MODEL_NUMBER_LEN 40
+#define ATA_IDENTIFY_FW_REVISION_LEN 8
+#define ATA_IDENTIFY_48_LBA_LEN 8
+#define ATA_IDENTIFY_MEDIA_SERIAL_NUMBER_LEN 30
+#define ATA_IDENTIFY_WWN_LEN 8
+
+/**
+ *
+ *
+ * ATA_IDENTIFY_DEVICE_FIELD_MASKS The following constants define bit masks
+ * utilized to determine if a feature is supported/enabled or if a bit is
+ * simply set inside of the IDENTIFY DEVICE data structre.
+ */
+#define ATA_IDENTIFY_REMOVABLE_MEDIA_ENABLE 0x0080
+#define ATA_IDENTIFY_CAPABILITIES1_NORMAL_DMA_ENABLE 0x0100
+#define ATA_IDENTIFY_CAPABILITIES1_STANDBY_ENABLE 0x2000
+#define ATA_IDENTIFY_COMMAND_SET_SUPPORTED0_SMART_ENABLE 0x0001
+#define ATA_IDENTIFY_COMMAND_SET_SUPPORTED1_48BIT_ENABLE 0x0400
+#define ATA_IDENTIFY_COMMAND_SET_WWN_SUPPORT_ENABLE 0x0100
+#define ATA_IDENTIFY_COMMAND_SET_ENABLED0_SMART_ENABLE 0x0001
+#define ATA_IDENTIFY_SATA_CAPABILITIES_NCQ_ENABLE 0x0100
+#define ATA_IDENTIFY_NCQ_QUEUE_DEPTH_ENABLE 0x001F
+#define ATA_IDENTIFY_SECTOR_LARGER_THEN_512_ENABLE 0x0100
+#define ATA_IDENTIFY_LOGICAL_SECTOR_PER_PHYSICAL_SECTOR_MASK 0x000F
+#define ATA_IDENTIFY_LOGICAL_SECTOR_PER_PHYSICAL_SECTOR_ENABLE 0x2000
+#define ATA_IDENTIFY_WRITE_UNCORRECTABLE_SUPPORT 0x0004
+#define ATA_IDENTIFY_COMMAND_SET_SMART_SELF_TEST_SUPPORTED 0x0002
+
+/**
+ *
+ *
+ * ATAPI_IDENTIFY_DEVICE_FIELD_MASKS These constants define the various bit
+ * definitions for the fields in the PACKET IDENTIFY DEVICE data structure.
+ */
+#define ATAPI_IDENTIFY_16BYTE_CMD_PCKT_ENABLE 0x01
+
+/**
+ *
+ *
+ * ATA_PACKET_FEATURE_BITS These constants define the various bit definitions
+ * for the ATA PACKET feature register.
+ */
+#define ATA_PACKET_FEATURE_DMA 0x01
+#define ATA_PACKET_FEATURE_OVL 0x02
+#define ATA_PACKET_FEATURE_DMADIR 0x04
+
+/**
+ *
+ *
+ * ATA_Device_Power_Mode_Values These constants define the power mode values
+ * returned by ATA_Check_Power_Mode
+ */
+#define ATA_STANDBY_POWER_MODE 0x00
+#define ATA_IDLE_POWER_MODE 0x80
+#define ATA_ACTIVE_POWER_MODE 0xFF
+
+/**
+ *
+ *
+ * ATA_WRITE_UNCORRECTIABLE feature field values These constants define the
+ * Write Uncorrectable feature values used with the SATI translation.
+ */
+#define ATA_WRITE_UNCORRECTABLE_PSUEDO 0x55
+#define ATA_WRITE_UNCORRECTABLE_FLAGGED 0xAA
+
+
+
+/**
+ * struct ATA_IDENTIFY_DEVICE - This structure depicts the ATA IDENTIFY DEVICE
+ * data format.
+ *
+ *
+ */
+struct ata_identify_device_data {
+ u16 general_config_bits; /* word 00 */
+ u16 obsolete0; /* word 01 (num cylinders) */
+ u16 vendor_specific_config_bits; /* word 02 */
+ u16 obsolete1; /* word 03 (num heads) */
+ u16 retired1[2]; /* words 04-05 */
+ u16 obsolete2; /* word 06 (sectors / track) */
+ u16 reserved_for_compact_flash1[2]; /* words 07-08 */
+ u16 retired0; /* word 09 */
+ u8 serial_number[ATA_IDENTIFY_SERIAL_NUMBER_LEN]; /* word 10-19 */
+ u16 retired2[2]; /* words 20-21 */
+ u16 obsolete4; /* word 22 */
+ u8 firmware_revision[ATA_IDENTIFY_FW_REVISION_LEN]; /* words 23-26 */
+ u8 model_number[ATA_IDENTIFY_MODEL_NUMBER_LEN]; /* words 27-46 */
+ u16 max_sectors_per_multiple; /* word 47 */
+ u16 reserved0; /* word 48 */
+ u16 capabilities1; /* word 49 */
+ u16 capabilities2; /* word 50 */
+ u16 obsolete5[2]; /* words 51-52 */
+ u16 validity_bits; /* word 53 */
+ u16 obsolete6[5]; /*
+ * words 54-58 Used to be:
+ * current cylinders,
+ * current heads,
+ * current sectors/Track,
+ * current capacity */
+ u16 current_max_sectors_per_multiple; /* word 59 */
+ u8 total_num_sectors[4]; /* words 60-61 */
+ u16 obsolete7; /* word 62 */
+ u16 multi_word_dma_mode; /* word 63 */
+ u16 pio_modes_supported; /* word 64 */
+ u16 min_multiword_dma_transfer_cycle; /* word 65 */
+ u16 rec_min_multiword_dma_transfer_cycle; /* word 66 */
+ u16 min_pio_transfer_no_flow_ctrl; /* word 67 */
+ u16 min_pio_transfer_with_flow_ctrl; /* word 68 */
+ u16 reserved1[2]; /* words 69-70 */
+ u16 reserved2[4]; /* words 71-74 */
+ u16 queue_depth; /* word 75 */
+ u16 serial_ata_capabilities; /* word 76 */
+ u16 serial_ata_reserved; /* word 77 */
+ u16 serial_ata_features_supported; /* word 78 */
+ u16 serial_ata_features_enabled; /* word 79 */
+ u16 major_version_number; /* word 80 */
+ u16 minor_version_number; /* word 81 */
+ u16 command_set_supported0; /* word 82 */
+ u16 command_set_supported1; /* word 83 */
+ u16 command_set_supported_extention; /* word 84 */
+ u16 command_set_enabled0; /* word 85 */
+ u16 command_set_enabled1; /* word 86 */
+ u16 command_set_default; /* word 87 */
+ u16 ultra_dma_mode; /* word 88 */
+ u16 security_erase_completion_time; /* word 89 */
+ u16 enhanced_security_erase_time; /* word 90 */
+ u16 current_power_mgmt_value; /* word 91 */
+ u16 master_password_revision; /* word 92 */
+ u16 hardware_reset_result; /* word 93 */
+ u16 current_acoustic_management_value; /* word 94 */
+ u16 stream_min_request_size; /* word 95 */
+ u16 stream_transfer_time; /* word 96 */
+ u16 stream_access_latency; /* word 97 */
+ u16 stream_performance_granularity[2]; /* words 98-99 */
+ u8 max_48bit_lba[ATA_IDENTIFY_48_LBA_LEN]; /* words 100-103 */
+ u16 streaming_transfer_time; /* word 104 */
+ u16 reserved3; /* word 105 */
+ u16 physical_logical_sector_info; /* word 106 */
+ u16 acoustic_test_interseek_delay; /* word 107 */
+ u8 world_wide_name[ATA_IDENTIFY_WWN_LEN]; /* words 108-111 */
+ u8 reserved_for_wwn_extention[ATA_IDENTIFY_WWN_LEN]; /* words 112-115 */
+ u16 reserved4; /* word 116 */
+ u8 words_per_logical_sector[4]; /* words 117-118 */
+ u16 command_set_supported2; /* word 119 */
+ u16 reserved5[7]; /* words 120-126 */
+ u16 removable_media_status; /* word 127 */
+ u16 security_status; /* word 128 */
+ u16 vendor_specific1[31]; /* words 129-159 */
+ u16 cfa_power_mode1; /* word 160 */
+ u16 reserved_for_compact_flash2[7]; /* words 161-167 */
+ u16 device_nominal_form_factor; /* word 168 */
+ u16 reserved_for_compact_flash3[7]; /* words 169-175 */
+ u16 current_media_serial_number[ATA_IDENTIFY_MEDIA_SERIAL_NUMBER_LEN]; /* words 176-205 */
+ u16 reserved6[3]; /* words 206-208 */
+ u16 logical_sector_alignment; /* words 209 */
+ u16 reserved7[7]; /* words 210-216 */
+ u16 nominal_media_rotation_rate; /* word 217 */
+ u16 reserved8[37]; /* words 218-254 */
+ u16 integrity_word; /* word 255 */
+
+};
+
+#define ATA_IDENTIFY_DEVICE_GET_OFFSET(field_name) \
+ ((unsigned long)&(((struct ata_identify_device_data *)0)->field_name))
+#define ATA_IDENTIFY_DEVICE_WCE_ENABLE 0x20
+#define ATA_IDENTIFY_DEVICE_RA_ENABLE 0x40
+
+/**
+ * struct ATAPI_IDENTIFY_PACKET_DATA - The following structure depicts the
+ * ATA-ATAPI 7 version of the IDENTIFY PACKET DEVICE data structure.
+ *
+ *
+ */
+struct atapi_identify_packet_device {
+ u16 generalConfigBits; /* word 00 */
+ u16 reserved0; /* word 01 (num cylinders) */
+ u16 uniqueConfigBits; /* word 02 */
+ u16 reserved1[7]; /* words 03 - 09 */
+ u8 serialNumber[ATA_IDENTIFY_SERIAL_NUMBER_LEN]; /* word 10-19 */
+ u16 reserved2[3]; /* words 20-22 */
+ u8 firmwareRevision[ATA_IDENTIFY_FW_REVISION_LEN]; /* words 23-26 */
+ u8 modelNumber[ATA_IDENTIFY_MODEL_NUMBER_LEN]; /* words 27-46 */
+ u16 reserved4[2]; /* words 47-48 */
+ u16 capabilities1; /* word 49 */
+ u16 capabilities2; /* word 50 */
+ u16 obsolete0[2]; /* words 51-52 */
+ u16 validityBits; /* word 53 */
+ u16 reserved[8]; /* words 54-61 */
+
+ u16 DMADIRBitRequired; /* word 62, page2 */
+ u16 multiWordDmaMode; /* word 63 */
+ u16 pioModesSupported; /* word 64 */
+ u16 minMultiwordDmaTransferCycle; /* word 65 */
+ u16 recMinMultiwordDmaTransferCycle; /* word 66 */
+ u16 minPioTransferNoFlowCtrl; /* word 67 */
+ u16 minPioTransferWithFlowCtrl; /* word 68 */
+ u16 reserved6[2]; /* words 69-70 */
+ u16 nsFromPACKETReceiptToBusRelease; /* word 71 */
+ u16 nsFromSERVICEReceiptToBSYreset; /* wore 72 */
+ u16 reserved7[2]; /* words 73-74 */
+ u16 queueDepth; /* word 75 */
+ u16 serialAtaCapabilities; /* word 76 */
+ u16 serialAtaReserved; /* word 77 */
+ u16 serialAtaFeaturesSupported; /* word 78 */
+ u16 serialAtaFeaturesEnabled; /* word 79 */
+
+ u16 majorVersionNumber; /* word 80, page3 */
+ u16 minorVersionNumber; /* word 81 */
+ u16 commandSetSupported0; /* word 82 */
+ u16 commandSetSupported1; /* word 83 */
+
+ u16 commandSetSupportedExtention; /* word 84, page4 */
+ u16 commandSetEnabled0; /* word 85 */
+ u16 commandSetEnabled1; /* word 86 */
+ u16 commandSetDefault; /* word 87 */
+
+ u16 ultraDmaMode; /* word 88, page5 */
+ u16 reserved8[4]; /* words 89 - 92 */
+
+ u16 hardwareResetResult; /* word 93, page6 */
+ u16 currentAcousticManagementValue; /* word 94 */
+ u16 reserved9[30]; /* words 95-124 */
+ u16 ATAPIByteCount0Behavior; /* word 125 */
+ u16 obsolete1; /* word 126 */
+ u16 removableMediaStatus; /* word 127, */
+
+ u16 securityStatus; /* word 128, page7 */
+ u16 vendorSpecific1[31]; /* words 129-159 */
+ u16 reservedForCompactFlash[16]; /* words 160-175 */
+ u16 reserved10[79]; /* words 176-254 */
+ u16 integrityWord; /* word 255 */
+};
+
+/**
+ * struct ata_extended_smart_self_test_log - The following structure depicts
+ * the ATA-8 version of the Extended SMART self test log page descriptor
+ * entry.
+ *
+ *
+ */
+union ata_descriptor_entry {
+ struct DESCRIPTOR_ENTRY {
+ u8 lba_field;
+ u8 status_byte;
+ u8 time_stamp_low;
+ u8 time_stamp_high;
+ u8 checkpoint_byte;
+ u8 failing_lba_low;
+ u8 failing_lba_mid;
+ u8 failing_lba_high;
+ u8 failing_lba_low_ext;
+ u8 failing_lba_mid_ext;
+ u8 failing_lba_high_ext;
+
+ u8 vendor_specific1;
+ u8 vendor_specific2;
+ u8 vendor_specific3;
+ u8 vendor_specific4;
+ u8 vendor_specific5;
+ u8 vendor_specific6;
+ u8 vendor_specific7;
+ u8 vendor_specific8;
+ u8 vendor_specific9;
+ u8 vendor_specific10;
+ u8 vendor_specific11;
+ u8 vendor_specific12;
+ u8 vendor_specific13;
+ u8 vendor_specific14;
+ u8 vendor_specific15;
+ } DESCRIPTOR_ENTRY;
+
+ u8 descriptor_entry[26];
+
+};
+
+/**
+ * struct ata_extended_smart_self_test_log - The following structure depicts
+ * the ATA-8 version of the SMART self test log page descriptor entry.
+ *
+ *
+ */
+union ata_smart_descriptor_entry {
+ struct SMART_DESCRIPTOR_ENTRY {
+ u8 lba_field;
+ u8 status_byte;
+ u8 time_stamp_low;
+ u8 time_stamp_high;
+ u8 checkpoint_byte;
+ u8 failing_lba_low;
+ u8 failing_lba_mid;
+ u8 failing_lba_high;
+ u8 failing_lba_low_ext;
+
+ u8 vendor_specific1;
+ u8 vendor_specific2;
+ u8 vendor_specific3;
+ u8 vendor_specific4;
+ u8 vendor_specific5;
+ u8 vendor_specific6;
+ u8 vendor_specific7;
+ u8 vendor_specific8;
+ u8 vendor_specific9;
+ u8 vendor_specific10;
+ u8 vendor_specific11;
+ u8 vendor_specific12;
+ u8 vendor_specific13;
+ u8 vendor_specific14;
+ u8 vendor_specific15;
+ } SMART_DESCRIPTOR_ENTRY;
+
+ u8 smart_descriptor_entry[24];
+
+};
+
+/**
+ * struct ata_extended_smart_self_test_log - The following structure depicts
+ * the ATA-8 version of the Extended SMART self test log page.
+ *
+ *
+ */
+struct ata_extended_smart_self_test_log {
+ u8 self_test_log_data_structure_revision_number; /* byte 0 */
+ u8 reserved0; /* byte 1 */
+ u8 self_test_descriptor_index[2]; /* byte 2-3 */
+
+ union ata_descriptor_entry descriptor_entrys[19]; /* bytes 4-497 */
+
+ u8 vendor_specific[2]; /* byte 498-499 */
+ u8 reserved1[11]; /* byte 500-510 */
+ u8 data_structure_checksum; /* byte 511 */
+
+};
+
+/**
+ * struct ata_extended_smart_self_test_log - The following structure depicts
+ * the ATA-8 version of the SMART self test log page.
+ *
+ *
+ */
+struct ata_smart_self_test_log {
+ u8 self_test_log_data_structure_revision_number[2]; /* bytes 0-1 */
+
+ union ata_smart_descriptor_entry descriptor_entrys[21]; /* bytes 2-505 */
+
+ u8 vendor_specific[2]; /* byte 506-507 */
+ u8 self_test_index; /* byte 508 */
+ u8 reserved1[2]; /* byte 509-510 */
+ u8 data_structure_checksum; /* byte 511 */
+
+};
+
+#endif /* _ATA_H_ */
+
diff --git a/drivers/scsi/isci/core/intel_sas.h b/drivers/scsi/isci/core/intel_sas.h
new file mode 100644
index 000000000000..eb9686ea35f1
--- /dev/null
+++ b/drivers/scsi/isci/core/intel_sas.h
@@ -0,0 +1,948 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _INTEL_SAS_H_
+#define _INTEL_SAS_H_
+
+/**
+ * This file contains all of the definitions relating to structures, constants,
+ * etc. defined by the SAS specification.
+ *
+ *
+ */
+
+#include "intel_sata.h"
+#include "intel_scsi.h"
+
+/**
+ * struct sci_sas_address - This structure depicts how a SAS address is
+ * represented by SCI.
+ *
+ *
+ */
+struct sci_sas_address {
+ /**
+ * This member contains the higher 32-bits of the SAS address.
+ */
+ u32 high;
+
+ /**
+ * This member contains the lower 32-bits of the SAS address.
+ */
+ u32 low;
+
+};
+
+/**
+ * struct sci_sas_identify_address_frame_protocols - This structure depicts the
+ * contents of bytes 2 and 3 in the SAS IDENTIFY ADDRESS FRAME (IAF).
+ *
+ * For specific information on each of these individual fields please reference
+ * the SAS specification Link layer section on address frames.
+ */
+struct sci_sas_identify_address_frame_protocols {
+ union {
+ struct {
+ u16 restricted1:1;
+ u16 smp_initiator:1;
+ u16 stp_initiator:1;
+ u16 ssp_initiator:1;
+ u16 reserved3:4;
+ u16 restricted2:1;
+ u16 smp_target:1;
+ u16 stp_target:1;
+ u16 ssp_target:1;
+ u16 reserved4:4;
+ } bits;
+
+ u16 all;
+ } u;
+
+};
+
+/**
+ * struct sci_sas_identify_address_frame - This structure depicts the contents
+ * of the SAS IDENTIFY ADDRESS FRAME (IAF).
+ *
+ * For specific information on each of these individual fields please reference
+ * the SAS specification Link layer section on address frames.
+ */
+struct sci_sas_identify_address_frame {
+ u16 address_frame_type:4;
+ u16 device_type:3;
+ u16 reserved1:1;
+ u16 reason:4;
+ u16 reserved2:4;
+
+ struct sci_sas_identify_address_frame_protocols protocols;
+
+ struct sci_sas_address device_name;
+ struct sci_sas_address sas_address;
+
+ u32 phy_identifier:8;
+ u32 break_reply_capable:1;
+ u32 requested_in_zpsds:1;
+ u32 in_zpsds_persistent:1;
+ u32 reserved5:21;
+
+ u32 reserved6[4];
+
+};
+
+/**
+ * struct sas_capabilities - This structure depicts the various SAS
+ * capabilities supported by the directly attached target device. For
+ * specific information on each of these individual fields please reference
+ * the SAS specification Phy layer section on speed negotiation windows.
+ *
+ *
+ */
+struct sas_capabilities {
+ union {
+#if defined (SCIC_SDS_4_ENABLED)
+ struct {
+ /**
+ * The SAS specification indicates the start bit shall always be set to
+ * 1. This implementation will have the start bit set to 0 if the
+ * PHY CAPABILITIES were either not received or speed negotiation failed.
+ */
+ u32 start:1;
+ u32 tx_ssc_type:1;
+ u32 reserved1:2;
+ u32 requested_logical_link_rate:4;
+
+ u32 gen1_without_ssc_supported:1;
+ u32 gen1_with_ssc_supported:1;
+ u32 gen2_without_ssc_supported:1;
+ u32 gen2_with_ssc_supported:1;
+ u32 gen3_without_ssc_supported:1;
+ u32 gen3_with_ssc_supported:1;
+ u32 reserved2:17;
+ u32 parity:1;
+ } bits;
+#endif /* (SCIC_SDS_4_ENABLED) */
+
+ u32 all;
+ } u;
+
+};
+
+/**
+ * enum _SCI_SAS_LINK_RATE - This enumeration depicts the SAS specification
+ * defined link speeds.
+ *
+ *
+ */
+enum sci_sas_link_rate {
+ SCI_SAS_NO_LINK_RATE = 0,
+ SCI_SATA_SPINUP_HOLD = 0x3,
+ SCI_SAS_150_GB = 0x8,
+ SCI_SAS_300_GB = 0x9,
+ SCI_SAS_600_GB = 0xA
+};
+
+/**
+ * enum _SCI_SAS_TASK_ATTRIBUTE - This enumeration depicts the SAM/SAS
+ * specification defined task attribute values for a command information
+ * unit.
+ *
+ *
+ */
+enum sci_sas_task_attribute {
+ SCI_SAS_SIMPLE_ATTRIBUTE = 0,
+ SCI_SAS_HEAD_OF_QUEUE_ATTRIBUTE = 1,
+ SCI_SAS_ORDERED_ATTRIBUTE = 2,
+ SCI_SAS_ACA_ATTRIBUTE = 4,
+};
+
+/**
+ * enum _SCI_SAS_TASK_MGMT_FUNCTION - This enumeration depicts the SAM/SAS
+ * specification defined task management functions.
+ *
+ * This HARD_RESET function listed here is not actually defined as a task
+ * management function in the industry standard.
+ */
+enum sci_sas_task_mgmt_function {
+ SCI_SAS_ABORT_TASK = SCSI_TASK_REQUEST_ABORT_TASK,
+ SCI_SAS_ABORT_TASK_SET = SCSI_TASK_REQUEST_ABORT_TASK_SET,
+ SCI_SAS_CLEAR_TASK_SET = SCSI_TASK_REQUEST_CLEAR_TASK_SET,
+ SCI_SAS_LOGICAL_UNIT_RESET = SCSI_TASK_REQUEST_LOGICAL_UNIT_RESET,
+ SCI_SAS_I_T_NEXUS_RESET = SCSI_TASK_REQUEST_I_T_NEXUS_RESET,
+ SCI_SAS_CLEAR_ACA = SCSI_TASK_REQUEST_CLEAR_ACA,
+ SCI_SAS_QUERY_TASK = SCSI_TASK_REQUEST_QUERY_TASK,
+ SCI_SAS_QUERY_TASK_SET = SCSI_TASK_REQUEST_QUERY_TASK_SET,
+ SCI_SAS_QUERY_ASYNCHRONOUS_EVENT = SCSI_TASK_REQUEST_QUERY_UNIT_ATTENTION,
+ SCI_SAS_HARD_RESET = 0xFF
+};
+
+
+/**
+ * enum _SCI_SAS_FRAME_TYPE - This enumeration depicts the SAS specification
+ * defined SSP frame types.
+ *
+ *
+ */
+enum sci_sas_frame_type {
+ SCI_SAS_DATA_FRAME = 0x01,
+ SCI_SAS_XFER_RDY_FRAME = 0x05,
+ SCI_SAS_COMMAND_FRAME = 0x06,
+ SCI_SAS_RESPONSE_FRAME = 0x07,
+ SCI_SAS_TASK_FRAME = 0x16
+};
+
+/**
+ * struct sci_ssp_command_iu - This structure depicts the contents of the SSP
+ * COMMAND INFORMATION UNIT. For specific information on each of these
+ * individual fields please reference the SAS specification SSP transport
+ * layer section.
+ *
+ *
+ */
+struct sci_ssp_command_iu {
+ u32 lun_upper;
+ u32 lun_lower;
+
+ u32 additional_cdb_length:6;
+ u32 reserved0:2;
+ u32 reserved1:8;
+ u32 enable_first_burst:1;
+ u32 task_priority:4;
+ u32 task_attribute:3;
+ u32 reserved2:8;
+
+ u32 cdb[4];
+
+};
+
+/**
+ * struct sci_ssp_task_iu - This structure depicts the contents of the SSP TASK
+ * INFORMATION UNIT. For specific information on each of these individual
+ * fields please reference the SAS specification SSP transport layer section.
+ *
+ *
+ */
+struct sci_ssp_task_iu {
+ u32 lun_upper;
+ u32 lun_lower;
+
+ u32 reserved0:8;
+ u32 task_function:8;
+ u32 reserved1:8;
+ u32 reserved2:8;
+
+ u32 reserved3:16;
+ u32 task_tag:16;
+
+ u32 reserved4[3];
+
+};
+
+#define SSP_RESPONSE_IU_MAX_DATA 64
+
+#define SCI_SSP_RESPONSE_IU_DATA_PRESENT_MASK (0x03)
+
+
+#define sci_ssp_get_sense_data_length(sense_data_length_buffer) \
+ SCIC_BUILD_DWORD(sense_data_length_buffer)
+
+#define sci_ssp_get_response_data_length(response_data_length_buffer) \
+ SCIC_BUILD_DWORD(response_data_length_buffer)
+
+/**
+ * struct sci_ssp_response_iu - This structure depicts the contents of the SSP
+ * RESPONSE INFORMATION UNIT. For specific information on each of these
+ * individual fields please reference the SAS specification SSP transport
+ * layer section.
+ *
+ *
+ */
+struct sci_ssp_response_iu {
+ u8 reserved0[8];
+
+ u8 retry_delay_timer[2];
+ u8 data_present;
+ u8 status;
+
+ u8 reserved1[4];
+ u8 sense_data_length[4];
+ u8 response_data_length[4];
+
+ u32 data[SSP_RESPONSE_IU_MAX_DATA];
+
+};
+
+/**
+ * enum _SCI_SAS_DATA_PRESENT_TYPE - This enumeration depicts the SAS
+ * specification defined SSP data present types in struct sci_ssp_response_iu.
+ *
+ *
+ */
+enum sci_ssp_response_iu_data_present_type {
+ SCI_SSP_RESPONSE_IU_NO_DATA = 0x00,
+ SCI_SSP_RESPONSE_IU_RESPONSE_DATA = 0x01,
+ SCI_SSP_RESPONSE_IU_SENSE_DATA = 0x02
+};
+
+/**
+ * struct sci_ssp_frame_header - This structure depicts the contents of an SSP
+ * frame header. For specific information on the individual fields please
+ * reference the SAS specification transport layer SSP frame format.
+ *
+ *
+ */
+struct sci_ssp_frame_header {
+ /* Word 0 */
+ u32 hashed_destination_address:24;
+ u32 frame_type:8;
+
+ /* Word 1 */
+ u32 hashed_source_address:24;
+ u32 reserved1_0:8;
+
+ /* Word 2 */
+ u32 reserved2_2:6;
+ u32 fill_bytes:2;
+ u32 reserved2_1:3;
+ u32 tlr_control:2;
+ u32 retry_data_frames:1;
+ u32 retransmit:1;
+ u32 changing_data_pointer:1;
+ u32 reserved2_0:16;
+
+ /* Word 3 */
+ u32 uiResv4;
+
+ /* Word 4 */
+ u16 target_port_transfer_tag;
+ u16 tag;
+
+ /* Word 5 */
+ u32 data_offset;
+
+};
+
+/**
+ * struct smp_request_header - This structure defines the contents of an SMP
+ * Request header.
+ *
+ * For specific information on each of these individual fields please reference
+ * the SAS specification.
+ */
+struct smp_request_header {
+ u8 smp_frame_type; /* byte 0 */
+ u8 function; /* byte 1 */
+ u8 allocated_response_length; /* byte 2 */
+ u8 request_length; /* byte 3 */
+};
+
+/**
+ * struct smp_response_header - This structure depicts the contents of the SAS
+ * SMP DISCOVER RESPONSE frame. For specific information on each of these
+ * individual fields please reference the SAS specification Link layer
+ * section on address frames.
+ *
+ *
+ */
+struct smp_response_header {
+ u8 smp_frame_type; /* byte 0 */
+ u8 function; /* byte 1 */
+ u8 function_result; /* byte 2 */
+ u8 response_length; /* byte 3 */
+};
+
+/**
+ * struct smp_request_general - This structure defines the contents of an SMP
+ * Request that is comprised of the struct smp_request_header and a CRC.
+ *
+ * For specific information on each of these individual fields please reference
+ * the SAS specification.
+ */
+struct smp_request_general {
+ u32 crc; /* bytes 4-7 */
+
+};
+
+/**
+ * struct smp_request_phy_identifier - This structure defines the contents of
+ * an SMP Request that is comprised of the struct smp_request_header and a phy
+ * identifier. Examples: SMP_REQUEST_DISCOVER, SMP_REQUEST_REPORT_PHY_SATA.
+ *
+ * For specific information on each of these individual fields please reference
+ * the SAS specification.
+ */
+struct smp_request_phy_identifier {
+ u32 reserved_byte4_7; /* bytes 4-7 */
+
+ u32 ignore_zone_group:1; /* byte 8 */
+ u32 reserved_byte8:7;
+
+ u32 phy_identifier:8; /* byte 9 */
+ u32 reserved_byte10:8; /* byte 10 */
+ u32 reserved_byte11:8; /* byte 11 */
+
+};
+
+/**
+ * struct smp_request_configure_route_information - This structure defines the
+ * contents of an SMP Configure Route Information request.
+ *
+ * For specific information on each of these individual fields please reference
+ * the SAS specification.
+ */
+struct smp_request_configure_route_information {
+ u32 expected_expander_change_count:16; /* bytes 4-5 */
+ u32 expander_route_index_high:8;
+ u32 expander_route_index:8; /* bytes 6-7 */
+
+ u32 reserved_byte8:8; /* bytes 8 */
+ u32 phy_identifier:8; /* bytes 9 */
+ u32 reserved_byte_10_11:16; /* bytes 10-11 */
+
+ u32 reserved_byte_12_bit_0_6:7;
+ u32 disable_route_entry:1; /* byte 12 */
+ u32 reserved_byte_13_15:24; /* bytes 13-15 */
+
+ u32 routed_sas_address[2]; /* bytes 16-23 */
+ u8 reserved_byte_24_39[16]; /* bytes 24-39 */
+
+};
+
+/**
+ * struct smp_request_phy_control - This structure defines the contents of an
+ * SMP Phy Controler request.
+ *
+ * For specific information on each of these individual fields please reference
+ * the SAS specification.
+ */
+struct smp_request_phy_control {
+ u16 expected_expander_change_count; /* byte 4-5 */
+
+ u16 reserved_byte_6_7; /* byte 6-7 */
+ u8 reserved_byte_8; /* byte 8 */
+
+ u8 phy_identifier; /* byte 9 */
+ u8 phy_operation; /* byte 10 */
+
+ u8 update_partial_pathway_timeout_value:1;
+ u8 reserved_byte_11_bit_1_7:7; /* byte 11 */
+
+ u8 reserved_byte_12_23[12]; /* byte 12-23 */
+
+ u8 attached_device_name[8]; /* byte 24-31 */
+
+ u8 reserved_byte_32_bit_3_0:4; /* byte 32 */
+ u8 programmed_minimum_physical_link_rate:4;
+
+ u8 reserved_byte_33_bit_3_0:4; /* byte 33 */
+ u8 programmed_maximum_physical_link_rate:4;
+
+ u16 reserved_byte_34_35; /* byte 34-35 */
+
+ u8 partial_pathway_timeout_value:4;
+ u8 reserved_byte_36_bit_4_7:4; /* byte 36 */
+
+ u16 reserved_byte_37_38; /* byte 37-38 */
+ u8 reserved_byte_39; /* byte 39 */
+
+};
+
+/**
+ * struct smp_request_vendor_specific - This structure depicts the vendor
+ * specific space for SMP request.
+ *
+ *
+ */
+ #define SMP_REQUEST_VENDOR_SPECIFIC_MAX_LENGTH 1016
+struct smp_request_vendor_specific {
+ u8 request_bytes[SMP_REQUEST_VENDOR_SPECIFIC_MAX_LENGTH];
+};
+
+/**
+ * struct smp_request - This structure simply unionizes the existing request
+ * structures into a common request type.
+ *
+ *
+ */
+struct smp_request {
+ struct smp_request_header header;
+
+ union { /* bytes 4-N */
+ struct smp_request_general report_general;
+ struct smp_request_phy_identifier discover;
+ struct smp_request_general report_manufacturer_information;
+ struct smp_request_phy_identifier report_phy_sata;
+ struct smp_request_phy_control phy_control;
+ struct smp_request_phy_identifier report_phy_error_log;
+ struct smp_request_phy_identifier report_route_information;
+ struct smp_request_configure_route_information configure_route_information;
+ struct smp_request_vendor_specific vendor_specific_request;
+ } request;
+
+};
+
+
+/**
+ * struct smp_response_report_general - This structure depicts the SMP Report
+ * General for expander devices. It adheres to the SAS-2.1 specification.
+ *
+ * For specific information on each of these individual fields please reference
+ * the SAS specification Application layer section on SMP.
+ */
+struct smp_response_report_general {
+ u16 expander_change_count; /* byte 4-5 */
+ u16 expander_route_indexes; /* byte 6-7 */
+
+ u32 reserved_byte8:7; /* byte 8 bit 0-6 */
+ u32 long_response:1; /* byte 8 bit 7 */
+
+ u32 number_of_phys:8; /* byte 9 */
+
+ u32 configurable_route_table:1; /* byte 10 */
+ u32 configuring:1;
+ u32 configures_others:1;
+ u32 open_reject_retry_supported:1;
+ u32 stp_continue_awt:1;
+ u32 self_configuring:1;
+ u32 zone_configuring:1;
+ u32 table_to_table_supported:1;
+
+ u32 reserved_byte11:8; /* byte 11 */
+
+ u32 enclosure_logical_identifier_high; /* byte 12-15 */
+ u32 enclosure_logical_identifier_low; /* byte 16-19 */
+
+ u32 reserved_byte20_23;
+ u32 reserved_byte24_27;
+
+};
+
+struct smp_response_report_general_long {
+ struct smp_response_report_general sas1_1;
+
+ struct {
+ u16 reserved1;
+ u16 stp_bus_inactivity_time_limit;
+ u16 stp_max_connect_time_limit;
+ u16 stp_smp_i_t_nexus_loss_time;
+
+ u32 zoning_enabled:1;
+ u32 zoning_supported:1;
+ u32 physicaL_presence_asserted:1;
+ u32 zone_locked:1;
+ u32 reserved2:1;
+ u32 num_zone_groups:3;
+ u32 saving_zoning_enabled_supported:3;
+ u32 saving_zone_perms_table_supported:1;
+ u32 saving_zone_phy_info_supported:1;
+ u32 saving_zone_manager_password_supported:1;
+ u32 saving:1;
+ u32 reserved3:1;
+ u32 max_number_routed_sas_addresses:16;
+
+ struct sci_sas_address active_zone_manager_sas_address;
+
+ u16 zone_lock_inactivity_time_limit;
+ u16 reserved4;
+
+ u8 reserved5;
+ u8 first_enclosure_connector_element_index;
+ u8 number_of_enclosure_connector_element_indices;
+ u8 reserved6;
+
+ u32 reserved7:7;
+ u32 reduced_functionality:1;
+ u32 time_to_reduce_functionality:8;
+ u32 initial_time_to_reduce_functionality:8;
+ u8 max_reduced_functionality_time;
+
+ u16 last_self_config_status_descriptor_index;
+ u16 max_number_of_stored_self_config_status_descriptors;
+
+ u16 last_phy_event_list_descriptor_index;
+ u16 max_number_of_stored_phy_event_list_descriptors;
+ } sas2;
+
+};
+
+/**
+ * struct smp_response_report_manufacturer_information - This structure depicts
+ * the SMP report manufacturer information for expander devices. It adheres
+ * to the SAS-2.1 specification.
+ *
+ * For specific information on each of these individual fields please reference
+ * the SAS specification Application layer section on SMP.
+ */
+struct smp_response_report_manufacturer_information {
+ u32 expander_change_count:16; /* bytes 4-5 */
+ u32 reserved1:16;
+
+ u32 sas1_1_format:1;
+ u32 reserved2:31;
+
+ u8 vendor_id[8];
+ u8 product_id[16];
+ u8 product_revision_level[4];
+ u8 component_vendor_id[8];
+ u8 component_id[2];
+ u8 component_revision_level;
+ u8 reserved3;
+ u8 vendor_specific[8];
+
+};
+
+#define SMP_RESPONSE_DISCOVER_FORMAT_1_1_SIZE 52
+#define SMP_RESPONSE_DISCOVER_FORMAT_2_SIZE 116
+
+/**
+ * struct smp_discover_response_protocols - This structure depicts the discover
+ * response where the supported protocols by the remote phy are specified.
+ *
+ * For specific information on each of these individual fields please reference
+ * the SAS specification Link layer section on address frames.
+ */
+struct smp_discover_response_protocols {
+ union {
+ struct {
+ u16 attached_sata_host:1;
+ u16 attached_smp_initiator:1;
+ u16 attached_stp_initiator:1;
+ u16 attached_ssp_initiator:1;
+ u16 reserved3:4;
+ u16 attached_sata_device:1;
+ u16 attached_smp_target:1;
+ u16 attached_stp_target:1;
+ u16 attached_ssp_target:1;
+ u16 reserved4:3;
+ u16 attached_sata_port_selector:1;
+ } bits;
+
+ u16 all;
+ } u;
+
+};
+
+/**
+ * struct SMP_RESPONSE_DISCOVER_FORMAT - This structure defines the SMP phy
+ * discover response format. It handles both SAS1.1 and SAS 2 definitions.
+ * The unions indicate locations where the SAS specification versions differ
+ * from one another.
+ *
+ *
+ */
+struct smp_response_discover {
+
+ union {
+ struct {
+ u8 reserved[2];
+ } sas1_1;
+
+ struct {
+ u16 expander_change_count;
+ } sas2;
+
+ } u1;
+
+ u8 reserved1[3];
+ u8 phy_identifier;
+ u8 reserved2[2];
+
+ union {
+ struct {
+ u16 reserved1:4;
+ u16 attached_device_type:3;
+ u16 reserved2:1;
+ u16 negotiated_physical_link_rate:4;
+ u16 reserved3:4;
+ } sas1_1;
+
+ struct {
+ u16 attached_reason:4;
+ u16 attached_device_type:3;
+ u16 reserved2:1;
+ u16 negotiated_logical_link_rate:4;
+ u16 reserved3:4;
+ } sas2;
+
+ } u2;
+
+ struct smp_discover_response_protocols protocols;
+ struct sci_sas_address sas_address;
+ struct sci_sas_address attached_sas_address;
+
+ u8 attached_phy_identifier;
+
+ union {
+ struct {
+ u8 reserved;
+ } sas1_1;
+
+ struct {
+ u8 attached_break_reply_capable:1;
+ u8 attached_requested_inside_zpsds:1;
+ u8 attached_inside_zpsds_persistent:1;
+ u8 reserved1:5;
+ } sas2;
+
+ } u3;
+
+ u8 reserved_for_identify[6];
+
+ u32 hardware_min_physical_link_rate:4;
+ u32 programmed_min_physical_link_rate:4;
+ u32 hardware_max_physical_link_rate:4;
+ u32 programmed_max_physical_link_rate:4;
+ u32 phy_change_count:8;
+ u32 partial_pathway_timeout_value:4;
+ u32 reserved5:3;
+ u32 virtual_phy:1;
+
+ u32 routing_attribute:4;
+ u32 reserved6:4;
+ u32 connector_type:7;
+ u32 reserved7:1;
+ u32 connector_element_index:8;
+ u32 connector_physical_link:8;
+
+ u16 reserved8;
+ u16 vendor_specific;
+
+ union {
+ struct {
+ /**
+ * In the SAS 1.1 specification this structure ends after 52 bytes.
+ * As a result, the contents of this field should never have a
+ * real value. It is undefined.
+ */
+ u8 undefined[SMP_RESPONSE_DISCOVER_FORMAT_2_SIZE
+ - SMP_RESPONSE_DISCOVER_FORMAT_1_1_SIZE];
+ } sas1_1;
+
+ struct {
+ struct sci_sas_address attached_device_name;
+
+ u32 zoning_enabled:1;
+ u32 inside_zpsds:1;
+ u32 zone_group_persistent:1;
+ u32 reserved1:1;
+ u32 requested_inside_zpsds:1;
+ u32 inside_zpsds_persistent:1;
+ u32 requested_inside_zpsds_changed_by_expander:1;
+ u32 reserved2:1;
+ u32 reserved_for_zoning_fields:16;
+ u32 zone_group:8;
+
+ u8 self_configuration_status;
+ u8 self_configuration_levels_completed;
+ u16 reserved_for_self_config_fields;
+
+ struct sci_sas_address self_configuration_sas_address;
+
+ u32 programmed_phy_capabilities;
+ u32 current_phy_capabilities;
+ u32 attached_phy_capabilities;
+
+ u32 reserved3;
+
+ u32 reserved4:16;
+ u32 negotiated_physical_link_rate:4;
+ u32 reason:4;
+ u32 hardware_muxing_supported:1;
+ u32 negotiated_ssc:1;
+ u32 reserved5:6;
+
+ u32 default_zoning_enabled:1;
+ u32 reserved6:1;
+ u32 default_zone_group_persistent:1;
+ u32 reserved7:1;
+ u32 default_requested_inside_zpsds:1;
+ u32 default_inside_zpsds_persistent:1;
+ u32 reserved8:2;
+ u32 reserved9:16;
+ u32 default_zone_group:8;
+
+ u32 saved_zoning_enabled:1;
+ u32 reserved10:1;
+ u32 saved_zone_group_persistent:1;
+ u32 reserved11:1;
+ u32 saved_requested_inside_zpsds:1;
+ u32 saved_inside_zpsds_persistent:1;
+ u32 reserved12:18;
+ u32 saved_zone_group:8;
+
+ u32 reserved14:2;
+ u32 shadow_zone_group_persistent:1;
+ u32 reserved15:1;
+ u32 shadow_requested_inside_zpsds:1;
+ u32 shadow_inside_zpsds_persistent:1;
+ u32 reserved16:18;
+ u32 shadow_zone_group:8;
+
+ u8 device_slot_number;
+ u8 device_slot_group_number;
+ u8 device_slot_group_output_connector[6];
+ } sas2;
+
+ } u4;
+
+};
+
+/**
+ * struct smp_response_report_phy_sata - This structure depicts the contents of
+ * the SAS SMP REPORT PHY SATA frame. For specific information on each of
+ * these individual fields please reference the SAS specification Link layer
+ * section on address frames.
+ *
+ *
+ */
+struct smp_response_report_phy_sata {
+ u32 ignored_byte_4_7; /* bytes 4-7 */
+
+ u32 affiliations_valid:1;
+ u32 affiliations_supported:1;
+ u32 reserved_byte11:6; /* byte 11 */
+ u32 ignored_byte10:8; /* byte 10 */
+ u32 phy_identifier:8; /* byte 9 */
+ u32 reserved_byte_8:8; /* byte 8 */
+
+ u32 reserved_12_15;
+ u32 stp_sas_address[2];
+ u8 device_to_host_fis[20];
+ u32 reserved_44_47;
+ u32 affiliated_stp_initiator_sas_address[2];
+
+};
+
+struct smp_response_vendor_specific {
+ u8 response_bytes[SMP_REQUEST_VENDOR_SPECIFIC_MAX_LENGTH];
+};
+
+union smp_response_body {
+ struct smp_response_report_general report_general;
+ struct smp_response_report_manufacturer_information report_manufacturer_information;
+ struct smp_response_discover discover;
+ struct smp_response_report_phy_sata report_phy_sata;
+ struct smp_response_vendor_specific vendor_specific_response;
+};
+
+/**
+ * struct smp_response - This structure simply unionizes the existing response
+ * structures into a common response type.
+ *
+ *
+ */
+struct smp_response {
+ struct smp_response_header header;
+
+ union smp_response_body response;
+
+};
+
+/* SMP Request Functions */
+#define SMP_FUNCTION_REPORT_GENERAL 0x00
+#define SMP_FUNCTION_REPORT_MANUFACTURER_INFORMATION 0x01
+#define SMP_FUNCTION_DISCOVER 0x10
+#define SMP_FUNCTION_REPORT_PHY_ERROR_LOG 0x11
+#define SMP_FUNCTION_REPORT_PHY_SATA 0x12
+#define SMP_FUNCTION_REPORT_ROUTE_INFORMATION 0X13
+#define SMP_FUNCTION_CONFIGURE_ROUTE_INFORMATION 0X90
+#define SMP_FUNCTION_PHY_CONTROL 0x91
+#define SMP_FUNCTION_PHY_TEST 0x92
+
+#define SMP_FRAME_TYPE_REQUEST 0x40
+#define SMP_FRAME_TYPE_RESPONSE 0x41
+
+#define PHY_OPERATION_NOP 0x00
+#define PHY_OPERATION_LINK_RESET 0x01
+#define PHY_OPERATION_HARD_RESET 0x02
+#define PHY_OPERATION_DISABLE 0x03
+#define PHY_OPERATION_CLEAR_ERROR_LOG 0x05
+#define PHY_OPERATION_CLEAR_AFFILIATION 0x06
+
+#define NPLR_PHY_ENABLED_UNK_LINK_RATE 0x00
+#define NPLR_PHY_DISABLED 0x01
+#define NPLR_PHY_ENABLED_SPD_NEG_FAILED 0x02
+#define NPLR_PHY_ENABLED_SATA_HOLD 0x03
+#define NPLR_PHY_ENABLED_1_5G 0x08
+#define NPLR_PHY_ENABLED_3_0G 0x09
+
+/* SMP Function Result values. */
+#define SMP_RESULT_FUNCTION_ACCEPTED 0x00
+#define SMP_RESULT_UNKNOWN_FUNCTION 0x01
+#define SMP_RESULT_FUNCTION_FAILED 0x02
+#define SMP_RESULT_INVALID_REQUEST_FRAME_LEN 0x03
+#define SMP_RESULT_INAVALID_EXPANDER_CHANGE_COUNT 0x04
+#define SMP_RESULT_BUSY 0x05
+#define SMP_RESULT_INCOMPLETE_DESCRIPTOR_LIST 0x06
+#define SMP_RESULT_PHY_DOES_NOT_EXIST 0x10
+#define SMP_RESULT_INDEX_DOES_NOT_EXIST 0x11
+#define SMP_RESULT_PHY_DOES_NOT_SUPPORT_SATA 0x12
+#define SMP_RESULT_UNKNOWN_PHY_OPERATION 0x13
+#define SMP_RESULT_UNKNOWN_PHY_TEST_FUNCTION 0x14
+#define SMP_RESULT_PHY_TEST_IN_PROGRESS 0x15
+#define SMP_RESULT_PHY_VACANT 0x16
+
+/* Attached Device Types */
+#define SMP_NO_DEVICE_ATTACHED 0
+#define SMP_END_DEVICE_ONLY 1
+#define SMP_EDGE_EXPANDER_DEVICE 2
+#define SMP_FANOUT_EXPANDER_DEVICE 3
+
+/* Expander phy routine attribute */
+#define DIRECT_ROUTING_ATTRIBUTE 0
+#define SUBTRACTIVE_ROUTING_ATTRIBUTE 1
+#define TABLE_ROUTING_ATTRIBUTE 2
+
+#endif /* _INTEL_SAS_H_ */
+
diff --git a/drivers/scsi/isci/core/intel_sat.h b/drivers/scsi/isci/core/intel_sat.h
new file mode 100644
index 000000000000..c4d78ed35cf1
--- /dev/null
+++ b/drivers/scsi/isci/core/intel_sat.h
@@ -0,0 +1,95 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SAT_H_
+#define _SAT_H_
+
+/**
+ * This file contains constants and constructs defined in the SCSI to ATA
+ * Translation (SAT) T10 standard. For more information please refer to
+ * www.t10.org.
+ *
+ *
+ */
+
+/**
+ *
+ *
+ * SAT_PROTOCOLS These constants indicate the various protocol values that can
+ * be supported in a SAT translator.
+ */
+#define SAT_PROTOCOL_ATA_HARD_RESET 0
+#define SAT_PROTOCOL_SOFT_RESET 1
+#define SAT_PROTOCOL_NON_DATA 3
+#define SAT_PROTOCOL_PIO_DATA_IN 4
+#define SAT_PROTOCOL_PIO_DATA_OUT 5
+#define SAT_PROTOCOL_DMA 6
+#define SAT_PROTOCOL_DMA_QUEUED 7
+#define SAT_PROTOCOL_DEVICE_DIAGNOSTIC 8
+#define SAT_PROTOCOL_DEVICE_RESET 9
+#define SAT_PROTOCOL_UDMA_DATA_IN 10
+#define SAT_PROTOCOL_UDMA_DATA_OUT 11
+#define SAT_PROTOCOL_FPDMA 12
+#define SAT_PROTOCOL_RETURN_RESPONSE_INFO 15
+
+#define SAT_PROTOCOL_PACKET 0x10
+#define SAT_PROTOCOL_PACKET_NON_DATA (SAT_PROTOCOL_PACKET | 0x0)
+#define SAT_PROTOCOL_PACKET_DMA_DATA_IN (SAT_PROTOCOL_PACKET | 0x1)
+#define SAT_PROTOCOL_PACKET_DMA_DATA_OUT (SAT_PROTOCOL_PACKET | 0x2)
+#define SAT_PROTOCOL_PACKET_PIO_DATA_IN (SAT_PROTOCOL_PACKET | 0x3)
+#define SAT_PROTOCOL_PACKET_PIO_DATA_OUT (SAT_PROTOCOL_PACKET | 0x4)
+
+#endif /* _SAT_H_ */
+
diff --git a/drivers/scsi/isci/core/intel_sata.h b/drivers/scsi/isci/core/intel_sata.h
new file mode 100644
index 000000000000..47390d54064d
--- /dev/null
+++ b/drivers/scsi/isci/core/intel_sata.h
@@ -0,0 +1,280 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SATA_H_
+#define _SATA_H_
+
+#include <linux/types.h>
+
+/**
+ * This file defines all of the SATA releated constants, enumerations, and
+ * types. Please note that this file does not necessarily contain an
+ * exhaustive list of all contants and commands.
+ *
+ *
+ */
+
+/**
+ *
+ *
+ * SATA FIS Types These constants depict the various SATA FIS types devined in
+ * the serial ATA specification.
+ */
+#define SATA_FIS_TYPE_REGH2D 0x27
+#define SATA_FIS_TYPE_REGD2H 0x34
+#define SATA_FIS_TYPE_SETDEVBITS 0xA1
+#define SATA_FIS_TYPE_DMA_ACTIVATE 0x39
+#define SATA_FIS_TYPE_DMA_SETUP 0x41
+#define SATA_FIS_TYPE_BIST_ACTIVATE 0x58
+#define SATA_FIS_TYPE_PIO_SETUP 0x5F
+#define SATA_FIS_TYPE_DATA 0x46
+
+#define SATA_REGISTER_FIS_SIZE 0x20
+
+/**
+ * struct sata_fis_header - This is the common definition for a SATA FIS Header
+ * word. A different header word is defined for any FIS type that does not
+ * use the standard header.
+ *
+ *
+ */
+struct sata_fis_header {
+ u32 fis_type:8; /* word 0 */
+ u32 pm_port:4;
+ u32 reserved:1;
+ u32 direction_flag:1; /* direction */
+ u32 interrupt_flag:1;
+ u32 command_flag:1; /* command, auto_activate, or notification */
+ u32 status:8;
+ u32 error:8;
+};
+
+
+/**
+ * struct sata_fis_reg_h2d - This is the definition for a SATA Host to Device
+ * Register FIS.
+ *
+ *
+ */
+struct sata_fis_reg_h2d {
+ u32 fis_type:8; /* word 0 */
+ u32 pm_port:4;
+ u32 reserved0:3;
+ u32 command_flag:1;
+ u32 command:8;
+ u32 features:8;
+ u32 lba_low:8; /* word 1 */
+ u32 lba_mid:8;
+ u32 lba_high:8;
+ u32 device:8;
+ u32 lba_low_exp:8; /* word 2 */
+ u32 lba_mid_exp:8;
+ u32 lba_high_exp:8;
+ u32 features_exp:8;
+ u32 sector_count:8; /* word 3 */
+ u32 sector_count_exp:8;
+ u32 reserved1:8;
+ u32 control:8;
+ u32 reserved2; /* word 4 */
+};
+
+/**
+ * struct sata_fis_reg_d2h - SATA Device To Host FIS
+ *
+ *
+ */
+struct sata_fis_reg_d2h {
+ u32 fis_type:8; /* word 0 */
+ u32 pm_port:4;
+ u32 reserved0:2;
+ u32 irq:1;
+ u32 reserved1:1;
+ u32 status:8;
+ u32 error:8;
+ u8 lba_low; /* word 1 */
+ u8 lba_mid;
+ u8 lba_high;
+ u8 device;
+ u8 lba_low_exp; /* word 2 */
+ u8 lba_mid_exp;
+ u8 lba_high_exp;
+ u8 reserved;
+ u8 sector_count; /* word 3 */
+ u8 sector_count_exp;
+ u16 reserved2;
+ u32 reserved3;
+};
+
+/**
+ *
+ *
+ * Status field bit definitions
+ */
+#define SATA_FIS_STATUS_DEVBITS_MASK (0x77)
+
+/**
+ * struct sata_fis_set_dev_bits - SATA Set Device Bits FIS
+ *
+ *
+ */
+struct sata_fis_set_dev_bits {
+ u32 fis_type:8; /* word 0 */
+ u32 pm_port:4;
+ u32 reserved0:2;
+ u32 irq:1;
+ u32 notification:1;
+ u32 status_low:4;
+ u32 status_high:4;
+ u32 error:8;
+ u32 s_active; /* word 1 */
+};
+
+/**
+ * struct sata_fis_dma_activate - SATA DMA Activate FIS
+ *
+ *
+ */
+struct sata_fis_dma_activate {
+ u32 fis_type:8; /* word 0 */
+ u32 pm_port:4;
+ u32 reserved0:24;
+};
+
+/**
+ *
+ *
+ * The lower 5 bits in the DMA Buffer ID Low field of the DMA Setup are used to
+ * communicate the command tag.
+ */
+#define SATA_DMA_SETUP_TAG_ENABLE 0x1F
+
+#define SATA_DMA_SETUP_AUTO_ACT_ENABLE 0x80
+
+/**
+ * struct sata_fis_dma_setup - SATA DMA Setup FIS
+ *
+ *
+ */
+struct sata_fis_dma_setup {
+ u32 fis_type:8; /* word 0 */
+ u32 pm_port:4;
+ u32 reserved_00:1;
+ u32 direction:1;
+ u32 irq:1;
+ u32 auto_activate:1;
+ u32 reserved_01:16;
+ u32 dma_buffer_id_low; /* word 1 */
+ u32 dma_buffer_id_high; /* word 2 */
+ u32 reserved0; /* word 3 */
+ u32 dma_buffer_offset; /* word 4 */
+ u32 dma_transfer_count; /* word 5 */
+ u32 reserved1; /* word 6 */
+};
+
+/**
+ * struct sata_fis_bist_activate - SATA BIST Activate FIS
+ *
+ *
+ */
+struct sata_fis_bist_activate {
+ u32 fis_type:8; /* word 0 */
+ u32 reserved0:8;
+ u32 pattern_definition:8;
+ u32 reserved1:8;
+ u32 data1; /* word 1 */
+ u32 data2; /* word 1 */
+};
+
+/*
+ * SATA PIO Setup FIS
+ */
+struct sata_fis_pio_setup {
+ u32 fis_type:8; /* word 0 */
+ u32 pm_port:4;
+ u32 reserved_00:1;
+ u32 direction:1;
+ u32 irq:1;
+ u32 reserved_01:1;
+ u32 status:8;
+ u32 error:8;
+ u32 lba_low:8; /* word 1 */
+ u32 lba_mid:8;
+ u32 lba_high:8;
+ u32 device:8;
+ u32 lba_low_exp:8; /* word 2 */
+ u32 lba_mid_exp:8;
+ u32 lba_high_exp:8;
+ u32 reserved:8;
+ u32 sector_count:8; /* word 3 */
+ u32 sector_count_exp:8;
+ u32 reserved1:8;
+ u32 ending_status:8;
+ u32 transfter_count:16; /* word 4 */
+ u32 reserved3:16;
+};
+
+/**
+ * struct sata_fis_data - SATA Data FIS
+ *
+ *
+ */
+struct sata_fis_data {
+ u32 fis_type:8; /* word 0 */
+ u32 pm_port:4;
+ u32 reserved0:24;
+ u8 data[4]; /* word 1 */
+};
+
+#endif /* _SATA_H_ */
diff --git a/drivers/scsi/isci/core/intel_scsi.h b/drivers/scsi/isci/core/intel_scsi.h
new file mode 100644
index 000000000000..1e45d3c98127
--- /dev/null
+++ b/drivers/scsi/isci/core/intel_scsi.h
@@ -0,0 +1,474 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * This file defines all of the SCSI related constants, enumerations, and
+ * types. Please note that this file does not necessarily contain an
+ * exhaustive list of all constants, commands, sub-commands, etc.
+ *
+ *
+ */
+
+#ifndef _SCSI_H__
+#define _SCSI_H__
+
+
+/*
+ * ******************************************************************************
+ * * C O N S T A N T S A N D M A C R O S
+ * ****************************************************************************** */
+
+/**
+ * enum _SCSI_TASK_MGMT_REQUEST_CODES - This enumberation contains the
+ * constants to be used for SCSI task management request codes. SAM does
+ * not specify any particular values for these codes so constants used here
+ * are the same as those specified in SAS.
+ *
+ *
+ */
+enum scsi_task_mgmt_request_codes {
+ SCSI_TASK_REQUEST_ABORT_TASK = 0x01,
+ SCSI_TASK_REQUEST_ABORT_TASK_SET = 0x02,
+ SCSI_TASK_REQUEST_CLEAR_TASK_SET = 0x04,
+ SCSI_TASK_REQUEST_LOGICAL_UNIT_RESET = 0x08,
+ SCSI_TASK_REQUEST_I_T_NEXUS_RESET = 0x10,
+ SCSI_TASK_REQUEST_CLEAR_ACA = 0x40,
+ SCSI_TASK_REQUEST_QUERY_TASK = 0x80,
+ SCSI_TASK_REQUEST_QUERY_TASK_SET = 0x81,
+ SCSI_TASK_REQUEST_QUERY_UNIT_ATTENTION = 0x82,
+
+};
+
+/**
+ * enum _SCSI_TASK_MGMT_RESPONSE_CODES - This enumeration contains all of the
+ * SCSI task management response codes.
+ *
+ *
+ */
+enum scsi_task_mgmt_response_codes {
+ SCSI_TASK_MGMT_FUNC_COMPLETE = 0,
+ SCSI_INVALID_FRAME = 2,
+ SCSI_TASK_MGMT_FUNC_NOT_SUPPORTED = 4,
+ SCSI_TASK_MGMT_FUNC_FAILED = 5,
+ SCSI_TASK_MGMT_FUNC_SUCCEEDED = 8,
+ SCSI_INVALID_LUN = 9
+};
+
+/**
+ * enum _SCSI_SENSE_RESPONSE_CODE - this enumeration depicts the types of sense
+ * data responses as per SPC-3.
+ *
+ *
+ */
+enum scsi_sense_response_code {
+ SCSI_FIXED_CURRENT_RESPONSE_CODE = 0x70,
+ SCSI_FIXED_DEFERRED_RESPONSE_CODE = 0x71,
+ SCSI_DESCRIPTOR_CURRENT_RESPONSE_CODE = 0x72,
+ SCSI_DESCRIPTOR_DEFERRED_RESPONSE_CODE = 0x73
+
+};
+
+/*
+ * This constant represents the valid bit located in byte 0 of a FIXED
+ * format sense data. */
+#define SCSI_FIXED_SENSE_DATA_VALID_BIT 0x80
+
+#define SCSI_FIXED_SENSE_DATA_BASE_LENGTH 18
+
+/* This value is used in the DATAPRES field of the SCSI Response IU. */
+#define SCSI_RESPONSE_DATA_PRES_SENSE_DATA 0x02
+
+/**
+ *
+ *
+ * SCSI_SENSE_KEYS These constants delineate all of the SCSI protocol sense key
+ * constants
+ */
+#define SCSI_SENSE_NO_SENSE 0x00
+#define SCSI_SENSE_RECOVERED_ERROR 0x01
+#define SCSI_SENSE_NOT_READY 0x02
+#define SCSI_SENSE_MEDIUM_ERROR 0x03
+#define SCSI_SENSE_HARDWARE_ERROR 0x04
+#define SCSI_SENSE_ILLEGAL_REQUEST 0x05
+#define SCSI_SENSE_UNIT_ATTENTION 0x06
+#define SCSI_SENSE_DATA_PROTECT 0x07
+#define SCSI_SENSE_BLANK_CHECK 0x08
+#define SCSI_SENSE_VENDOR_SPECIFIC 0x09
+#define SCSI_SENSE_COPY_ABORTED 0x0A
+#define SCSI_SENSE_ABORTED_COMMAND 0x0B
+#define SCSI_SENSE_VOLUME_OVERFLOW 0x0D
+#define SCSI_SENSE_MISCOMPARE 0x0E
+
+/**
+ *
+ *
+ * SCSI_ADDITIONAL_SENSE_CODES These constants delineate all of the SCSI
+ * protocol additional sense code constants.
+ */
+#define SCSI_ASC_NO_ADDITIONAL_SENSE 0x00
+#define SCSI_ASC_INITIALIZING_COMMAND_REQUIRED 0x04
+#define SCSI_ASC_LUN_SELF_TEST_IN_PROGRESS 0x04
+#define SCSI_ASC_LUN_FORMAT_IN_PROGRESS 0x04
+#define SCSI_ASC_LUN_NOT_RESPOND_TO_SELECTION 0x05
+#define SCSI_ASC_UNRECOVERED_READ_ERROR 0x11
+#define SCSI_ASC_INVALID_COMMAND_OPERATION_CODE 0x20
+#define SCSI_ASC_LBA_OUT_OF_RANGE 0x21
+#define SCSI_ASC_INVALID_FIELD_IN_CDB 0x24
+#define SCSI_ASC_INVALID_FIELD_IN_PARM_LIST 0x26
+#define SCSI_ASC_WRITE_PROTECTED 0x27
+#define SCSI_ASC_NOT_READY_TO_READY_CHANGE 0x28
+#define SCSI_ASC_SAVING_PARMS_NOT_SUPPORTED 0x39
+#define SCSI_ASC_MEDIUM_NOT_PRESENT 0x3A
+#define SCSI_ASC_INTERNAL_TARGET_FAILURE 0x44
+#define SCSI_ASC_IU_CRC_ERROR_DETECTED 0x47
+#define SCSI_ASC_MEDIUM_REMOVAL_REQUEST 0x5A
+#define SCSI_ASC_COMMAND_SEQUENCE_ERROR 0x2C
+#define SCSI_ASC_MEDIA_LOAD_OR_EJECT_FAILED 0x53
+#define SCSI_ASC_HARDWARE_IMPENDING_FAILURE 0x5D
+#define SCSI_ASC_POWER_STATE_CHANGE 0x5E
+#define SCSI_DIAGNOSTIC_FAILURE_ON_COMPONENT 0x40
+#define SCSI_ASC_ATA_DEVICE_FEATURE_NOT_ENABLED 0x67
+
+/**
+ *
+ *
+ * SCSI_ADDITIONAL_SENSE_CODE_QUALIFIERS This enumeration contains all of the
+ * used SCSI protocol additional sense code qualifier constants.
+ */
+#define SCSI_ASCQ_NO_ADDITIONAL_SENSE 0x00
+#define SCSI_ASCQ_INVALID_FIELD_IN_CDB 0x00
+#define SCSI_ASCQ_INVALID_FIELD_IN_PARM_LIST 0x00
+#define SCSI_ASCQ_LUN_NOT_RESPOND_TO_SELECTION 0x00
+#define SCSI_ASCQ_INTERNAL_TARGET_FAILURE 0x00
+#define SCSI_ASCQ_LBA_OUT_OF_RANGE 0x00
+#define SCSI_ASCQ_MEDIUM_NOT_PRESENT 0x00
+#define SCSI_ASCQ_NOT_READY_TO_READY_CHANGE 0x00
+#define SCSI_ASCQ_WRITE_PROTECTED 0x00
+#define SCSI_ASCQ_UNRECOVERED_READ_ERROR 0x00
+#define SCSI_ASCQ_SAVING_PARMS_NOT_SUPPORTED 0x00
+#define SCSI_ASCQ_INVALID_COMMAND_OPERATION_CODE 0x00
+#define SCSI_ASCQ_MEDIUM_REMOVAL_REQUEST 0x01
+#define SCSI_ASCQ_INITIALIZING_COMMAND_REQUIRED 0x02
+#define SCSI_ASCQ_IU_CRC_ERROR_DETECTED 0x03
+#define SCSI_ASCQ_LUN_FORMAT_IN_PROGRESS 0x04
+#define SCSI_ASCQ_LUN_SELF_TEST_IN_PROGRESS 0x09
+#define SCSI_ASCQ_GENERAL_HARD_DRIVE_FAILURE 0x10
+#define SCSI_ASCQ_IDLE_CONDITION_ACTIVATE_BY_COMMAND 0x03
+#define SCSI_ASCQ_STANDBY_CONDITION_ACTIVATE_BY_COMMAND 0x04
+#define SCSI_ASCQ_POWER_STATE_CHANGE_TO_IDLE 0x42
+#define SCSI_ASCQ_POWER_STATE_CHANGE_TO_STANDBY 0x43
+#define SCSI_ASCQ_ATA_DEVICE_FEATURE_NOT_ENABLED 0x0B
+#define SCSI_ASCQ_UNRECOVERED_READ_ERROR_AUTO_REALLOCATE_FAIL 0x04
+
+
+
+/**
+ *
+ *
+ * SCSI_STATUS_CODES These constants define all of the used SCSI status values.
+ */
+#define SCSI_STATUS_GOOD 0x00
+#define SCSI_STATUS_CHECK_CONDITION 0x02
+#define SCSI_STATUS_CONDITION_MET 0x04
+#define SCSI_STATUS_BUSY 0x08
+#define SCSI_STATUS_TASKFULL 0x28
+#define SCSI_STATUS_ACA 0x30
+#define SCSI_STATUS_ABORT 0x40
+
+/**
+ *
+ *
+ * SCSI_OPERATION_CODES These constants delineate all of the SCSI
+ * command/operation codes.
+ */
+#define SCSI_INQUIRY 0x12
+#define SCSI_READ_CAPACITY_10 0x25
+#define SCSI_SERVICE_ACTION_IN_16 0x9E
+#define SCSI_TEST_UNIT_READY 0x00
+#define SCSI_START_STOP_UNIT 0x1B
+#define SCSI_SYNCHRONIZE_CACHE_10 0x35
+#define SCSI_SYNCHRONIZE_CACHE_16 0x91
+#define SCSI_REQUEST_SENSE 0x03
+#define SCSI_REPORT_LUNS 0xA0
+#define SCSI_REASSIGN_BLOCKS 0x07
+#define SCSI_READ_6 0x08
+#define SCSI_READ_10 0x28
+#define SCSI_READ_12 0xA8
+#define SCSI_READ_16 0x88
+#define SCSI_WRITE_6 0x0A
+#define SCSI_WRITE_10 0x2A
+#define SCSI_WRITE_12 0xAA
+#define SCSI_WRITE_16 0x8A
+#define SCSI_VERIFY_10 0x2F
+#define SCSI_VERIFY_12 0xAF
+#define SCSI_VERIFY_16 0x8F
+#define SCSI_SEEK_6 0x01
+#define SCSI_SEEK_10 0x02
+#define SCSI_WRITE_VERIFY 0x2E
+#define SCSI_FORMAT_UNIT 0x04
+#define SCSI_READ_BUFFER 0x3C
+#define SCSI_WRITE_BUFFER 0x3B
+#define SCSI_SEND_DIAGNOSTIC 0x1D
+#define SCSI_RECEIVE_DIAGNOSTIC 0x1C
+#define SCSI_MODE_SENSE_6 0x1A
+#define SCSI_MODE_SENSE_10 0x5A
+#define SCSI_MODE_SELECT_6 0x15
+#define SCSI_MODE_SELECT_10 0x55
+#define SCSI_MAINTENANCE_IN 0xA3
+#define SCSI_LOG_SENSE 0x4D
+#define SCSI_LOG_SELECT 0x4C
+#define SCSI_RESERVE_6 0x16
+#define SCSI_RESERVE_10 0x56
+#define SCSI_RELEASE_6 0x17
+#define SCSI_RELEASE_10 0x57
+#define SCSI_ATA_PASSTHRU_12 0xA1
+#define SCSI_ATA_PASSTHRU_16 0x85
+#define SCSI_WRITE_LONG_10 0x3F
+#define SCSI_WRITE_LONG_16 0x9F
+#define SCSI_PERSISTENT_RESERVE_IN 0x5E
+#define SCSI_PERSISTENT_RESERVE_OUT 0x5F
+
+/**
+ *
+ *
+ * SCSI_SERVICE_ACTION_IN_CODES Service action in operations.
+ */
+#define SCSI_SERVICE_ACTION_IN_CODES_READ_CAPACITY_16 0x10
+
+#define SCSI_SERVICE_ACTION_MASK 0x1f
+
+/**
+ *
+ *
+ * SCSI_MAINTENANCE_IN_SERVICE_ACTION_CODES MAINTENANCE IN service action codes.
+ */
+#define SCSI_REPORT_TASK_MGMT 0x0D
+#define SCSI_REPORT_OP_CODES 0x0C
+
+/**
+ *
+ *
+ * SCSI_MODE_PAGE_CONTROLS These constants delineate all of the used SCSI Mode
+ * Page control values.
+ */
+#define SCSI_MODE_SENSE_PC_CURRENT 0x0
+#define SCSI_MODE_SENSE_PC_CHANGEABLE 0x1
+#define SCSI_MODE_SENSE_PC_DEFAULT 0x2
+#define SCSI_MODE_SENSE_PC_SAVED 0x3
+
+#define SCSI_MODE_SENSE_PC_SHIFT 0x06
+#define SCSI_MODE_SENSE_PAGE_CODE_ENABLE 0x3F
+#define SCSI_MODE_SENSE_DBD_ENABLE 0x08
+#define SCSI_MODE_SENSE_LLBAA_ENABLE 0x10
+
+/**
+ *
+ *
+ * SCSI_MODE_PAGE_CODES These constants delineate all of the used SCSI Mode
+ * Page codes.
+ */
+#define SCSI_MODE_PAGE_READ_WRITE_ERROR 0x01
+#define SCSI_MODE_PAGE_DISCONNECT_RECONNECT 0x02
+#define SCSI_MODE_PAGE_CACHING 0x08
+#define SCSI_MODE_PAGE_CONTROL 0x0A
+#define SCSI_MODE_PAGE_PROTOCOL_SPECIFIC_PORT 0x19
+#define SCSI_MODE_PAGE_POWER_CONDITION 0x1A
+#define SCSI_MODE_PAGE_INFORMATIONAL_EXCP_CONTROL 0x1C
+#define SCSI_MODE_PAGE_ALL_PAGES 0x3F
+
+#define SCSI_MODE_SENSE_ALL_SUB_PAGES_CODE 0xFF
+#define SCSI_MODE_SENSE_NO_SUB_PAGES_CODE 0x0
+#define SCSI_MODE_SENSE_PROTOCOL_PORT_NUM_SUBPAGES 0x1
+#define SCSI_MODE_PAGE_CACHE_PAGE_WCE_BIT 0x04
+#define SCSI_MODE_PAGE_CACHE_PAGE_DRA_BIT 0x20
+#define SCSI_MODE_PAGE_DEXCPT_ENABLE 0x08
+#define SCSI_MODE_SENSE_HEADER_FUA_ENABLE 0x10
+#define SCSI_MODE_PAGE_POWER_CONDITION_STANDBY 0x1
+#define SCSI_MODE_PAGE_POWER_CONDITION_IDLE 0x2
+
+#define SCSI_MODE_SENSE_6_HEADER_LENGTH 4
+#define SCSI_MODE_SENSE_10_HEADER_LENGTH 8
+#define SCSI_MODE_SENSE_STD_BLOCK_DESCRIPTOR_LENGTH 8
+#define SCSI_MODE_SENSE_LLBA_BLOCK_DESCRIPTOR_LENGTH 16
+
+#define SCSI_MODE_PAGE_INFORMATIONAL_EXCP_DXCPT_ENABLE 0x08
+#define SCSI_MODE_PAGE_19_SAS_ID 0x6
+#define SCSI_MODE_PAGE_19_SUB1_PAGE_NUM 0x1
+#define SCSI_MODE_PAGE_19_SUB1_PC 0x59
+
+#define SCSI_MODE_HEADER_MEDIUM_TYPE_SBC 0x00
+
+/* Mode Select constrains related masks value */
+#define SCSI_MODE_SELECT_PF_BIT 0x1
+#define SCSI_MODE_SELECT_PF_MASK 0x10
+#define SCSI_MODE_SELECT_MODE_PAGE_MRIE_BYTE 0x6
+#define SCSI_MODE_SELECT_MODE_PAGE_MRIE_MASK 0x0F
+#define SCSI_MODE_SELECT_MODE_PAGE_SPF_MASK 0x40
+#define SCSI_MODE_SELECT_MODE_PAGE_01_AWRE_MASK 0x80
+#define SCSI_MODE_SELECT_MODE_PAGE_01_ARRE_MASK 0x40
+#define SCSI_MODE_SELECT_MODE_PAGE_01_RC_ERBITS_MASK 0x1F
+#define SCSI_MODE_SELECT_MODE_PAGE_08_FSW_LBCSS_NVDIS 0xC1
+#define SCSI_MODE_SELECT_MODE_PAGE_1C_PERF_TEST 0x84
+#define SCSI_MODE_SELECT_MODE_PAGE_0A_TST_TMF_RLEC 0xF1
+#define SCSI_MODE_SELECT_MODE_PAGE_0A_MODIFIER 0xF0
+#define SCSI_MODE_SELECT_MODE_PAGE_0A_UA_SWP 0x38
+#define SCSI_MODE_SELECT_MODE_PAGE_0A_TAS_AUTO 0x47
+
+
+#define SCSI_CONTROL_BYTE_NACA_BIT_ENABLE 0x04
+#define SCSI_MOVE_FUA_BIT_ENABLE 0x08
+#define SCSI_READ_CAPACITY_PMI_BIT_ENABLE 0x01
+#define SCSI_READ_CAPACITY_10_DATA_LENGTH 8
+#define SCSI_READ_CAPACITY_16_DATA_LENGTH 32
+
+/* Inquiry constants */
+#define SCSI_INQUIRY_EVPD_ENABLE 0x01
+#define SCSI_INQUIRY_PAGE_CODE_OFFSET 0x02
+#define SCSI_INQUIRY_SUPPORTED_PAGES_PAGE 0x00
+#define SCSI_INQUIRY_UNIT_SERIAL_NUM_PAGE 0x80
+#define SCSI_INQUIRY_DEVICE_ID_PAGE 0x83
+#define SCSI_INQUIRY_ATA_INFORMATION_PAGE 0x89
+#define SCSI_INQUIRY_BLOCK_DEVICE_PAGE 0xB1
+#define SCSI_INQUIRY_BLOCK_DEVICE_LENGTH 0x3C
+#define SCSI_INQUIRY_STANDARD_ALLOCATION_LENGTH 0x24 /* 36 */
+
+#define SCSI_REQUEST_SENSE_ALLOCATION_LENGTH 0xFC /* 252 */
+
+/** Defines the log page codes that are use in gathing Smart data
+ */
+#define SCSI_LOG_PAGE_SUPPORTED_PAGES 0x00
+#define SCSI_LOG_PAGE_INFORMATION_EXCEPTION 0x2F
+#define SCSI_LOG_PAGE_SELF_TEST 0x10
+
+/**
+ *
+ *
+ * SCSI_INQUIRY_VPD The following are constants used with vital product data
+ * inquiry pages. Values are already shifted into the proper nibble location.
+ */
+#define SCSI_PIV_ENABLE 0x80
+#define SCSI_LUN_ASSOCIATION 0x00
+#define SCSI_TARGET_PORT_ASSOCIATION 0x10
+
+#define SCSI_VEN_UNIQUE_IDENTIFIER_TYPE 0x00
+#define SCSI_NAA_IDENTIFIER_TYPE 0x03
+
+#define SCSI_T10_IDENTIFIER_TYPE 0x01
+#define SCSI_BINARY_CODE_SET 0x01
+#define SCSI_ASCII_CODE_SET 0x02
+#define SCSI_FC_PROTOCOL_IDENTIFIER 0x00
+#define SCSI_SAS_PROTOCOL_IDENTIFIER 0x60
+
+#define SCSI_VERIFY_BYTCHK_ENABLED 0x02
+
+#define SCSI_SYNCHRONIZE_CACHE_IMMED_ENABLED 0x02
+/**
+ *
+ *
+ * SCSI_START_STOP_UNIT_POWER_CONDITION_CODES The following are SCSI Start Stop
+ * Unit command Power Condition codes.
+ */
+#define SCSI_START_STOP_UNIT_POWER_CONDITION_START_VALID 0x0
+#define SCSI_START_STOP_UNIT_POWER_CONDITION_ACTIVE 0x1
+#define SCSI_START_STOP_UNIT_POWER_CONDITION_IDLE 0x2
+#define SCSI_START_STOP_UNIT_POWER_CONDITION_STANDBY 0x3
+#define SCSI_START_STOP_UNIT_POWER_CONDITION_LU_CONTROL 0x7
+#define SCSI_START_STOP_UNIT_POWER_CONDITION_FORCE_S_CONTROL 0xB
+
+#define SCSI_START_STOP_UNIT_IMMED_MASK 0x1
+#define SCSI_START_STOP_UNIT_IMMED_SHIFT 0
+
+#define SCSI_START_STOP_UNIT_START_BIT_MASK 0x1
+#define SCSI_START_STOP_UNIT_START_BIT_SHIFT 0
+
+#define SCSI_START_STOP_UNIT_LOEJ_BIT_MASK 0x2
+#define SCSI_START_STOP_UNIT_LOEJ_BIT_SHIFT 1
+
+#define SCSI_START_STOP_UNIT_NO_FLUSH_MASK 0x4
+#define SCSI_START_STOP_UNIT_NO_FLUSH_SHIFT 2
+
+#define SCSI_START_STOP_UNIT_POWER_CONDITION_MODIFIER_MASK 0xF
+#define SCSI_START_STOP_UNIT_POWER_CONDITION_MODIFIER_SHIFT 0
+
+#define SCSI_START_STOP_UNIT_POWER_CONDITION_MASK 0xF0
+#define SCSI_START_STOP_UNIT_POWER_CONDITION_SHIFT 4
+
+#define SCSI_LOG_SENSE_PC_FIELD_MASK 0xC0
+#define SCSI_LOG_SENSE_PC_FIELD_SHIFT 6
+
+#define SCSI_LOG_SENSE_PAGE_CODE_FIELD_MASK 0x3F
+#define SCSI_LOG_SENSE_PAGE_CODE_FIELD_SHIFT 0
+
+/**
+ *
+ *
+ * MRIE - Method of reporting informational exceptions codes
+ */
+#define NO_REPORTING_INFO_EXCEPTION_CONDITION 0x0
+#define ASYNCHRONOUS_EVENT_REPORTING 0x1
+#define ESTABLISH_UNIT_ATTENTION_CONDITION 0x2
+#define CONDITIONALLY_GENERATE_RECOVERED_ERROR 0x3
+#define UNCONDITIONALLY_GENERATE_RECOVERED_ERROR 0x4
+#define GENERATE_NO_SENSE 0x5
+#define REPORT_INFO_EXCEPTION_CONDITION_ON_REQUEST 0x6
+
+#define SCSI_INFORMATION_EXCEPTION_DEXCPT_BIT 0x08
+
+/* Reassign Blocks masks */
+#define SCSI_REASSIGN_BLOCKS_LONGLBA_BIT 0x02
+#define SCSI_REASSIGN_BLOCKS_LONGLIST_BIT 0x01
+
+#endif /* _SCSI_H_ */
+
diff --git a/drivers/scsi/isci/core/sati_device.h b/drivers/scsi/isci/core/sati_device.h
new file mode 100644
index 000000000000..4d1cfde12cae
--- /dev/null
+++ b/drivers/scsi/isci/core/sati_device.h
@@ -0,0 +1,156 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SATI_DEVICE_H_
+#define _SATI_DEVICE_H_
+
+/**
+ * This file contains all of the defintions for the SATI remote device object.
+ * Some translations require information to be remembered on a per device
+ * basis. This information is stored in the object defined in this file.
+ *
+ *
+ */
+
+#include "sati_types.h"
+#include "intel_ata.h"
+
+/**
+ * enum _SATI_DEVICE_STATE - This enumeration depicts the various states
+ * possible for the a translation remote device object.
+ *
+ *
+ */
+enum sati_device_state {
+ SATI_DEVICE_STATE_OPERATIONAL,
+ SATI_DEVICE_STATE_STOPPED,
+ SATI_DEVICE_STATE_STANDBY,
+ SATI_DEVICE_STATE_IDLE,
+ SATI_DEVICE_STATE_DEVICE_FAULT_OCCURRED,
+ SATI_DEVICE_STATE_FORMAT_UNIT_IN_PROGRESS,
+ SATI_DEVICE_STATE_SELF_TEST_IN_PROGRESS,
+ SATI_DEVICE_STATE_SEQUENCE_INCOMPLETE,
+ SATI_DEVICE_STATE_UNIT_ATTENTION_CONDITION
+
+};
+
+/**
+ *
+ *
+ * SATI_DEVICE_CAPABILITIES These constants define the various capabilities
+ * that a remote device may support for which there is an impact on translation.
+ */
+#define SATI_DEVICE_CAP_UDMA_ENABLE 0x00000001
+#define SATI_DEVICE_CAP_NCQ_REQUESTED_ENABLE 0x00000002
+#define SATI_DEVICE_CAP_NCQ_SUPPORTED_ENABLE 0x00000004
+#define SATI_DEVICE_CAP_48BIT_ENABLE 0x00000008
+#define SATI_DEVICE_CAP_DMA_FUA_ENABLE 0x00000010
+#define SATI_DEVICE_CAP_SMART_SUPPORT 0x00000020
+#define SATI_DEVICE_CAP_REMOVABLE_MEDIA 0x00000040
+#define SATI_DEVICE_CAP_SMART_ENABLE 0x00000080
+#define SATI_DEVICE_CAP_WRITE_UNCORRECTABLE_ENABLE 0x00000100
+#define SATI_DEVICE_CAP_MULTIPLE_SECTORS_PER_PHYSCIAL_SECTOR 0x00000200
+#define SATI_DEVICE_CAP_SMART_SELF_TEST_SUPPORT 0x00000400
+
+
+/**
+ * struct sati_device - The SATI_DEVICE structure define the state of the
+ * remote device with respect to translation.
+ *
+ *
+ */
+struct sati_device {
+ /**
+ * This field simply dictates the state of the SATI device.
+ */
+ enum sati_device_state state;
+
+ /**
+ * This field indicates features supported by the remote device that
+ * impact translation execution.
+ */
+ u16 capabilities;
+
+ /**
+ * This field indicates the depth of the native command queue supported
+ * by the device.
+ */
+ u8 ncq_depth;
+
+ /**
+ * This field stores the additional sense code for a unit attention
+ * condition.
+ */
+ u8 unit_attention_asc;
+
+ /**
+ * This field indicates the additional sense code qualifier for a unit
+ * attention condition.
+ */
+ u8 unit_attention_ascq;
+
+};
+
+void sati_device_construct(
+ struct sati_device *device,
+ bool is_ncq_enabled,
+ u8 max_ncq_depth);
+
+void sati_device_update_capabilities(
+ struct sati_device *device,
+ struct ata_identify_device_data *identify);
+
+#endif /* _SATI_TRANSLATOR_SEQUENCE_H_ */
+
diff --git a/drivers/scsi/isci/core/sati_translator_sequence.h b/drivers/scsi/isci/core/sati_translator_sequence.h
new file mode 100644
index 000000000000..592570d50ebd
--- /dev/null
+++ b/drivers/scsi/isci/core/sati_translator_sequence.h
@@ -0,0 +1,304 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SATI_TRANSLATOR_SEQUENCE_H_
+#define _SATI_TRANSLATOR_SEQUENCE_H_
+
+/**
+ * This file contains all of the defintions for the SATI translator sequence.
+ * A translator sequence is simply a defintion for the various sequences of
+ * commands that occur in this translator.
+ *
+ *
+ */
+
+#include "sati_device.h"
+
+/**
+ * enum _SATI_TRANSLATOR_SEQUENCE_TYPE - This enumeration defines the possible
+ * sequence types for the translator.
+ *
+ *
+ */
+enum sati_translator_sequence_type {
+ /* SCSI Primary Command (SPC) sequences. */
+ SATI_SEQUENCE_REPORT_LUNS,
+ SATI_SEQUENCE_TEST_UNIT_READY,
+ SATI_SEQUENCE_INQUIRY_STANDARD,
+ SATI_SEQUENCE_INQUIRY_SUPPORTED_PAGES,
+ SATI_SEQUENCE_INQUIRY_SERIAL_NUMBER,
+ SATI_SEQUENCE_INQUIRY_DEVICE_ID,
+ SATI_SEQUENCE_INQUIRY_BLOCK_DEVICE,
+ SATI_SEQUENCE_MODE_SENSE_6_CACHING,
+ SATI_SEQUENCE_MODE_SENSE_6_INFORMATIONAL_EXCP_CONTROL,
+ SATI_SEQUENCE_MODE_SENSE_6_READ_WRITE_ERROR,
+ SATI_SEQUENCE_MODE_SENSE_6_DISCONNECT_RECONNECT,
+ SATI_SEQUENCE_MODE_SENSE_6_CONTROL,
+ SATI_SEQUENCE_MODE_SENSE_6_ALL_PAGES,
+ SATI_SEQUENCE_MODE_SENSE_10_CACHING,
+ SATI_SEQUENCE_MODE_SENSE_10_INFORMATIONAL_EXCP_CONTROL,
+ SATI_SEQUENCE_MODE_SENSE_10_READ_WRITE_ERROR,
+ SATI_SEQUENCE_MODE_SENSE_10_DISCONNECT_RECONNECT,
+ SATI_SEQUENCE_MODE_SENSE_10_CONTROL,
+ SATI_SEQUENCE_MODE_SENSE_10_ALL_PAGES,
+ SATI_SEQUENCE_MODE_SELECT_MODE_PAGE_CACHING,
+ SATI_SEQUENCE_MODE_SELECT_MODE_POWER_CONDITION,
+ SATI_SEQUENCE_MODE_SELECT_MODE_INFORMATION_EXCEPT_CONTROL,
+
+ /* Log Sense Sequences */
+ SATI_SEQUENCE_LOG_SENSE_SELF_TEST_LOG_PAGE,
+ SATI_SEQUENCE_LOG_SENSE_EXTENDED_SELF_TEST_LOG_PAGE,
+ SATI_SEQUENCE_LOG_SENSE_SUPPORTED_LOG_PAGE,
+ SATI_SEQUENCE_LOG_SENSE_INFO_EXCEPTION_LOG_PAGE,
+
+ /* SCSI Block Command (SBC) sequences. */
+
+ SATI_SEQUENCE_READ_6,
+ SATI_SEQUENCE_READ_10,
+ SATI_SEQUENCE_READ_12,
+ SATI_SEQUENCE_READ_16,
+
+ SATI_SEQUENCE_READ_CAPACITY_10,
+ SATI_SEQUENCE_READ_CAPACITY_16,
+
+ SATI_SEQUENCE_SYNCHRONIZE_CACHE,
+
+ SATI_SEQUENCE_VERIFY_10,
+ SATI_SEQUENCE_VERIFY_12,
+ SATI_SEQUENCE_VERIFY_16,
+
+ SATI_SEQUENCE_WRITE_6,
+ SATI_SEQUENCE_WRITE_10,
+ SATI_SEQUENCE_WRITE_12,
+ SATI_SEQUENCE_WRITE_16,
+
+ SATI_SEQUENCE_START_STOP_UNIT,
+
+ SATI_SEQUENCE_REASSIGN_BLOCKS,
+
+ /* SCSI Task Requests sequences */
+
+ SATI_SEQUENCE_LUN_RESET,
+
+ SATI_SEQUENCE_REQUEST_SENSE_SMART_RETURN_STATUS,
+ SATI_SEQUENCE_REQUEST_SENSE_CHECK_POWER_MODE,
+
+ SATI_SEQUENCE_WRITE_LONG
+
+};
+
+#define SATI_SEQUENCE_TYPE_READ_MIN SATI_SEQUENCE_READ_6
+#define SATI_SEQUENCE_TYPE_READ_MAX SATI_SEQUENCE_READ_16
+
+/**
+ *
+ *
+ * SATI_SEQUENCE_STATES These constants depict the various state values
+ * associated with a translation sequence.
+ */
+#define SATI_SEQUENCE_STATE_INITIAL 0
+#define SATI_SEQUENCE_STATE_TRANSLATE_DATA 1
+#define SATI_SEQUENCE_STATE_AWAIT_RESPONSE 2
+#define SATI_SEQUENCE_STATE_FINAL 3
+#define SATI_SEQUENCE_STATE_INCOMPLETE 4
+
+/**
+ *
+ *
+ * SATI_DATA_DIRECTIONS These constants depict the various types of data
+ * directions for a translation sequence. Data can flow in/out (read/write) or
+ * no data at all.
+ */
+#define SATI_DATA_DIRECTION_NONE 0
+#define SATI_DATA_DIRECTION_IN 1
+#define SATI_DATA_DIRECTION_OUT 2
+
+/**
+ * struct SATI_MODE_SELECT_PROCESSING_STATE - This structure contains all of
+ * the current processing states for processing mode select 6 and 10
+ * commands' parameter fields.
+ *
+ *
+ */
+typedef struct SATI_MODE_SELECT_PROCESSING_STATE {
+ u8 *mode_pages;
+ u32 mode_page_offset;
+ u32 mode_pages_size;
+ u32 size_of_data_processed;
+ u32 total_ata_command_sent;
+ u32 ata_command_sent_for_cmp; /* cmp: current mode page */
+ bool current_mode_page_processed;
+
+} SATI_MODE_SELECT_PROCESSING_STATE_T;
+
+
+enum SATI_REASSIGN_BLOCKS_ATA_COMMAND_STATUS {
+ SATI_REASSIGN_BLOCKS_READY_TO_SEND,
+ SATI_REASSIGN_BLOCKS_COMMAND_FAIL,
+ SATI_REASSIGN_BLOCKS_COMMAND_SUCCESS,
+};
+
+/**
+ * struct sati_reassign_blocks_processing_state - This structure contains all
+ * of the current processing states for processing reassign block command's
+ * parameter fields.
+ *
+ *
+ */
+struct sati_reassign_blocks_processing_state {
+ u32 lba_offset;
+ u32 block_lists_size;
+ u8 lba_size;
+ u32 size_of_data_processed;
+ u32 ata_command_sent_for_current_lba;
+ bool current_lba_processed;
+ enum SATI_REASSIGN_BLOCKS_ATA_COMMAND_STATUS ata_command_status;
+
+};
+
+#define SATI_ATAPI_REQUEST_SENSE_CDB_LENGTH 12
+
+/**
+ * struct sati_atapi_data - The SATI_ATAPI_DATA structure is for sati atapi IO
+ * specific data.
+ *
+ *
+ */
+struct sati_atapi_data {
+ u8 request_sense_cdb[SATI_ATAPI_REQUEST_SENSE_CDB_LENGTH];
+};
+
+/**
+ * struct sati_translator_sequence - This structure contains all of the
+ * translation information associated with a particular request.
+ *
+ *
+ */
+struct sati_translator_sequence {
+ /**
+ * This field contains the sequence type determined by the SATI.
+ */
+ u8 type;
+
+ /**
+ * This field indicates the current state for the sequence.
+ */
+ u8 state;
+
+ /**
+ * This field indicates the data direction (none, read, or write) for
+ * the translated request.
+ */
+ u8 data_direction;
+
+ /**
+ * This field contains the SATA/ATA protocol to be utilized during
+ * the IO transfer.
+ */
+ u8 protocol;
+
+ /**
+ * This field is utilized for sequences requiring data translation.
+ * It specifies the amount of data requested by the caller from the
+ * operation. It's necessary, because at times the user requests less
+ * data than is available. Thus, we need to avoid overrunning the
+ * buffer.
+ */
+ u32 allocation_length;
+
+ /**
+ * This field specifies the amount of data that will actually be
+ * transfered across the wire for this ATA request.
+ */
+ u32 ata_transfer_length;
+
+ /**
+ * This field specifies the amount of data bytes that have been
+ * set in a translation sequence. It will be incremented every time
+ * a data byte has been set by a sati translation.
+ */
+ u16 number_data_bytes_set;
+
+ /**
+ * This field indicates whether or not the sense response has been set
+ * by the translation sequence.
+ */
+ bool is_sense_response_set;
+
+ /**
+ * This field specifies the remote device context for which this
+ * translator sequence is destined.
+ */
+ struct sati_device *device;
+
+ /**
+ * This field is utilized to provide the translator with memory space
+ * required for translations that utilize multiple requests.
+ */
+ union {
+ u32 translated_command;
+ u32 move_sector_count;
+ u32 scratch;
+ struct sati_reassign_blocks_processing_state reassign_blocks_process_state;
+ SATI_MODE_SELECT_PROCESSING_STATE_T process_state;
+ struct sati_atapi_data sati_atapi_data;
+ } command_specific_data;
+
+};
+
+
+
+#endif /* _SATI_TRANSLATOR_SEQUENCE_H_ */
+
diff --git a/drivers/scsi/isci/core/sati_types.h b/drivers/scsi/isci/core/sati_types.h
new file mode 100644
index 000000000000..b6159e06c280
--- /dev/null
+++ b/drivers/scsi/isci/core/sati_types.h
@@ -0,0 +1,145 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SATI_TYPES_H_
+#define _SATI_TYPES_H_
+
+/**
+ * This file contains various type definitions to be utilized with SCSI to ATA
+ * Translation Implementation.
+ *
+ *
+ */
+
+/**
+ * enum _SATI_STATUS - This enumeration defines the possible return values from
+ * the SATI translation methods.
+ *
+ *
+ */
+enum sati_status {
+ /**
+ * This indicates that the translation was supported and occurred
+ * without error.
+ */
+ SATI_SUCCESS,
+
+ /**
+ * This indicates that the translation was supported, occurred without
+ * error, and no additional translation is necessary. This is done in
+ * conditions where the SCSI command doesn't require any interaction with
+ * the remote device.
+ */
+ SATI_COMPLETE,
+
+ /**
+ * This indicated everything SATI_COMPLETE does in addition to the response data
+ * not using all the memory allocated by the OS.
+ */
+ SATI_COMPLETE_IO_DONE_EARLY,
+
+ /**
+ * This indicates that translator sequence has finished some specific
+ * command in the sequence, but additional commands are necessary.
+ */
+ SATI_SEQUENCE_INCOMPLETE,
+
+ /**
+ * This indicates a general failure has occurred for which no further
+ * specification information is available.
+ */
+ SATI_FAILURE,
+
+ /**
+ * This indicates that the result of the IO request indicates a
+ * failure. The caller should reference the corresponding response
+ * data for further details.
+ */
+ SATI_FAILURE_CHECK_RESPONSE_DATA,
+
+ /**
+ * This status indicates that the supplied sequence type doesn't map
+ * to an existing definition.
+ */
+ SATI_FAILURE_INVALID_SEQUENCE_TYPE,
+
+ /**
+ * This status indicates that the supplied sequence state doesn't match
+ * the operation being requested by the user.
+ */
+ SATI_FAILURE_INVALID_STATE
+
+};
+
+#if (!defined(DISABLE_SATI_MODE_SENSE) \
+ || !defined(DISABLE_SATI_MODE_SELECT) \
+ || !defined(DISABLE_SATI_REQUEST_SENSE)) \
+
+#if !defined(ENABLE_SATI_MODE_PAGES)
+/**
+ *
+ *
+ * This macro enables the common mode page data structures and code. Currently,
+ * MODE SENSE, MODE SELECT, and REQUEST SENSE all make reference to this common
+ * code. As a result, enable the common mode page code if any of these 3 are
+ * being translated.
+ */
+#define ENABLE_SATI_MODE_PAGES
+#endif /* !defined(ENABLE_SATI_MODE_PAGES) */
+
+#endif /* MODE_SENSE/SELECT/REQUEST_SENSE */
+
+#endif /* _SATI_TYPES_H_ */
+
diff --git a/drivers/scsi/isci/core/sci_base_controller.h b/drivers/scsi/isci/core/sci_base_controller.h
new file mode 100644
index 000000000000..36c53406ea5a
--- /dev/null
+++ b/drivers/scsi/isci/core/sci_base_controller.h
@@ -0,0 +1,306 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCI_BASE_CONTROLLER_H_
+#define _SCI_BASE_CONTROLLER_H_
+
+#include "intel_sas.h"
+#include "sci_controller_constants.h"
+#include "sci_base_state.h"
+#include "sci_base_memory_descriptor_list.h"
+#include "sci_base_state_machine.h"
+#include "sci_object.h"
+
+struct sci_base_memory_descriptor_list;
+
+/**
+ * enum sci_base_controller_states - This enumeration depicts all the states
+ * for the common controller state machine.
+ *
+ *
+ */
+enum sci_base_controller_states {
+ /**
+ * Simply the initial state for the base controller state machine.
+ */
+ SCI_BASE_CONTROLLER_STATE_INITIAL = 0,
+
+ /**
+ * This state indicates that the controller is reset. The memory for
+ * the controller is in it's initial state, but the controller requires
+ * initialization.
+ * This state is entered from the INITIAL state.
+ * This state is entered from the RESETTING state.
+ */
+ SCI_BASE_CONTROLLER_STATE_RESET,
+
+ /**
+ * This state is typically an action state that indicates the controller
+ * is in the process of initialization. In this state no new IO operations
+ * are permitted.
+ * This state is entered from the RESET state.
+ */
+ SCI_BASE_CONTROLLER_STATE_INITIALIZING,
+
+ /**
+ * This state indicates that the controller has been successfully
+ * initialized. In this state no new IO operations are permitted.
+ * This state is entered from the INITIALIZING state.
+ */
+ SCI_BASE_CONTROLLER_STATE_INITIALIZED,
+
+ /**
+ * This state indicates the the controller is in the process of becoming
+ * ready (i.e. starting). In this state no new IO operations are permitted.
+ * This state is entered from the INITIALIZED state.
+ */
+ SCI_BASE_CONTROLLER_STATE_STARTING,
+
+ /**
+ * This state indicates the controller is now ready. Thus, the user
+ * is able to perform IO operations on the controller.
+ * This state is entered from the STARTING state.
+ */
+ SCI_BASE_CONTROLLER_STATE_READY,
+
+ /**
+ * This state is typically an action state that indicates the controller
+ * is in the process of resetting. Thus, the user is unable to perform
+ * IO operations on the controller. A reset is considered destructive in
+ * most cases.
+ * This state is entered from the READY state.
+ * This state is entered from the FAILED state.
+ * This state is entered from the STOPPED state.
+ */
+ SCI_BASE_CONTROLLER_STATE_RESETTING,
+
+ /**
+ * This state indicates that the controller is in the process of stopping.
+ * In this state no new IO operations are permitted, but existing IO
+ * operations are allowed to complete.
+ * This state is entered from the READY state.
+ */
+ SCI_BASE_CONTROLLER_STATE_STOPPING,
+
+ /**
+ * This state indicates that the controller has successfully been stopped.
+ * In this state no new IO operations are permitted.
+ * This state is entered from the STOPPING state.
+ */
+ SCI_BASE_CONTROLLER_STATE_STOPPED,
+
+ /**
+ * This state indicates that the controller could not successfully be
+ * initialized. In this state no new IO operations are permitted.
+ * This state is entered from the INITIALIZING state.
+ * This state is entered from the STARTING state.
+ * This state is entered from the STOPPING state.
+ * This state is entered from the RESETTING state.
+ */
+ SCI_BASE_CONTROLLER_STATE_FAILED,
+
+ SCI_BASE_CONTROLLER_MAX_STATES
+
+};
+
+/**
+ * struct sci_base_controller - The base controller object abstracts the fields
+ * common to all SCI controller objects.
+ *
+ *
+ */
+struct sci_base_controller {
+ /**
+ * The field specifies that the parent object for the base controller
+ * is the base object itself.
+ */
+ struct sci_base_object parent;
+
+ /**
+ * This field points to the memory descriptor list associated with this
+ * controller. The MDL indicates the memory requirements necessary for
+ * this controller object.
+ */
+ struct sci_base_memory_descriptor_list mdl;
+
+ /**
+ * This field contains the information for the base controller state
+ * machine.
+ */
+ struct sci_base_state_machine state_machine;
+};
+
+/* Forward declarations */
+struct sci_base_remote_device;
+struct sci_base_request;
+
+typedef enum sci_status
+(*sci_base_controller_handler_t)(struct sci_base_controller *);
+
+typedef enum sci_status
+(*sci_base_controller_timed_handler_t)(struct sci_base_controller *, u32);
+
+typedef enum sci_status
+(*sci_base_controller_request_handler_t)(struct sci_base_controller *,
+ struct sci_base_remote_device *,
+ struct sci_base_request *);
+
+typedef enum sci_status
+(*sci_base_controller_start_request_handler_t)(struct sci_base_controller *,
+ struct sci_base_remote_device *,
+ struct sci_base_request *, u16);
+
+/**
+ * struct sci_base_controller_state_handler - This structure contains all of
+ * the state handler methods common to base controller state machines.
+ * Handler methods provide the ability to change the behavior for user
+ * requests or transitions depending on the state the machine is in.
+ *
+ *
+ */
+struct sci_base_controller_state_handler {
+ /**
+ * The start_handler specifies the method invoked when a user attempts to
+ * start a controller.
+ */
+ sci_base_controller_timed_handler_t start;
+
+ /**
+ * The stop_handler specifies the method invoked when a user attempts to
+ * stop a controller.
+ */
+ sci_base_controller_timed_handler_t stop;
+
+ /**
+ * The reset_handler specifies the method invoked when a user attempts to
+ * reset a controller.
+ */
+ sci_base_controller_handler_t reset;
+
+ /**
+ * The initialize_handler specifies the method invoked when a user
+ * attempts to initialize a controller.
+ */
+ sci_base_controller_handler_t initialize;
+
+ /**
+ * The start_io_handler specifies the method invoked when a user
+ * attempts to start an IO request for a controller.
+ */
+ sci_base_controller_start_request_handler_t start_io;
+
+ /**
+ * The complete_io_handler specifies the method invoked when a user
+ * attempts to complete an IO request for a controller.
+ */
+ sci_base_controller_request_handler_t complete_io;
+
+ /**
+ * The continue_io_handler specifies the method invoked when a user
+ * attempts to continue an IO request for a controller.
+ */
+ sci_base_controller_request_handler_t continue_io;
+
+ /**
+ * The start_task_handler specifies the method invoked when a user
+ * attempts to start a task management request for a controller.
+ */
+ sci_base_controller_start_request_handler_t start_task;
+
+ /**
+ * The complete_task_handler specifies the method invoked when a user
+ * attempts to complete a task management request for a controller.
+ */
+ sci_base_controller_request_handler_t complete_task;
+
+};
+
+/**
+ * sci_base_controller_construct() - Construct the base controller
+ * @this_controller: This parameter specifies the base controller to be
+ * constructed.
+ * @state_table: This parameter specifies the table of state definitions to be
+ * utilized for the controller state machine.
+ * @mde_array: This parameter specifies the array of memory descriptor entries
+ * to be managed by this list.
+ * @mde_array_length: This parameter specifies the size of the array of entries.
+ * @next_mdl: This parameter specifies a subsequent MDL object to be managed by
+ * this MDL object.
+ * @oem_parameters: This parameter specifies the original equipment
+ * manufacturer parameters to be utilized by this controller object.
+ *
+ */
+static inline void sci_base_controller_construct(
+ struct sci_base_controller *scic_base,
+ const struct sci_base_state *state_table,
+ struct sci_physical_memory_descriptor *mdes,
+ u32 mde_count,
+ struct sci_base_memory_descriptor_list *next_mdl)
+{
+ scic_base->parent.private = NULL;
+
+ sci_base_state_machine_construct(
+ &scic_base->state_machine,
+ &scic_base->parent,
+ state_table,
+ SCI_BASE_CONTROLLER_STATE_INITIAL
+ );
+
+ sci_base_mdl_construct(&scic_base->mdl, mdes, mde_count, next_mdl);
+
+ sci_base_state_machine_start(&scic_base->state_machine);
+}
+
+#endif /* _SCI_BASE_CONTROLLER_H_ */
diff --git a/drivers/scsi/isci/core/sci_base_memory_descriptor_list.c b/drivers/scsi/isci/core/sci_base_memory_descriptor_list.c
new file mode 100644
index 000000000000..86ae6a855399
--- /dev/null
+++ b/drivers/scsi/isci/core/sci_base_memory_descriptor_list.c
@@ -0,0 +1,159 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * This file contains the base implementation for the memory descriptor list.
+ * This is currently comprised of MDL iterator methods.
+ *
+ *
+ */
+
+#include "sci_environment.h"
+#include "sci_base_memory_descriptor_list.h"
+
+/*
+ * ******************************************************************************
+ * * P U B L I C M E T H O D S
+ * ****************************************************************************** */
+
+void sci_mdl_first_entry(
+ struct sci_base_memory_descriptor_list *base_mdl)
+{
+ base_mdl->next_index = 0;
+
+ /*
+ * If this MDL is managing another MDL, then recursively rewind that MDL
+ * object as well. */
+ if (base_mdl->next_mdl != SCI_INVALID_HANDLE)
+ sci_mdl_first_entry(base_mdl->next_mdl);
+}
+
+
+void sci_mdl_next_entry(
+ struct sci_base_memory_descriptor_list *base_mdl)
+{
+ /*
+ * If there is at least one more entry left in the array, then change
+ * the next pointer to it. */
+ if (base_mdl->next_index < base_mdl->length)
+ base_mdl->next_index++;
+ else if (base_mdl->next_index == base_mdl->length) {
+ /*
+ * This MDL has exhausted it's set of entries. If this MDL is managing
+ * another MDL, then start iterating through that MDL. */
+ if (base_mdl->next_mdl != SCI_INVALID_HANDLE)
+ sci_mdl_next_entry(base_mdl->next_mdl);
+ }
+}
+
+
+struct sci_physical_memory_descriptor *sci_mdl_get_current_entry(
+ struct sci_base_memory_descriptor_list *base_mdl)
+{
+ if (base_mdl->next_index < base_mdl->length)
+ return &base_mdl->mde_array[base_mdl->next_index];
+ else if (base_mdl->next_index == base_mdl->length) {
+ /*
+ * This MDL has exhausted it's set of entries. If this MDL is managing
+ * another MDL, then return it's current entry. */
+ if (base_mdl->next_mdl != SCI_INVALID_HANDLE)
+ return sci_mdl_get_current_entry(base_mdl->next_mdl);
+ }
+
+ return NULL;
+}
+
+/*
+ * ******************************************************************************
+ * * P R O T E C T E D M E T H O D S
+ * ****************************************************************************** */
+
+void sci_base_mdl_construct(
+ struct sci_base_memory_descriptor_list *mdl,
+ struct sci_physical_memory_descriptor *mde_array,
+ u32 mde_array_length,
+ struct sci_base_memory_descriptor_list *next_mdl)
+{
+ mdl->length = mde_array_length;
+ mdl->mde_array = mde_array;
+ mdl->next_index = 0;
+ mdl->next_mdl = next_mdl;
+}
+
+/* --------------------------------------------------------------------------- */
+
+bool sci_base_mde_is_valid(
+ struct sci_physical_memory_descriptor *mde,
+ u32 alignment,
+ u32 size,
+ u16 attributes)
+{
+ /* Only need the lower 32 bits to ensure alignment is met. */
+ u32 physical_address = lower_32_bits(mde->physical_address);
+
+ if (
+ ((((unsigned long)mde->virtual_address) & (alignment - 1)) != 0)
+ || ((physical_address & (alignment - 1)) != 0)
+ || (mde->constant_memory_alignment != alignment)
+ || (mde->constant_memory_size != size)
+ || (mde->virtual_address == NULL)
+ || (mde->constant_memory_attributes != attributes)
+ ) {
+ return false;
+ }
+
+ return true;
+}
+
diff --git a/drivers/scsi/isci/core/sci_base_memory_descriptor_list.h b/drivers/scsi/isci/core/sci_base_memory_descriptor_list.h
new file mode 100644
index 000000000000..257d6e368b4a
--- /dev/null
+++ b/drivers/scsi/isci/core/sci_base_memory_descriptor_list.h
@@ -0,0 +1,155 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCI_BASE_MEMORY_DESCRIPTOR_LIST_H_
+#define _SCI_BASE_MEMORY_DESCRIPTOR_LIST_H_
+
+/**
+ * This file contains the protected interface structures, constants and
+ * interface methods for the struct sci_base_memory_descriptor_list object.
+ *
+ *
+ */
+
+
+#include "sci_types.h"
+#include "sci_memory_descriptor_list.h"
+
+
+/**
+ * struct sci_base_memory_descriptor_list - This structure contains all of the
+ * fields necessary to implement a simple stack for managing the list of
+ * available controller indices.
+ *
+ *
+ */
+struct sci_base_memory_descriptor_list {
+ /**
+ * This field indicates the length of the memory descriptor entry array.
+ */
+ u32 length;
+
+ /**
+ * This field is utilized to provide iterator pattern functionality.
+ * It indicates the index of the next memory descriptor in the iteration.
+ */
+ u32 next_index;
+
+ /**
+ * This field will point to the list of memory descriptors.
+ */
+ struct sci_physical_memory_descriptor *mde_array;
+
+ /**
+ * This field simply allows a user to chain memory descriptor lists
+ * together if desired. This field will be initialized to
+ * SCI_INVALID_HANDLE.
+ */
+ struct sci_base_memory_descriptor_list *next_mdl;
+
+};
+
+/**
+ * sci_base_mdl_construct() - This method is invoked to construct an memory
+ * descriptor list. It initializes the fields of the MDL.
+ * @mdl: This parameter specifies the memory descriptor list to be constructed.
+ * @mde_array: This parameter specifies the array of memory descriptor entries
+ * to be managed by this list.
+ * @mde_array_length: This parameter specifies the size of the array of entries.
+ * @next_mdl: This parameter specifies a subsequent MDL object to be managed by
+ * this MDL object.
+ *
+ * none.
+ */
+void sci_base_mdl_construct(
+ struct sci_base_memory_descriptor_list *mdl,
+ struct sci_physical_memory_descriptor *mde_array,
+ u32 mde_array_length,
+ struct sci_base_memory_descriptor_list *next_mdl);
+
+/**
+ * sci_base_mde_construct() -
+ *
+ * This macro constructs an memory descriptor entry with the given alignment
+ * and size
+ */
+#define sci_base_mde_construct(mde, alignment, size, attributes) \
+ { \
+ (mde)->constant_memory_alignment = (alignment); \
+ (mde)->constant_memory_size = (size); \
+ (mde)->constant_memory_attributes = (attributes); \
+ }
+
+/**
+ * sci_base_mde_is_valid() - This method validates that the memory descriptor
+ * is correctly filled out by the SCI User
+ * @mde: This parameter is the mde entry to validate
+ * @alignment: This parameter specifies the expected alignment of the memory
+ * for the mde.
+ * @size: This parameter specifies the memory size expected for the mde its
+ * value should not have been changed by the SCI User.
+ * @attributes: This parameter specifies the attributes for the memory
+ * descriptor provided.
+ *
+ * bool This method returns an indication as to whether the supplied MDE is
+ * valid or not. true The MDE is valid. false The MDE is not valid.
+ */
+bool sci_base_mde_is_valid(
+ struct sci_physical_memory_descriptor *mde,
+ u32 alignment,
+ u32 size,
+ u16 attributes);
+
+#endif /* _SCI_BASE_MEMORY_DESCRIPTOR_LIST_H_ */
diff --git a/drivers/scsi/isci/core/sci_base_phy.h b/drivers/scsi/isci/core/sci_base_phy.h
new file mode 100644
index 000000000000..6c0d9bbbc95f
--- /dev/null
+++ b/drivers/scsi/isci/core/sci_base_phy.h
@@ -0,0 +1,205 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCI_BASE_PHY_H_
+#define _SCI_BASE_PHY_H_
+
+/**
+ * This file contains all of the structures, constants, and methods common to
+ * all phy object definitions.
+ *
+ *
+ */
+
+#include "sci_base_state_machine.h"
+
+/**
+ * enum sci_base_phy_states - This enumeration depicts the standard states
+ * common to all phy state machine implementations.
+ *
+ *
+ */
+enum sci_base_phy_states {
+ /**
+ * Simply the initial state for the base domain state machine.
+ */
+ SCI_BASE_PHY_STATE_INITIAL,
+
+ /**
+ * This state indicates that the phy has successfully been stopped.
+ * In this state no new IO operations are permitted on this phy.
+ * This state is entered from the INITIAL state.
+ * This state is entered from the STARTING state.
+ * This state is entered from the READY state.
+ * This state is entered from the RESETTING state.
+ */
+ SCI_BASE_PHY_STATE_STOPPED,
+
+ /**
+ * This state indicates that the phy is in the process of becomming
+ * ready. In this state no new IO operations are permitted on this phy.
+ * This state is entered from the STOPPED state.
+ * This state is entered from the READY state.
+ * This state is entered from the RESETTING state.
+ */
+ SCI_BASE_PHY_STATE_STARTING,
+
+ /**
+ * This state indicates the the phy is now ready. Thus, the user
+ * is able to perform IO operations utilizing this phy as long as it
+ * is currently part of a valid port.
+ * This state is entered from the STARTING state.
+ */
+ SCI_BASE_PHY_STATE_READY,
+
+ /**
+ * This state indicates that the phy is in the process of being reset.
+ * In this state no new IO operations are permitted on this phy.
+ * This state is entered from the READY state.
+ */
+ SCI_BASE_PHY_STATE_RESETTING,
+
+ /**
+ * Simply the final state for the base phy state machine.
+ */
+ SCI_BASE_PHY_STATE_FINAL,
+
+ SCI_BASE_PHY_MAX_STATES
+
+};
+
+/**
+ * struct sci_base_phy - This structure defines all of the fields common to PHY
+ * objects.
+ *
+ *
+ */
+struct sci_base_phy {
+ /**
+ * This field depicts the parent object (struct sci_base_object) for the phy.
+ */
+ struct sci_base_object parent;
+
+ /**
+ * This field contains the information for the base phy state machine.
+ */
+ struct sci_base_state_machine state_machine;
+};
+
+typedef enum sci_status (*SCI_BASE_PHY_HANDLER_T)(
+ struct sci_base_phy *
+ );
+
+/**
+ * struct sci_base_phy_state_handler - This structure contains all of the state
+ * handler methods common to base phy state machines. Handler methods
+ * provide the ability to change the behavior for user requests or
+ * transitions depending on the state the machine is in.
+ *
+ *
+ */
+struct sci_base_phy_state_handler {
+ /**
+ * The start_handler specifies the method invoked when there is an
+ * attempt to start a phy.
+ */
+ SCI_BASE_PHY_HANDLER_T start_handler;
+
+ /**
+ * The stop_handler specifies the method invoked when there is an
+ * attempt to stop a phy.
+ */
+ SCI_BASE_PHY_HANDLER_T stop_handler;
+
+ /**
+ * The reset_handler specifies the method invoked when there is an
+ * attempt to reset a phy.
+ */
+ SCI_BASE_PHY_HANDLER_T reset_handler;
+
+ /**
+ * The destruct_handler specifies the method invoked when attempting to
+ * destruct a phy.
+ */
+ SCI_BASE_PHY_HANDLER_T destruct_handler;
+
+};
+
+/**
+ * sci_base_phy_construct() - Construct the base phy
+ * @this_phy: This parameter specifies the base phy to be constructed.
+ * @state_table: This parameter specifies the table of state definitions to be
+ * utilized for the phy state machine.
+ *
+ */
+static inline void sci_base_phy_construct(
+ struct sci_base_phy *base_phy,
+ const struct sci_base_state *state_table)
+{
+ base_phy->parent.private = NULL;
+ sci_base_state_machine_construct(
+ &base_phy->state_machine,
+ &base_phy->parent,
+ state_table,
+ SCI_BASE_PHY_STATE_INITIAL
+ );
+
+ sci_base_state_machine_start(
+ &base_phy->state_machine
+ );
+}
+
+
+#endif /* _SCI_BASE_PHY_H_ */
diff --git a/drivers/scsi/isci/core/sci_base_port.h b/drivers/scsi/isci/core/sci_base_port.h
new file mode 100644
index 000000000000..4e2031d195f0
--- /dev/null
+++ b/drivers/scsi/isci/core/sci_base_port.h
@@ -0,0 +1,203 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCI_BASE_PORT_H_
+#define _SCI_BASE_PORT_H_
+
+#include "sci_base_state_machine.h"
+#include "sci_object.h"
+
+/**
+ * enum sci_base_port_states - This enumeration depicts all the states for the
+ * common port state machine.
+ *
+ *
+ */
+enum sci_base_port_states {
+ /**
+ * This state indicates that the port has successfully been stopped.
+ * In this state no new IO operations are permitted.
+ * This state is entered from the STOPPING state.
+ */
+ SCI_BASE_PORT_STATE_STOPPED,
+
+ /**
+ * This state indicates that the port is in the process of stopping.
+ * In this state no new IO operations are permitted, but existing IO
+ * operations are allowed to complete.
+ * This state is entered from the READY state.
+ */
+ SCI_BASE_PORT_STATE_STOPPING,
+
+ /**
+ * This state indicates the port is now ready. Thus, the user is
+ * able to perform IO operations on this port.
+ * This state is entered from the STARTING state.
+ */
+ SCI_BASE_PORT_STATE_READY,
+
+ /**
+ * This state indicates the port is in the process of performing a hard
+ * reset. Thus, the user is unable to perform IO operations on this
+ * port.
+ * This state is entered from the READY state.
+ */
+ SCI_BASE_PORT_STATE_RESETTING,
+
+ /**
+ * This state indicates the port has failed a reset request. This state
+ * is entered when a port reset request times out.
+ * This state is entered from the RESETTING state.
+ */
+ SCI_BASE_PORT_STATE_FAILED,
+
+ SCI_BASE_PORT_MAX_STATES
+
+};
+
+/**
+ * struct sci_base_port - The base port object abstracts the fields common to
+ * all SCI port objects.
+ *
+ *
+ */
+struct sci_base_port {
+ /**
+ * The field specifies that the parent object for the base controller
+ * is the base object itself.
+ */
+ struct sci_base_object parent;
+
+ /**
+ * This field contains the information for the base port state machine.
+ */
+ struct sci_base_state_machine state_machine;
+};
+
+struct sci_base_phy;
+
+typedef enum sci_status (*SCI_BASE_PORT_HANDLER_T)(
+ struct sci_base_port *
+ );
+
+typedef enum sci_status (*SCI_BASE_PORT_PHY_HANDLER_T)(
+ struct sci_base_port *,
+ struct sci_base_phy *
+ );
+
+typedef enum sci_status (*SCI_BASE_PORT_RESET_HANDLER_T)(
+ struct sci_base_port *,
+ u32 timeout
+ );
+
+/**
+ * struct sci_base_port_state_handler - This structure contains all of the
+ * state handler methods common to base port state machines. Handler
+ * methods provide the ability to change the behavior for user requests or
+ * transitions depending on the state the machine is in.
+ *
+ *
+ */
+struct sci_base_port_state_handler {
+ /**
+ * The start_handler specifies the method invoked when a user attempts to
+ * start a port.
+ */
+ SCI_BASE_PORT_HANDLER_T start_handler;
+
+ /**
+ * The stop_handler specifies the method invoked when a user attempts to
+ * stop a port.
+ */
+ SCI_BASE_PORT_HANDLER_T stop_handler;
+
+ /**
+ * The destruct_handler specifies the method invoked when attempting to
+ * destruct a port.
+ */
+ SCI_BASE_PORT_HANDLER_T destruct_handler;
+
+ /**
+ * The reset_handler specifies the method invoked when a user attempts to
+ * hard reset a port.
+ */
+ SCI_BASE_PORT_RESET_HANDLER_T reset_handler;
+
+ /**
+ * The add_phy_handler specifies the method invoked when a user attempts to
+ * add another phy into the port.
+ */
+ SCI_BASE_PORT_PHY_HANDLER_T add_phy_handler;
+
+ /**
+ * The remove_phy_handler specifies the method invoked when a user
+ * attempts to remove a phy from the port.
+ */
+ SCI_BASE_PORT_PHY_HANDLER_T remove_phy_handler;
+
+};
+
+/**
+ * sci_base_port_construct() - Construct the base port object
+ * @this_port: This parameter specifies the base port to be constructed.
+ * @state_table: This parameter specifies the table of state definitions to be
+ * utilized for the domain state machine.
+ *
+ */
+void sci_base_port_construct(
+ struct sci_base_port *this_port,
+ const struct sci_base_state *state_table);
+
+#endif /* _SCI_BASE_PORT_H_ */
diff --git a/drivers/scsi/isci/core/sci_base_remote_device.h b/drivers/scsi/isci/core/sci_base_remote_device.h
new file mode 100644
index 000000000000..fe6614b8ef5b
--- /dev/null
+++ b/drivers/scsi/isci/core/sci_base_remote_device.h
@@ -0,0 +1,277 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCI_BASE_REMOTE_DEVICE_H_
+#define _SCI_BASE_REMOTE_DEVICE_H_
+
+/**
+ * This file contains all of the structures, constants, and methods common to
+ * all remote device object definitions.
+ *
+ *
+ */
+
+#include "sci_base_state_machine.h"
+
+struct sci_base_request;
+
+/**
+ * enum sci_base_remote_device_states - This enumeration depicts all the states
+ * for the common remote device state machine.
+ *
+ *
+ */
+enum sci_base_remote_device_states {
+ /**
+ * Simply the initial state for the base remote device state machine.
+ */
+ SCI_BASE_REMOTE_DEVICE_STATE_INITIAL,
+
+ /**
+ * This state indicates that the remote device has successfully been
+ * stopped. In this state no new IO operations are permitted.
+ * This state is entered from the INITIAL state.
+ * This state is entered from the STOPPING state.
+ */
+ SCI_BASE_REMOTE_DEVICE_STATE_STOPPED,
+
+ /**
+ * This state indicates the the remote device is in the process of
+ * becoming ready (i.e. starting). In this state no new IO operations
+ * are permitted.
+ * This state is entered from the STOPPED state.
+ */
+ SCI_BASE_REMOTE_DEVICE_STATE_STARTING,
+
+ /**
+ * This state indicates the remote device is now ready. Thus, the user
+ * is able to perform IO operations on the remote device.
+ * This state is entered from the STARTING state.
+ */
+ SCI_BASE_REMOTE_DEVICE_STATE_READY,
+
+ /**
+ * This state indicates that the remote device is in the process of
+ * stopping. In this state no new IO operations are permitted, but
+ * existing IO operations are allowed to complete.
+ * This state is entered from the READY state.
+ * This state is entered from the FAILED state.
+ */
+ SCI_BASE_REMOTE_DEVICE_STATE_STOPPING,
+
+ /**
+ * This state indicates that the remote device has failed.
+ * In this state no new IO operations are permitted.
+ * This state is entered from the INITIALIZING state.
+ * This state is entered from the READY state.
+ */
+ SCI_BASE_REMOTE_DEVICE_STATE_FAILED,
+
+ /**
+ * This state indicates the device is being reset.
+ * In this state no new IO operations are permitted.
+ * This state is entered from the READY state.
+ */
+ SCI_BASE_REMOTE_DEVICE_STATE_RESETTING,
+
+ /**
+ * Simply the final state for the base remote device state machine.
+ */
+ SCI_BASE_REMOTE_DEVICE_STATE_FINAL,
+
+ SCI_BASE_REMOTE_DEVICE_MAX_STATES
+
+};
+
+/**
+ * struct sci_base_remote_device - The base remote device object abstracts the
+ * fields common to all SCI remote device objects.
+ *
+ *
+ */
+struct sci_base_remote_device {
+ /**
+ * The field specifies that the parent object for the base remote
+ * device is the base object itself.
+ */
+ struct sci_base_object parent;
+
+ /**
+ * This field contains the information for the base remote device state
+ * machine.
+ */
+ struct sci_base_state_machine state_machine;
+};
+
+
+typedef enum sci_status (*SCI_BASE_REMOTE_DEVICE_HANDLER_T)(
+ struct sci_base_remote_device *
+ );
+
+typedef enum sci_status (*SCI_BASE_REMOTE_DEVICE_REQUEST_HANDLER_T)(
+ struct sci_base_remote_device *,
+ struct sci_base_request *
+ );
+
+typedef enum sci_status (*SCI_BASE_REMOTE_DEVICE_HIGH_PRIORITY_REQUEST_COMPLETE_HANDLER_T)(
+ struct sci_base_remote_device *,
+ struct sci_base_request *,
+ void *,
+ enum sci_io_status
+ );
+
+/**
+ * struct sci_base_remote_device_state_handler - This structure contains all of
+ * the state handler methods common to base remote device state machines.
+ * Handler methods provide the ability to change the behavior for user
+ * requests or transitions depending on the state the machine is in.
+ *
+ *
+ */
+struct sci_base_remote_device_state_handler {
+ /**
+ * The start_handler specifies the method invoked when a user attempts to
+ * start a remote device.
+ */
+ SCI_BASE_REMOTE_DEVICE_HANDLER_T start_handler;
+
+ /**
+ * The stop_handler specifies the method invoked when a user attempts to
+ * stop a remote device.
+ */
+ SCI_BASE_REMOTE_DEVICE_HANDLER_T stop_handler;
+
+ /**
+ * The fail_handler specifies the method invoked when a remote device
+ * failure has occurred. A failure may be due to an inability to
+ * initialize/configure the device.
+ */
+ SCI_BASE_REMOTE_DEVICE_HANDLER_T fail_handler;
+
+ /**
+ * The destruct_handler specifies the method invoked when attempting to
+ * destruct a remote device.
+ */
+ SCI_BASE_REMOTE_DEVICE_HANDLER_T destruct_handler;
+
+ /**
+ * The reset handler specifies the method invloked when requesting to reset a
+ * remote device.
+ */
+ SCI_BASE_REMOTE_DEVICE_HANDLER_T reset_handler;
+
+ /**
+ * The reset complete handler specifies the method invloked when reporting
+ * that a reset has completed to the remote device.
+ */
+ SCI_BASE_REMOTE_DEVICE_HANDLER_T reset_complete_handler;
+
+ /**
+ * The start_io_handler specifies the method invoked when a user
+ * attempts to start an IO request for a remote device.
+ */
+ SCI_BASE_REMOTE_DEVICE_REQUEST_HANDLER_T start_io_handler;
+
+ /**
+ * The complete_io_handler specifies the method invoked when a user
+ * attempts to complete an IO request for a remote device.
+ */
+ SCI_BASE_REMOTE_DEVICE_REQUEST_HANDLER_T complete_io_handler;
+
+ /**
+ * The continue_io_handler specifies the method invoked when a user
+ * attempts to continue an IO request for a remote device.
+ */
+ SCI_BASE_REMOTE_DEVICE_REQUEST_HANDLER_T continue_io_handler;
+
+ /**
+ * The start_task_handler specifies the method invoked when a user
+ * attempts to start a task management request for a remote device.
+ */
+ SCI_BASE_REMOTE_DEVICE_REQUEST_HANDLER_T start_task_handler;
+
+ /**
+ * The complete_task_handler specifies the method invoked when a user
+ * attempts to complete a task management request for a remote device.
+ */
+ SCI_BASE_REMOTE_DEVICE_REQUEST_HANDLER_T complete_task_handler;
+
+};
+
+/**
+ * sci_base_remote_device_construct() - Construct the base remote device
+ * @this_remote_device: This parameter specifies the base remote device to be
+ * constructed.
+ * @state_table: This parameter specifies the table of state definitions to be
+ * utilized for the remote device state machine.
+ *
+ */
+static inline void sci_base_remote_device_construct(
+ struct sci_base_remote_device *base_dev,
+ const struct sci_base_state *state_table)
+{
+ base_dev->parent.private = NULL;
+ sci_base_state_machine_construct(
+ &base_dev->state_machine,
+ &base_dev->parent,
+ state_table,
+ SCI_BASE_REMOTE_DEVICE_STATE_INITIAL
+ );
+
+ sci_base_state_machine_start(
+ &base_dev->state_machine
+ );
+}
+#endif /* _SCI_BASE_REMOTE_DEVICE_H_ */
diff --git a/drivers/scsi/isci/core/sci_base_request.h b/drivers/scsi/isci/core/sci_base_request.h
new file mode 100644
index 000000000000..d1b2195b228a
--- /dev/null
+++ b/drivers/scsi/isci/core/sci_base_request.h
@@ -0,0 +1,195 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCI_BASE_REQUST_H_
+#define _SCI_BASE_REQUST_H_
+
+/**
+ * This file contains all of the constants, types, and method declarations for
+ * the SCI base IO and task request objects.
+ *
+ *
+ */
+
+#include "sci_base_state_machine.h"
+
+/**
+ * enum sci_base_request_states - This enumeration depicts all the states for
+ * the common request state machine.
+ *
+ *
+ */
+enum sci_base_request_states {
+ /**
+ * Simply the initial state for the base request state machine.
+ */
+ SCI_BASE_REQUEST_STATE_INITIAL,
+
+ /**
+ * This state indicates that the request has been constructed. This state
+ * is entered from the INITIAL state.
+ */
+ SCI_BASE_REQUEST_STATE_CONSTRUCTED,
+
+ /**
+ * This state indicates that the request has been started. This state is
+ * entered from the CONSTRUCTED state.
+ */
+ SCI_BASE_REQUEST_STATE_STARTED,
+
+ /**
+ * This state indicates that the request has completed.
+ * This state is entered from the STARTED state. This state is entered from
+ * the ABORTING state.
+ */
+ SCI_BASE_REQUEST_STATE_COMPLETED,
+
+ /**
+ * This state indicates that the request is in the process of being
+ * terminated/aborted.
+ * This state is entered from the CONSTRUCTED state.
+ * This state is entered from the STARTED state.
+ */
+ SCI_BASE_REQUEST_STATE_ABORTING,
+
+ /**
+ * Simply the final state for the base request state machine.
+ */
+ SCI_BASE_REQUEST_STATE_FINAL,
+};
+
+/**
+ * struct sci_base_request - The base request object abstracts the fields
+ * common to all SCI IO and task request objects.
+ *
+ *
+ */
+struct sci_base_request {
+ /**
+ * The field specifies that the parent object for the base request is the
+ * base object itself.
+ */
+ struct sci_base_object parent;
+
+ /**
+ * This field contains the information for the base request state machine.
+ */
+ struct sci_base_state_machine state_machine;
+};
+
+typedef enum sci_status (*SCI_BASE_REQUEST_HANDLER_T)(
+ struct sci_base_request *this_request
+ );
+
+/**
+ * struct sci_base_request_state_handler - This structure contains all of the
+ * state handler methods common to base IO and task request state machines.
+ * Handler methods provide the ability to change the behavior for user
+ * requests or transitions depending on the state the machine is in.
+ *
+ *
+ */
+struct sci_base_request_state_handler {
+ /**
+ * The start_handler specifies the method invoked when a user attempts to
+ * start a request.
+ */
+ SCI_BASE_REQUEST_HANDLER_T start_handler;
+
+ /**
+ * The abort_handler specifies the method invoked when a user attempts to
+ * abort a request.
+ */
+ SCI_BASE_REQUEST_HANDLER_T abort_handler;
+
+ /**
+ * The complete_handler specifies the method invoked when a user attempts to
+ * complete a request.
+ */
+ SCI_BASE_REQUEST_HANDLER_T complete_handler;
+
+ /**
+ * The destruct_handler specifies the method invoked when a user attempts to
+ * destruct a request.
+ */
+ SCI_BASE_REQUEST_HANDLER_T destruct_handler;
+
+};
+
+/**
+ * sci_base_request_construct() - Construct the base request.
+ * @this_request: This parameter specifies the base request to be constructed.
+ * @state_table: This parameter specifies the table of state definitions to be
+ * utilized for the request state machine.
+ *
+ */
+static inline void sci_base_request_construct(
+ struct sci_base_request *base_req,
+ const struct sci_base_state *my_state_table)
+{
+ base_req->parent.private = NULL;
+ sci_base_state_machine_construct(
+ &base_req->state_machine,
+ &base_req->parent,
+ my_state_table,
+ SCI_BASE_REQUEST_STATE_INITIAL
+ );
+
+ sci_base_state_machine_start(
+ &base_req->state_machine
+ );
+}
+
+#endif /* _SCI_BASE_REQUST_H_ */
diff --git a/drivers/scsi/isci/core/sci_base_state.h b/drivers/scsi/isci/core/sci_base_state.h
new file mode 100644
index 000000000000..d6b9c1a951b1
--- /dev/null
+++ b/drivers/scsi/isci/core/sci_base_state.h
@@ -0,0 +1,90 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCI_BASE_STATE_H_
+#define _SCI_BASE_STATE_H_
+
+#include "sci_object.h"
+
+typedef void (*SCI_BASE_STATE_HANDLER_T)(
+ void
+ );
+
+typedef void (*SCI_STATE_TRANSITION_T)(
+ struct sci_base_object *base_object
+ );
+
+/**
+ * struct sci_base_state - The base state object abstracts the fields common to
+ * all state objects defined in SCI.
+ *
+ *
+ */
+struct sci_base_state {
+ /**
+ * This field is a function pointer that defines the method to be
+ * invoked when the state is entered.
+ */
+ SCI_STATE_TRANSITION_T enter_state;
+
+ /**
+ * This field is a function pointer that defines the method to be
+ * invoked when the state is exited.
+ */
+ SCI_STATE_TRANSITION_T exit_state;
+
+};
+
+#endif /* _SCI_BASE_STATE_H_ */
diff --git a/drivers/scsi/isci/core/sci_base_state_machine.c b/drivers/scsi/isci/core/sci_base_state_machine.c
new file mode 100644
index 000000000000..5b1e8da55fe6
--- /dev/null
+++ b/drivers/scsi/isci/core/sci_base_state_machine.c
@@ -0,0 +1,182 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * This file contains all of the functionality common to all state machine
+ * object implementations.
+ *
+ *
+ */
+
+#include "sci_base_state_machine.h"
+
+static void sci_state_machine_exit_state(struct sci_base_state_machine *sm)
+{
+ u32 state = sm->current_state_id;
+ SCI_STATE_TRANSITION_T exit = sm->state_table[state].exit_state;
+
+ if (exit)
+ exit(sm->state_machine_owner);
+}
+
+static void sci_state_machine_enter_state(struct sci_base_state_machine *sm)
+{
+ u32 state = sm->current_state_id;
+ SCI_STATE_TRANSITION_T enter = sm->state_table[state].enter_state;
+
+ if (enter)
+ enter(sm->state_machine_owner);
+}
+
+/*
+ * ******************************************************************************
+ * * P R O T E C T E D M E T H O D S
+ * ****************************************************************************** */
+
+/**
+ * This method will set the initial state and state table for the state
+ * machine. The caller should follow this request with the initialize
+ * request to cause the state machine to start.
+ * @sm: This parameter provides the state machine object to be
+ * constructed.
+ * @state_machine_owner: This parameter indicates the object that is owns the
+ * state machine being constructed.
+ * @state_table: This parameter specifies the table of state objects that is
+ * managed by this state machine.
+ * @initial_state: This parameter specifies the value of the initial state for
+ * this state machine.
+ *
+ */
+void sci_base_state_machine_construct(struct sci_base_state_machine *sm,
+ struct sci_base_object *owner,
+ const struct sci_base_state *state_table,
+ u32 initial_state)
+{
+ sm->state_machine_owner = owner;
+ sm->initial_state_id = initial_state;
+ sm->previous_state_id = initial_state;
+ sm->current_state_id = initial_state;
+ sm->state_table = state_table;
+}
+
+/**
+ * This method will cause the state machine to enter the initial state.
+ * @sm: This parameter specifies the state machine that is to
+ * be started.
+ *
+ * sci_base_state_machine_construct() for how to set the initial state none
+ */
+void sci_base_state_machine_start(struct sci_base_state_machine *sm)
+{
+ sm->current_state_id = sm->initial_state_id;
+#if defined(SCI_BASE_ENABLE_SUBJECT_NOTIFICATION)
+ sci_base_subject_notify(&sm->parent);
+#endif
+ sci_state_machine_enter_state(sm);
+}
+
+/**
+ * This method will cause the state machine to exit it's current state only.
+ * @sm: This parameter specifies the state machine that is to
+ * be stopped.
+ *
+ */
+void sci_base_state_machine_stop(
+ struct sci_base_state_machine *sm)
+{
+ sci_state_machine_exit_state(sm);
+#if defined(SCI_BASE_ENABLE_SUBJECT_NOTIFICATION)
+ sci_base_subject_notify(&sm->parent);
+#endif
+}
+
+/**
+ * This method performs an update to the current state of the state machine.
+ * @sm: This parameter specifies the state machine for which
+ * the caller wishes to perform a state change.
+ * @next_state: This parameter specifies the new state for the state machine.
+ *
+ */
+void sci_base_state_machine_change_state(
+ struct sci_base_state_machine *sm,
+ u32 next_state)
+{
+ sci_state_machine_exit_state(sm);
+
+ sm->previous_state_id = sm->current_state_id;
+ sm->current_state_id = next_state;
+
+#if defined(SCI_BASE_ENABLE_SUBJECT_NOTIFICATION)
+ /* Notify of the state change prior to entering the state. */
+ sci_base_subject_notify(&sm->parent);
+#endif
+
+ sci_state_machine_enter_state(sm);
+}
+
+/**
+ * This method simply returns the current state of the state machine to the
+ * caller.
+ * @sm: This parameter specifies the state machine for which to
+ * retrieve the current state.
+ *
+ * This method returns a u32 value indicating the current state for the
+ * supplied state machine.
+ */
+u32 sci_base_state_machine_get_state(struct sci_base_state_machine *sm)
+{
+ return sm->current_state_id;
+}
+
diff --git a/drivers/scsi/isci/core/sci_base_state_machine.h b/drivers/scsi/isci/core/sci_base_state_machine.h
new file mode 100644
index 000000000000..cee38bd3d127
--- /dev/null
+++ b/drivers/scsi/isci/core/sci_base_state_machine.h
@@ -0,0 +1,139 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCI_BASE_STATE_MACHINE_H_
+#define _SCI_BASE_STATE_MACHINE_H_
+
+/**
+ * This file contains all structures, constants, or method declarations common
+ * to all state machines defined in SCI.
+ *
+ *
+ */
+
+
+#include "sci_base_state.h"
+
+
+/**
+ * SET_STATE_HANDLER() -
+ *
+ * This macro simply provides simplified retrieval of an objects state handler.
+ */
+#define SET_STATE_HANDLER(object, table, state) \
+ (object)->state_handlers = &(table)[(state)]
+
+/**
+ * struct sci_base_state_machine - This structure defines the fields common to
+ * all state machines.
+ *
+ *
+ */
+struct sci_base_state_machine {
+ /**
+ * This field points to the start of the state machine's state table.
+ */
+ const struct sci_base_state *state_table;
+
+ /**
+ * This field points to the object to which this state machine is
+ * associated. It serves as a cookie to be provided to the state
+ * enter/exit methods.
+ */
+ struct sci_base_object *state_machine_owner;
+
+ /**
+ * This field simply indicates the state value for the state machine's
+ * initial state.
+ */
+ u32 initial_state_id;
+
+ /**
+ * This field indicates the current state of the state machine.
+ */
+ u32 current_state_id;
+
+ /**
+ * This field indicates the previous state of the state machine.
+ */
+ u32 previous_state_id;
+
+};
+
+/*
+ * ******************************************************************************
+ * * P R O T E C T E D M E T H O D S
+ * ****************************************************************************** */
+
+void sci_base_state_machine_construct(
+ struct sci_base_state_machine *this_state_machine,
+ struct sci_base_object *state_machine_owner,
+ const struct sci_base_state *state_table,
+ u32 initial_state);
+
+void sci_base_state_machine_start(
+ struct sci_base_state_machine *this_state_machine);
+
+void sci_base_state_machine_stop(
+ struct sci_base_state_machine *this_state_machine);
+
+void sci_base_state_machine_change_state(
+ struct sci_base_state_machine *this_state_machine,
+ u32 next_state);
+
+u32 sci_base_state_machine_get_state(
+ struct sci_base_state_machine *this_state_machine);
+
+#endif /* _SCI_BASE_STATE_MACHINE_H_ */
diff --git a/drivers/scsi/isci/core/sci_controller.h b/drivers/scsi/isci/core/sci_controller.h
new file mode 100644
index 000000000000..26c3548cbf7a
--- /dev/null
+++ b/drivers/scsi/isci/core/sci_controller.h
@@ -0,0 +1,100 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCI_CONTROLLER_H_
+#define _SCI_CONTROLLER_H_
+
+/**
+ * This file contains all of the interface methods that can be called by an SCI
+ * user on all SCI controller objects.
+ *
+ *
+ */
+
+
+#include "sci_types.h"
+
+struct sci_base_memory_descriptor_list;
+struct scic_sds_controller;
+
+#define SCI_CONTROLLER_INVALID_IO_TAG 0xFFFF
+
+/**
+ * sci_controller_get_memory_descriptor_list_handle() - This method simply
+ * returns a handle for the memory descriptor list associated with the
+ * supplied controller. The descriptor list provides DMA safe/capable
+ * memory requirements for this controller.
+ * @controller: This parameter specifies the controller for which to retrieve
+ * the DMA safe memory descriptor list.
+ *
+ * The user must adhere to the alignment requirements specified in memory
+ * descriptor. In situations where the operating environment does not offer
+ * memory allocation utilities supporting alignment, then it is the
+ * responsibility of the user to manually align the memory buffer for SCI.
+ * Thus, the user may have to allocate a larger buffer to meet the alignment.
+ * Additionally, the user will need to remember the actual memory allocation
+ * addresses in order to ensure the memory can be properly freed when necessary
+ * to do so. This method will return a valid handle, but the MDL may not be
+ * accurate until after the user has invoked the associated
+ * sci_controller_initialize() routine. A pointer to a physical memory
+ * descriptor array.
+ */
+struct sci_base_memory_descriptor_list *
+ sci_controller_get_memory_descriptor_list_handle(
+ struct scic_sds_controller *controller);
+
+
+#endif /* _SCI_CONTROLLER_H_ */
+
diff --git a/drivers/scsi/isci/core/sci_controller_constants.h b/drivers/scsi/isci/core/sci_controller_constants.h
new file mode 100644
index 000000000000..06c34c7bdd5f
--- /dev/null
+++ b/drivers/scsi/isci/core/sci_controller_constants.h
@@ -0,0 +1,215 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCI_CONTROLLER_CONSTANTS_H_
+#define _SCI_CONTROLLER_CONSTANTS_H_
+
+/**
+ * This file contains constant values that change based on the type of core or
+ * framework being managed. These constants are exported in order to
+ * provide the user with information as to the bounds (i.e. how many) of
+ * specific objects.
+ *
+ *
+ */
+
+
+#ifdef SCIC_SDS_4_ENABLED
+
+#ifndef SCI_MAX_PHYS
+/**
+ *
+ *
+ * This constant defines the maximum number of phy objects that can be
+ * supported for the SCU Driver Standard (SDS) library. This is tied directly
+ * to silicon capabilities.
+ */
+#define SCI_MAX_PHYS (4)
+#endif
+
+#ifndef SCI_MAX_PORTS
+/**
+ *
+ *
+ * This constant defines the maximum number of port objects that can be
+ * supported for the SCU Driver Standard (SDS) library. This is tied directly
+ * to silicon capabilities.
+ */
+#define SCI_MAX_PORTS SCI_MAX_PHYS
+#endif
+
+#ifndef SCI_MIN_SMP_PHYS
+/**
+ *
+ *
+ * This constant defines the minimum number of SMP phy objects that can be
+ * supported for a single expander level. This was determined by using 36
+ * physical phys and room for 2 virtual phys.
+ */
+#define SCI_MIN_SMP_PHYS (38)
+#endif
+
+#ifndef SCI_MAX_SMP_PHYS
+/**
+ *
+ *
+ * This constant defines the maximum number of SMP phy objects that can be
+ * supported for the SCU Driver Standard (SDS) library. This number can be
+ * increased if required.
+ */
+#define SCI_MAX_SMP_PHYS (384)
+#endif
+
+#ifndef SCI_MAX_REMOTE_DEVICES
+/**
+ *
+ *
+ * This constant defines the maximum number of remote device objects that can
+ * be supported for the SCU Driver Standard (SDS) library. This is tied
+ * directly to silicon capabilities.
+ */
+#define SCI_MAX_REMOTE_DEVICES (256)
+#endif
+
+#ifndef SCI_MIN_REMOTE_DEVICES
+/**
+ *
+ *
+ * This constant defines the minimum number of remote device objects that can
+ * be supported for the SCU Driver Standard (SDS) library. This # can be
+ * configured for minimum memory environments to any value less than
+ * SCI_MAX_REMOTE_DEVICES
+ */
+#define SCI_MIN_REMOTE_DEVICES (16)
+#endif
+
+#ifndef SCI_MAX_IO_REQUESTS
+/**
+ *
+ *
+ * This constant defines the maximum number of IO request objects that can be
+ * supported for the SCU Driver Standard (SDS) library. This is tied directly
+ * to silicon capabilities.
+ */
+#define SCI_MAX_IO_REQUESTS (256)
+#endif
+
+#ifndef SCI_MIN_IO_REQUESTS
+/**
+ *
+ *
+ * This constant defines the minimum number of IO request objects that can be
+ * supported for the SCU Driver Standard (SDS) library. This # can be
+ * configured for minimum memory environments to any value less than
+ * SCI_MAX_IO_REQUESTS.
+ */
+#define SCI_MIN_IO_REQUESTS (1)
+#endif
+
+#ifndef SCI_MAX_MSIX_MESSAGES
+/**
+ *
+ *
+ * This constant defines the maximum number of MSI-X interrupt vectors/messages
+ * supported for an SCU hardware controller instance.
+ */
+#define SCI_MAX_MSIX_MESSAGES (2)
+#endif
+
+#ifndef SCI_MAX_SCATTER_GATHER_ELEMENTS
+/**
+ *
+ *
+ * This constant defines the maximum number of Scatter-Gather Elements to be
+ * used by any SCI component.
+ */
+#define SCI_MAX_SCATTER_GATHER_ELEMENTS 130
+#endif
+
+#ifndef SCI_MIN_SCATTER_GATHER_ELEMENTS
+/**
+ *
+ *
+ * This constant defines the minimum number of Scatter-Gather Elements to be
+ * used by any SCI component.
+ */
+#define SCI_MIN_SCATTER_GATHER_ELEMENTS 1
+#endif
+
+#else /* SCIC_SDS_4_ENABLED */
+
+#error "SCI Core configuration left unspecified (e.g. SCIC_SDS_4_ENABLED)"
+
+#endif /* SCIC_SDS_4_ENABLED */
+
+/**
+ *
+ *
+ * This constant defines the maximum number of controllers that can occur in a
+ * single silicon package.
+ */
+#define SCI_MAX_CONTROLLERS 2
+
+/**
+ *
+ *
+ * The maximum number of supported domain objects is currently tied to the
+ * maximum number of support port objects.
+ */
+#define SCI_MAX_DOMAINS SCI_MAX_PORTS
+
+
+#endif /* _SCI_CONTROLLER_CONSTANTS_H_ */
+
diff --git a/drivers/scsi/isci/core/sci_memory_descriptor_list.h b/drivers/scsi/isci/core/sci_memory_descriptor_list.h
new file mode 100644
index 000000000000..44de1c18d2c8
--- /dev/null
+++ b/drivers/scsi/isci/core/sci_memory_descriptor_list.h
@@ -0,0 +1,169 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCI_MEMORY_DESCRIPTOR_LIST_H_
+#define _SCI_MEMORY_DESCRIPTOR_LIST_H_
+
+/**
+ * This file contains all of the basic data types utilized by an SCI user or
+ * implementor.
+ *
+ *
+ */
+
+
+#include "sci_types.h"
+
+struct sci_base_memory_descriptor_list;
+
+/**
+ *
+ *
+ * SCI_MDE_ATTRIBUTES These constants depict memory attributes for the Memory
+ * Descriptor Entries (MDEs) contained in the MDL.
+ */
+#define SCI_MDE_ATTRIBUTE_CACHEABLE 0x0001
+#define SCI_MDE_ATTRIBUTE_PHYSICALLY_CONTIGUOUS 0x0002
+
+/**
+ * struct sci_physical_memory_descriptor - This structure defines a description
+ * of a memory location for the SCI implementation.
+ *
+ *
+ */
+struct sci_physical_memory_descriptor {
+ /**
+ * This field contains the virtual address associated with this descriptor
+ * element. This field shall be zero when the descriptor is retrieved from
+ * the SCI implementation. The user shall set this field prior
+ * sci_controller_start()
+ */
+ void *virtual_address;
+
+ /**
+ * This field contains the physical address associated with this desciptor
+ * element. This field shall be zero when the descriptor is retrieved from
+ * the SCI implementation. The user shall set this field prior
+ * sci_controller_start()
+ */
+ dma_addr_t physical_address;
+
+ /**
+ * This field contains the size requirement for this memory descriptor.
+ * A value of zero for this field indicates the end of the descriptor
+ * list. The value should be treated as read only for an SCI user.
+ */
+ u32 constant_memory_size;
+
+ /**
+ * This field contains the alignment requirement for this memory
+ * descriptor. A value of zero for this field indicates the end of the
+ * descriptor list. All other values indicate the number of bytes to
+ * achieve the necessary alignment. The value should be treated as
+ * read only for an SCI user.
+ */
+ u32 constant_memory_alignment;
+
+ /**
+ * This field contains an indication regarding the desired memory
+ * attributes for this memory descriptor entry.
+ * Notes:
+ * - If the cacheable attribute is set, the user can allocate
+ * memory that is backed by cache for better performance. It
+ * is not required that the memory be backed by cache.
+ * - If the physically contiguous attribute is set, then the
+ * entire memory must be physically contiguous across all
+ * page boundaries.
+ */
+ u16 constant_memory_attributes;
+
+};
+
+/**
+ * sci_mdl_first_entry() - This method simply rewinds the MDL iterator back to
+ * the first memory descriptor entry in the list.
+ * @mdl: This parameter specifies the memory descriptor list that is to be
+ * rewound.
+ *
+ */
+void sci_mdl_first_entry(
+ struct sci_base_memory_descriptor_list *mdl);
+
+/**
+ * sci_mdl_next_entry() - This method simply updates the "current" pointer to
+ * the next sequential memory descriptor.
+ * @mdl: This parameter specifies the memory descriptor list for which to
+ * return the next memory descriptor entry in the list.
+ *
+ * none.
+ */
+void sci_mdl_next_entry(
+ struct sci_base_memory_descriptor_list *mdl);
+
+/**
+ * sci_mdl_get_current_entry() - This method simply returns the current memory
+ * descriptor entry.
+ * @mdl: This parameter specifies the memory descriptor list for which to
+ * return the current memory descriptor entry.
+ *
+ * This method returns a pointer to the current physical memory descriptor in
+ * the MDL. NULL This value is returned if there are no descriptors in the list.
+ */
+struct sci_physical_memory_descriptor *sci_mdl_get_current_entry(
+ struct sci_base_memory_descriptor_list *mdl);
+
+
+#endif /* _SCI_MEMORY_DESCRIPTOR_LIST_H_ */
+
diff --git a/drivers/scsi/isci/core/sci_object.h b/drivers/scsi/isci/core/sci_object.h
new file mode 100644
index 000000000000..930694264f1a
--- /dev/null
+++ b/drivers/scsi/isci/core/sci_object.h
@@ -0,0 +1,99 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCI_OBJECT_H_
+#define _SCI_OBJECT_H_
+
+/**
+ * This file contains all of the method and constants associated with the SCI
+ * base object. The SCI base object is the class from which all other
+ * objects derive in the Storage Controller Interface.
+ *
+ *
+ */
+
+
+#include "sci_types.h"
+#include "sci_status.h"
+
+/**
+ * struct sci_base_object - all core objects must include this as their
+ * first member to permit the casting below
+ *
+ * TODO: unwind this assumption, convert these routines and callers to pass a struct
+ * sci_base_object pointer without casting, or convert 'private' to the
+ * expected type per-object
+ *
+ */
+struct sci_base_object {
+ void *private;
+};
+
+static inline void *sci_object_get_association(void *obj)
+{
+ struct sci_base_object *base = obj;
+
+ return base->private;
+}
+
+static inline void sci_object_set_association(void *obj, void *private)
+{
+ struct sci_base_object *base = obj;
+
+ base->private = private;
+}
+
+#endif /* _SCI_OBJECT_H_ */
+
diff --git a/drivers/scsi/isci/core/sci_pool.h b/drivers/scsi/isci/core/sci_pool.h
new file mode 100644
index 000000000000..c0d2ea32529b
--- /dev/null
+++ b/drivers/scsi/isci/core/sci_pool.h
@@ -0,0 +1,199 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * This file contains the interface to the pool class. This class allows two
+ * different two different priority tasks to insert and remove items from
+ * the free pool. The user of the pool is expected to evaluate the pool
+ * condition empty before a get operation and pool condition full before a
+ * put operation. Methods Provided: - sci_pool_create() -
+ * sci_pool_initialize() - sci_pool_empty() - sci_pool_full() -
+ * sci_pool_get() - sci_pool_put()
+ *
+ *
+ */
+
+#ifndef _SCI_POOL_H_
+#define _SCI_POOL_H_
+
+/**
+ * SCI_POOL_INCREMENT() -
+ *
+ * Private operation for the pool
+ */
+#define SCI_POOL_INCREMENT(this_pool, index) \
+ (((index) + 1) == (this_pool).size ? 0 : (index) + 1)
+
+/**
+ * SCI_POOL_CREATE() -
+ *
+ * This creates a pool structure of pool_name. The members in the pool are of
+ * type with number of elements equal to size.
+ */
+#define SCI_POOL_CREATE(pool_name, type, pool_size) \
+ struct \
+ { \
+ u32 size; \
+ u32 get; \
+ u32 put; \
+ type array[(pool_size) + 1]; \
+ } pool_name
+
+
+/**
+ * sci_pool_empty() -
+ *
+ * This macro evaluates the pool and returns true if the pool is empty. If the
+ * pool is empty the user should not perform any get operation on the pool.
+ */
+#define sci_pool_empty(this_pool) \
+ ((this_pool).get == (this_pool).put)
+
+/**
+ * sci_pool_full() -
+ *
+ * This macro evaluates the pool and returns true if the pool is full. If the
+ * pool is full the user should not perform any put operation.
+ */
+#define sci_pool_full(this_pool) \
+ (SCI_POOL_INCREMENT(this_pool, (this_pool).put) == (this_pool).get)
+
+/**
+ * sci_pool_size() -
+ *
+ * This macro returns the size of the pool created. The internal size of the
+ * pool is actually 1 larger then necessary in order to ensure get and put
+ * pointers can be written simultaneously by different users. As a result,
+ * this macro subtracts 1 from the internal size
+ */
+#define sci_pool_size(this_pool) \
+ ((this_pool).size - 1)
+
+/**
+ * sci_pool_count() -
+ *
+ * This macro indicates the number of elements currently contained in the pool.
+ */
+#define sci_pool_count(this_pool) \
+ (\
+ sci_pool_empty((this_pool)) \
+ ? 0 \
+ : (\
+ sci_pool_full((this_pool)) \
+ ? sci_pool_size((this_pool)) \
+ : (\
+ (this_pool).get > (this_pool).put \
+ ? ((this_pool).size - (this_pool).get + (this_pool).put) \
+ : ((this_pool).put - (this_pool).get) \
+ ) \
+ ) \
+ )
+
+/**
+ * sci_pool_initialize() -
+ *
+ * This macro initializes the pool to an empty condition.
+ */
+#define sci_pool_initialize(this_pool) \
+ { \
+ (this_pool).size = (sizeof((this_pool).array) / sizeof((this_pool).array[0])); \
+ (this_pool).get = 0; \
+ (this_pool).put = 0; \
+ }
+
+/**
+ * sci_pool_get() -
+ *
+ * This macro will get the next free element from the pool. This should only be
+ * called if the pool is not empty.
+ */
+#define sci_pool_get(this_pool, my_value) \
+ { \
+ (my_value) = (this_pool).array[(this_pool).get]; \
+ (this_pool).get = SCI_POOL_INCREMENT((this_pool), (this_pool).get); \
+ }
+
+/**
+ * sci_pool_put() -
+ *
+ * This macro will put the value into the pool. This should only be called if
+ * the pool is not full.
+ */
+#define sci_pool_put(this_pool, the_value) \
+ { \
+ (this_pool).array[(this_pool).put] = (the_value); \
+ (this_pool).put = SCI_POOL_INCREMENT((this_pool), (this_pool).put); \
+ }
+
+/**
+ * sci_pool_erase() -
+ *
+ * This macro will search the pool and remove any elements in the pool matching
+ * the supplied value. This method can only be utilized on pools
+ */
+#define sci_pool_erase(this_pool, type, the_value) \
+ { \
+ type tmp_value; \
+ u32 index; \
+ u32 element_count = sci_pool_count((this_pool)); \
+ \
+ for (index = 0; index < element_count; index++) { \
+ sci_pool_get((this_pool), tmp_value); \
+ if (tmp_value != (the_value)) \
+ sci_pool_put((this_pool), tmp_value); \
+ } \
+ }
+
+#endif /* _SCI_POOL_H_ */
diff --git a/drivers/scsi/isci/core/sci_status.h b/drivers/scsi/isci/core/sci_status.h
new file mode 100644
index 000000000000..72b61081c28d
--- /dev/null
+++ b/drivers/scsi/isci/core/sci_status.h
@@ -0,0 +1,409 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCI_STATUS_H_
+#define _SCI_STATUS_H_
+
+/**
+ * This file contains all of the return status codes utilized across the
+ * various sub-components in SCI.
+ *
+ *
+ */
+
+
+/**
+ * enum _SCI_STATUS - This is the general return status enumeration for non-IO,
+ * non-task management related SCI interface methods.
+ *
+ *
+ */
+enum sci_status {
+ /**
+ * This member indicates successful completion.
+ */
+ SCI_SUCCESS = 0,
+
+ /**
+ * This value indicates that the calling method completed successfully,
+ * but that the IO may have completed before having it's start method
+ * invoked. This occurs during SAT translation for requests that do
+ * not require an IO to the target or for any other requests that may
+ * be completed without having to submit IO.
+ */
+ SCI_SUCCESS_IO_COMPLETE_BEFORE_START,
+
+ /**
+ * This Value indicates that the SCU hardware returned an early response
+ * because the io request specified more data than is returned by the
+ * target device (mode pages, inquiry data, etc.). The completion routine
+ * will handle this case to get the actual number of bytes transferred.
+ */
+ SCI_SUCCESS_IO_DONE_EARLY,
+
+ /**
+ * This member indicates that the object for which a state change is
+ * being requested is already in said state.
+ */
+ SCI_WARNING_ALREADY_IN_STATE,
+
+ /**
+ * This member indicates interrupt coalescence timer may cause SAS
+ * specification compliance issues (i.e. SMP target mode response
+ * frames must be returned within 1.9 milliseconds).
+ */
+ SCI_WARNING_TIMER_CONFLICT,
+
+ /**
+ * This field indicates a sequence of action is not completed yet. Mostly,
+ * this status is used when multiple ATA commands are needed in a SATI translation.
+ */
+ SCI_WARNING_SEQUENCE_INCOMPLETE,
+
+ /**
+ * This member indicates that there was a general failure.
+ */
+ SCI_FAILURE,
+
+ /**
+ * This member indicates that the SCI implementation is unable to complete
+ * an operation due to a critical flaw the prevents any further operation
+ * (i.e. an invalid pointer).
+ */
+ SCI_FATAL_ERROR,
+
+ /**
+ * This member indicates the calling function failed, because the state
+ * of the controller is in a state that prevents successful completion.
+ */
+ SCI_FAILURE_INVALID_STATE,
+
+ /**
+ * This member indicates the calling function failed, because there is
+ * insufficient resources/memory to complete the request.
+ */
+ SCI_FAILURE_INSUFFICIENT_RESOURCES,
+
+ /**
+ * This member indicates the calling function failed, because the
+ * controller object required for the operation can't be located.
+ */
+ SCI_FAILURE_CONTROLLER_NOT_FOUND,
+
+ /**
+ * This member indicates the calling function failed, because the
+ * discovered controller type is not supported by the library.
+ */
+ SCI_FAILURE_UNSUPPORTED_CONTROLLER_TYPE,
+
+ /**
+ * This member indicates the calling function failed, because the
+ * requested initialization data version isn't supported.
+ */
+ SCI_FAILURE_UNSUPPORTED_INIT_DATA_VERSION,
+
+ /**
+ * This member indicates the calling function failed, because the
+ * requested configuration of SAS Phys into SAS Ports is not supported.
+ */
+ SCI_FAILURE_UNSUPPORTED_PORT_CONFIGURATION,
+
+ /**
+ * This member indicates the calling function failed, because the
+ * requested protocol is not supported by the remote device, port,
+ * or controller.
+ */
+ SCI_FAILURE_UNSUPPORTED_PROTOCOL,
+
+ /**
+ * This member indicates the calling function failed, because the
+ * requested information type is not supported by the SCI implementation.
+ */
+ SCI_FAILURE_UNSUPPORTED_INFORMATION_TYPE,
+
+ /**
+ * This member indicates the calling function failed, because the
+ * device already exists.
+ */
+ SCI_FAILURE_DEVICE_EXISTS,
+
+ /**
+ * This member indicates the calling function failed, because adding
+ * a phy to the object is not possible.
+ */
+ SCI_FAILURE_ADDING_PHY_UNSUPPORTED,
+
+ /**
+ * This member indicates the calling function failed, because the
+ * requested information type is not supported by the SCI implementation.
+ */
+ SCI_FAILURE_UNSUPPORTED_INFORMATION_FIELD,
+
+ /**
+ * This member indicates the calling function failed, because the SCI
+ * implementation does not support the supplied time limit.
+ */
+ SCI_FAILURE_UNSUPPORTED_TIME_LIMIT,
+
+ /**
+ * This member indicates the calling method failed, because the SCI
+ * implementation does not contain the specified Phy.
+ */
+ SCI_FAILURE_INVALID_PHY,
+
+ /**
+ * This member indicates the calling method failed, because the SCI
+ * implementation does not contain the specified Port.
+ */
+ SCI_FAILURE_INVALID_PORT,
+
+ /**
+ * This member indicates the calling method was partly successful
+ * The port was reset but not all phys in port are operational
+ */
+ SCI_FAILURE_RESET_PORT_PARTIAL_SUCCESS,
+
+ /**
+ * This member indicates that calling method failed
+ * The port reset did not complete because none of the phys are operational
+ */
+ SCI_FAILURE_RESET_PORT_FAILURE,
+
+ /**
+ * This member indicates the calling method failed, because the SCI
+ * implementation does not contain the specified remote device.
+ */
+ SCI_FAILURE_INVALID_REMOTE_DEVICE,
+
+ /**
+ * This member indicates the calling method failed, because the remote
+ * device is in a bad state and requires a reset.
+ */
+ SCI_FAILURE_REMOTE_DEVICE_RESET_REQUIRED,
+
+ /**
+ * This member indicates the calling method failed, because the SCI
+ * implementation does not contain or support the specified IO tag.
+ */
+ SCI_FAILURE_INVALID_IO_TAG,
+
+ /**
+ * This member indicates that the operation failed and the user should
+ * check the response data associated with the IO.
+ */
+ SCI_FAILURE_IO_RESPONSE_VALID,
+
+ /**
+ * This member indicates that the operation failed, the failure is
+ * controller implementation specific, and the response data associated
+ * with the request is not valid. You can query for the controller
+ * specific error information via scic_controller_get_request_status()
+ */
+ SCI_FAILURE_CONTROLLER_SPECIFIC_IO_ERR,
+
+ /**
+ * This member indicated that the operation failed because the
+ * user requested this IO to be terminated.
+ */
+ SCI_FAILURE_IO_TERMINATED,
+
+ /**
+ * This member indicates that the operation failed and the associated
+ * request requires a SCSI abort task to be sent to the target.
+ */
+ SCI_FAILURE_IO_REQUIRES_SCSI_ABORT,
+
+ /**
+ * This member indicates that the operation failed because the supplied
+ * device could not be located.
+ */
+ SCI_FAILURE_DEVICE_NOT_FOUND,
+
+ /**
+ * This member indicates that the operation failed because the
+ * objects association is required and is not correctly set.
+ */
+ SCI_FAILURE_INVALID_ASSOCIATION,
+
+ /**
+ * This member indicates that the operation failed, because a timeout
+ * occurred.
+ */
+ SCI_FAILURE_TIMEOUT,
+
+ /**
+ * This member indicates that the operation failed, because the user
+ * specified a value that is either invalid or not supported.
+ */
+ SCI_FAILURE_INVALID_PARAMETER_VALUE,
+
+ /**
+ * This value indicates that the operation failed, because the number
+ * of messages (MSI-X) is not supported.
+ */
+ SCI_FAILURE_UNSUPPORTED_MESSAGE_COUNT,
+
+ /**
+ * This value indicates that the method failed due to a lack of
+ * available NCQ tags.
+ */
+ SCI_FAILURE_NO_NCQ_TAG_AVAILABLE,
+
+ /**
+ * This value indicates that a protocol violation has occurred on the
+ * link.
+ */
+ SCI_FAILURE_PROTOCOL_VIOLATION,
+
+ /**
+ * This value indicates a failure condition that retry may help to clear.
+ */
+ SCI_FAILURE_RETRY_REQUIRED,
+
+ /**
+ * This field indicates the retry limit was reached when a retry is attempted
+ */
+ SCI_FAILURE_RETRY_LIMIT_REACHED,
+
+ /**
+ * This member indicates the calling method was partly successful.
+ * Mostly, this status is used when a LUN_RESET issued to an expander attached
+ * STP device in READY NCQ substate needs to have RNC suspended/resumed
+ * before posting TC.
+ */
+ SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS,
+
+ /**
+ * This field indicates an illegal phy connection based on the routing attribute
+ * of both expander phy attached to each other.
+ */
+ SCI_FAILURE_ILLEGAL_ROUTING_ATTRIBUTE_CONFIGURATION,
+
+ /**
+ * This field indicates a CONFIG ROUTE INFO command has a response with function result
+ * INDEX DOES NOT EXIST, usually means exceeding max route index.
+ */
+ SCI_FAILURE_EXCEED_MAX_ROUTE_INDEX,
+
+ /**
+ * This value indicates that an unsupported PCI device ID has been
+ * specified. This indicates that attempts to invoke
+ * scic_library_allocate_controller() will fail.
+ */
+ SCI_FAILURE_UNSUPPORTED_PCI_DEVICE_ID
+
+};
+
+/**
+ * enum _SCI_IO_STATUS - This enumeration depicts all of the possible IO
+ * completion status values. Each value in this enumeration maps directly
+ * to a value in the enum sci_status enumeration. Please refer to that
+ * enumeration for detailed comments concerning what the status represents.
+ *
+ * Add the API to retrieve the SCU status from the core. Check to see that the
+ * following status are properly handled: - SCI_IO_FAILURE_UNSUPPORTED_PROTOCOL
+ * - SCI_IO_FAILURE_INVALID_IO_TAG
+ */
+enum sci_io_status {
+ SCI_IO_SUCCESS = SCI_SUCCESS,
+ SCI_IO_FAILURE = SCI_FAILURE,
+ SCI_IO_SUCCESS_COMPLETE_BEFORE_START = SCI_SUCCESS_IO_COMPLETE_BEFORE_START,
+ SCI_IO_SUCCESS_IO_DONE_EARLY = SCI_SUCCESS_IO_DONE_EARLY,
+ SCI_IO_FAILURE_INVALID_STATE = SCI_FAILURE_INVALID_STATE,
+ SCI_IO_FAILURE_INSUFFICIENT_RESOURCES = SCI_FAILURE_INSUFFICIENT_RESOURCES,
+ SCI_IO_FAILURE_UNSUPPORTED_PROTOCOL = SCI_FAILURE_UNSUPPORTED_PROTOCOL,
+ SCI_IO_FAILURE_RESPONSE_VALID = SCI_FAILURE_IO_RESPONSE_VALID,
+ SCI_IO_FAILURE_CONTROLLER_SPECIFIC_ERR = SCI_FAILURE_CONTROLLER_SPECIFIC_IO_ERR,
+ SCI_IO_FAILURE_TERMINATED = SCI_FAILURE_IO_TERMINATED,
+ SCI_IO_FAILURE_REQUIRES_SCSI_ABORT = SCI_FAILURE_IO_REQUIRES_SCSI_ABORT,
+ SCI_IO_FAILURE_INVALID_PARAMETER_VALUE = SCI_FAILURE_INVALID_PARAMETER_VALUE,
+ SCI_IO_FAILURE_NO_NCQ_TAG_AVAILABLE = SCI_FAILURE_NO_NCQ_TAG_AVAILABLE,
+ SCI_IO_FAILURE_PROTOCOL_VIOLATION = SCI_FAILURE_PROTOCOL_VIOLATION,
+
+ SCI_IO_FAILURE_REMOTE_DEVICE_RESET_REQUIRED = SCI_FAILURE_REMOTE_DEVICE_RESET_REQUIRED,
+
+ SCI_IO_FAILURE_RETRY_REQUIRED = SCI_FAILURE_RETRY_REQUIRED,
+ SCI_IO_FAILURE_RETRY_LIMIT_REACHED = SCI_FAILURE_RETRY_LIMIT_REACHED,
+ SCI_IO_FAILURE_INVALID_REMOTE_DEVICE = SCI_FAILURE_INVALID_REMOTE_DEVICE
+};
+
+/**
+ * enum _SCI_TASK_STATUS - This enumeration depicts all of the possible task
+ * completion status values. Each value in this enumeration maps directly
+ * to a value in the enum sci_status enumeration. Please refer to that
+ * enumeration for detailed comments concerning what the status represents.
+ *
+ * Check to see that the following status are properly handled:
+ */
+enum sci_task_status {
+ SCI_TASK_SUCCESS = SCI_SUCCESS,
+ SCI_TASK_FAILURE = SCI_FAILURE,
+ SCI_TASK_FAILURE_INVALID_STATE = SCI_FAILURE_INVALID_STATE,
+ SCI_TASK_FAILURE_INSUFFICIENT_RESOURCES = SCI_FAILURE_INSUFFICIENT_RESOURCES,
+ SCI_TASK_FAILURE_UNSUPPORTED_PROTOCOL = SCI_FAILURE_UNSUPPORTED_PROTOCOL,
+ SCI_TASK_FAILURE_INVALID_TAG = SCI_FAILURE_INVALID_IO_TAG,
+ SCI_TASK_FAILURE_RESPONSE_VALID = SCI_FAILURE_IO_RESPONSE_VALID,
+ SCI_TASK_FAILURE_CONTROLLER_SPECIFIC_ERR = SCI_FAILURE_CONTROLLER_SPECIFIC_IO_ERR,
+ SCI_TASK_FAILURE_TERMINATED = SCI_FAILURE_IO_TERMINATED,
+ SCI_TASK_FAILURE_INVALID_PARAMETER_VALUE = SCI_FAILURE_INVALID_PARAMETER_VALUE,
+
+ SCI_TASK_FAILURE_REMOTE_DEVICE_RESET_REQUIRED = SCI_FAILURE_REMOTE_DEVICE_RESET_REQUIRED,
+ SCI_TASK_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS = SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS
+
+};
+
+
+#endif /* _SCI_STATUS_H_ */
+
diff --git a/drivers/scsi/isci/core/sci_types.h b/drivers/scsi/isci/core/sci_types.h
new file mode 100644
index 000000000000..431735d1a589
--- /dev/null
+++ b/drivers/scsi/isci/core/sci_types.h
@@ -0,0 +1,88 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCI_TYPES_H_
+#define _SCI_TYPES_H_
+
+#include <linux/string.h>
+
+#define sci_cb_make_physical_address(physical_addr, addr_upper, addr_lower) \
+ ((physical_addr) = (addr_lower) | ((u64)addr_upper) << 32)
+
+#define SCI_INVALID_HANDLE 0x0
+
+/**
+ * The SCI_LIBRARY_HANDLE_T will be utilized by SCI users as an opaque handle
+ * for the SCI Library object.
+ *
+ * SCI_LIBRARY_HANDLE_T
+ */
+typedef void *SCI_LIBRARY_HANDLE_T;
+
+
+typedef enum {
+ SCI_IO_REQUEST_DATA_IN = 0, /* Read operation */
+ SCI_IO_REQUEST_DATA_OUT, /* Write operation */
+ SCI_IO_REQUEST_NO_DATA
+} SCI_IO_REQUEST_DATA_DIRECTION;
+
+
+enum sci_controller_mode {
+ SCI_MODE_SPEED, /* Optimized for performance */
+ SCI_MODE_SIZE /* Optimized for memory use */
+};
+
+#endif /* _SCI_TYPES_H_ */
+
diff --git a/drivers/scsi/isci/core/sci_util.c b/drivers/scsi/isci/core/sci_util.c
new file mode 100644
index 000000000000..5cdd96f29a9e
--- /dev/null
+++ b/drivers/scsi/isci/core/sci_util.c
@@ -0,0 +1,70 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sci_util.h"
+
+void scic_word_copy_with_swap(
+ u32 *destination,
+ u32 *source,
+ u32 word_count)
+{
+ while (word_count--) {
+ *destination = SCIC_SWAP_DWORD(*source);
+
+ source++;
+ destination++;
+ }
+}
+
diff --git a/drivers/scsi/isci/core/sci_util.h b/drivers/scsi/isci/core/sci_util.h
new file mode 100644
index 000000000000..67e2badf8ea8
--- /dev/null
+++ b/drivers/scsi/isci/core/sci_util.h
@@ -0,0 +1,138 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCI_UTIL_H_
+#define _SCI_UTIL_H_
+
+#include "sci_types.h"
+
+/**
+ * SCIC_SWAP_DWORD() -
+ *
+ * Normal byte swap macro
+ */
+#define SCIC_SWAP_DWORD(x) \
+ (\
+ (((x) >> 24) & 0x000000FF) \
+ | (((x) >> 8) & 0x0000FF00) \
+ | (((x) << 8) & 0x00FF0000) \
+ | (((x) << 24) & 0xFF000000) \
+ )
+
+#define SCIC_BUILD_DWORD(char_buffer) \
+ (\
+ ((char_buffer)[0] << 24) \
+ | ((char_buffer)[1] << 16) \
+ | ((char_buffer)[2] << 8) \
+ | ((char_buffer)[3]) \
+ )
+
+#define SCI_FIELD_OFFSET(type, field) ((unsigned long)&(((type *)0)->field))
+
+/**
+ * sci_physical_address_add() -
+ *
+ * This macro simply performs addition on an dma_addr_t type. The
+ * lower u32 value is "clipped" or "wrapped" back through 0. When this occurs
+ * the upper 32-bits are incremented by 1.
+ */
+#define sci_physical_address_add(physical_address, value) \
+ { \
+ u32 lower = lower_32_bits((physical_address)); \
+ u32 upper = upper_32_bits((physical_address)); \
+ \
+ if (lower + (value) < lower) \
+ upper += 1; \
+ \
+ lower += (value); \
+ sci_cb_make_physical_address(physical_address, upper, lower); \
+ }
+
+/**
+ * sci_physical_address_subtract() -
+ *
+ * This macro simply performs subtraction on an dma_addr_t type. The
+ * lower u32 value is "clipped" or "wrapped" back through 0. When this occurs
+ * the upper 32-bits are decremented by 1.
+ */
+#define sci_physical_address_subtract(physical_address, value) \
+ { \
+ u32 lower = lower_32_bits((physical_address)); \
+ u32 upper = upper_32_bits((physical_address)); \
+ \
+ if (lower - (value) > lower) \
+ upper -= 1; \
+ \
+ lower -= (value); \
+ sci_cb_make_physical_address(physical_address, upper, lower); \
+ }
+
+/**
+ * scic_word_copy_with_swap() - Copy the data from source to destination and
+ * swap the bytes during the copy.
+ * @destination: This parameter specifies the destination address to which the
+ * data is to be copied.
+ * @source: This parameter specifies the source address from which data is to
+ * be copied.
+ * @word_count: This parameter specifies the number of 32-bit words to copy and
+ * byte swap.
+ *
+ */
+void scic_word_copy_with_swap(
+ u32 *destination,
+ u32 *source,
+ u32 word_count);
+
+#endif /* _SCI_UTIL_H_ */
diff --git a/drivers/scsi/isci/core/scic_config_parameters.h b/drivers/scsi/isci/core/scic_config_parameters.h
new file mode 100644
index 000000000000..4c16a50a0658
--- /dev/null
+++ b/drivers/scsi/isci/core/scic_config_parameters.h
@@ -0,0 +1,347 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCIC_SDS_USER_PARAMETERS_H_
+#define _SCIC_SDS_USER_PARAMETERS_H_
+
+/**
+ * This file contains all of the structure definitions and interface methods
+ * that can be called by a SCIC user on the SCU Driver Standard
+ * (struct scic_sds_user_parameters) user parameter block.
+ *
+ *
+ */
+
+
+#include "sci_types.h"
+#include "sci_status.h"
+#include "intel_sas.h"
+#include "sci_controller_constants.h"
+
+struct scic_sds_controller;
+
+/**
+ *
+ *
+ * SCIC_SDS_PARM_PHY_SPEED These constants define the speeds utilized for a
+ * phy/port.
+ */
+#define SCIC_SDS_PARM_NO_SPEED 0
+
+/**
+ *
+ *
+ * This value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
+ */
+#define SCIC_SDS_PARM_GEN1_SPEED 1
+
+/**
+ *
+ *
+ * This value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
+ */
+#define SCIC_SDS_PARM_GEN2_SPEED 2
+
+/**
+ *
+ *
+ * This value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
+ */
+#define SCIC_SDS_PARM_GEN3_SPEED 3
+
+/**
+ *
+ *
+ * For range checks, the max speed generation
+ */
+#define SCIC_SDS_PARM_MAX_SPEED SCIC_SDS_PARM_GEN3_SPEED
+
+/**
+ * struct scic_sds_user_parameters - This structure delineates the various user
+ * parameters that can be changed by the core user.
+ *
+ *
+ */
+struct scic_sds_user_parameters {
+ struct {
+ /**
+ * This field specifies the NOTIFY (ENABLE SPIN UP) primitive
+ * insertion frequency for this phy index.
+ */
+ u32 notify_enable_spin_up_insertion_frequency;
+
+ /**
+ * This method specifies the number of transmitted DWORDs within which
+ * to transmit a single ALIGN primitive. This value applies regardless
+ * of what type of device is attached or connection state. A value of
+ * 0 indicates that no ALIGN primitives will be inserted.
+ */
+ u16 align_insertion_frequency;
+
+ /**
+ * This method specifies the number of transmitted DWORDs within which
+ * to transmit 2 ALIGN primitives. This applies for SAS connections
+ * only. A minimum value of 3 is required for this field.
+ */
+ u16 in_connection_align_insertion_frequency;
+
+ /**
+ * This field indicates the maximum speed generation to be utilized
+ * by phys in the supplied port.
+ * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
+ * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
+ * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
+ */
+ u8 max_speed_generation;
+
+ } phys[SCI_MAX_PHYS];
+
+ /**
+ * This field specifies the maximum number of direct attached devices
+ * that can have power supplied to them simultaneously.
+ */
+ u8 max_number_concurrent_device_spin_up;
+
+ /**
+ * This field specifies the number of seconds to allow a phy to consume
+ * power before yielding to another phy.
+ *
+ */
+ u8 phy_spin_up_delay_interval;
+
+ /**
+ * These timer values specifies how long a link will remain open with no
+ * activity in increments of a microsecond, it can be in increments of
+ * 100 microseconds if the upper most bit is set.
+ *
+ */
+ u16 stp_inactivity_timeout;
+ u16 ssp_inactivity_timeout;
+
+ /**
+ * These timer values specifies how long a link will remain open in increments
+ * of 100 microseconds.
+ *
+ */
+ u16 stp_max_occupancy_timeout;
+ u16 ssp_max_occupancy_timeout;
+
+ /**
+ * This timer value specifies how long a link will remain open with no
+ * outbound traffic in increments of a microsecond.
+ *
+ */
+ u8 no_outbound_task_timeout;
+
+};
+
+/**
+ * This structure/union specifies the various different user parameter sets
+ * available. Each type is specific to a hardware controller version.
+ *
+ * union scic_user_parameters
+ */
+union scic_user_parameters {
+ /**
+ * This field specifies the user parameters specific to the
+ * Storage Controller Unit (SCU) Driver Standard (SDS) version
+ * 1.
+ */
+ struct scic_sds_user_parameters sds1;
+
+};
+
+
+/**
+ *
+ *
+ * SCIC_SDS_OEM_PHY_MASK These constants define the valid values for phy_mask
+ */
+
+/**
+ *
+ *
+ * This is the min value assignable to a port's phy mask
+ */
+#define SCIC_SDS_PARM_PHY_MASK_MIN 0x0
+
+/**
+ *
+ *
+ * This is the max value assignable to a port's phy mask
+ */
+#define SCIC_SDS_PARM_PHY_MASK_MAX 0xF
+
+/**
+ * struct scic_sds_oem_parameters - This structure delineates the various OEM
+ * parameters that must be set the core user.
+ *
+ *
+ */
+struct scic_sds_oem_parameters {
+ struct {
+ /**
+ * This field indicates whether Spread Spectrum Clocking (SSC)
+ * should be enabled or disabled.
+ */
+ bool do_enable_ssc;
+
+ } controller;
+
+ struct {
+ /**
+ * This field specifies the phys to be contained inside a port.
+ * The bit position in the mask specifies the index of the phy
+ * to be contained in the port. Multiple bits (i.e. phys)
+ * can be contained in a single port.
+ */
+ u8 phy_mask;
+
+ } ports[SCI_MAX_PORTS];
+
+ struct {
+ /**
+ * This field specifies the SAS address to be transmitted on
+ * for this phy index.
+ */
+ struct sci_sas_address sas_address;
+
+ } phys[SCI_MAX_PHYS];
+
+};
+
+/**
+ * This structure/union specifies the various different OEM parameter sets
+ * available. Each type is specific to a hardware controller version.
+ *
+ * union scic_oem_parameters
+ */
+union scic_oem_parameters {
+ /**
+ * This field specifies the OEM parameters specific to the
+ * Storage Controller Unit (SCU) Driver Standard (SDS) version
+ * 1.
+ */
+ struct scic_sds_oem_parameters sds1;
+
+};
+
+/**
+ * scic_user_parameters_set() - This method allows the user to attempt to
+ * change the user parameters utilized by the controller.
+ * @controller: This parameter specifies the controller on which to set the
+ * user parameters.
+ * @user_parameters: This parameter specifies the USER_PARAMETERS object
+ * containing the potential new values.
+ *
+ * Indicate if the update of the user parameters was successful. SCI_SUCCESS
+ * This value is returned if the operation succeeded. SCI_FAILURE_INVALID_STATE
+ * This value is returned if the attempt to change the user parameter failed,
+ * because changing one of the parameters is not currently allowed.
+ * SCI_FAILURE_INVALID_PARAMETER_VALUE This value is returned if the user
+ * supplied an invalid interrupt coalescence time, spin up delay interval, etc.
+ */
+enum sci_status scic_user_parameters_set(
+ struct scic_sds_controller *controller,
+ union scic_user_parameters *user_parameters);
+
+/**
+ * scic_user_parameters_get() - This method allows the user to retrieve the
+ * user parameters utilized by the controller.
+ * @controller: This parameter specifies the controller on which to set the
+ * user parameters.
+ * @user_parameters: This parameter specifies the USER_PARAMETERS object into
+ * which the framework shall save it's parameters.
+ *
+ */
+void scic_user_parameters_get(
+ struct scic_sds_controller *controller,
+ union scic_user_parameters *user_parameters);
+
+/**
+ * scic_oem_parameters_set() - This method allows the user to attempt to change
+ * the OEM parameters utilized by the controller.
+ * @controller: This parameter specifies the controller on which to set the
+ * user parameters.
+ * @oem_parameters: This parameter specifies the OEM parameters object
+ * containing the potential new values.
+ *
+ * Indicate if the update of the user parameters was successful. SCI_SUCCESS
+ * This value is returned if the operation succeeded. SCI_FAILURE_INVALID_STATE
+ * This value is returned if the attempt to change the user parameter failed,
+ * because changing one of the parameters is not currently allowed.
+ * SCI_FAILURE_INVALID_PARAMETER_VALUE This value is returned if the user
+ * supplied an unsupported value for one of the OEM parameters.
+ */
+enum sci_status scic_oem_parameters_set(
+ struct scic_sds_controller *controller,
+ union scic_oem_parameters *oem_parameters);
+
+/**
+ * scic_oem_parameters_get() - This method allows the user to retreive the OEM
+ * parameters utilized by the controller.
+ * @controller: This parameter specifies the controller on which to set the
+ * user parameters.
+ * @oem_parameters: This parameter specifies the OEM parameters object in which
+ * to write the core's OEM parameters.
+ *
+ */
+void scic_oem_parameters_get(
+ struct scic_sds_controller *controller,
+ union scic_oem_parameters *oem_parameters);
+
+
+#endif /* _SCIC_SDS_USER_PARAMETERS_H_ */
+
diff --git a/drivers/scsi/isci/core/scic_controller.h b/drivers/scsi/isci/core/scic_controller.h
new file mode 100644
index 000000000000..756b14fcd9a4
--- /dev/null
+++ b/drivers/scsi/isci/core/scic_controller.h
@@ -0,0 +1,586 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCIC_CONTROLLER_H_
+#define _SCIC_CONTROLLER_H_
+
+/**
+ * This file contains all of the interface methods that can be called by an
+ * SCIC user on a controller object.
+ *
+ *
+ */
+
+
+#include "sci_types.h"
+#include "sci_status.h"
+#include "sci_controller.h"
+#include "scic_config_parameters.h"
+
+struct scic_sds_request;
+struct scic_sds_phy;
+struct scic_sds_port;
+struct scic_sds_remote_device;
+
+/**
+ * enum _SCIC_INTERRUPT_TYPE - This enumeration depicts the various types of
+ * interrupts that are potentially supported by a SCI Core implementation.
+ *
+ *
+ */
+enum scic_interrupt_type {
+ SCIC_LEGACY_LINE_INTERRUPT_TYPE,
+ SCIC_MSIX_INTERRUPT_TYPE,
+
+ /**
+ * This enumeration value indicates the use of polling.
+ */
+ SCIC_NO_INTERRUPTS
+
+};
+
+/**
+ * This method is called by the SCI user in order to have the SCI
+ * implementation handle the interrupt. This method performs minimal
+ * processing to allow for streamlined interrupt time usage.
+ *
+ * SCIC_CONTROLLER_INTERRUPT_HANDLER true: returned if there is an interrupt to
+ * process and it was processed. false: returned if no interrupt was processed.
+ */
+typedef bool (*SCIC_CONTROLLER_INTERRUPT_HANDLER)(
+ struct scic_sds_controller *controller
+ );
+
+/**
+ * This method is called by the SCI user to process completions generated as a
+ * result of a previously handled interrupt. This method will result in the
+ * completion of IO requests and handling of other controller generated
+ * events. This method should be called some time after the interrupt
+ * handler.
+ *
+ * Most, if not all, of the user callback APIs are invoked from within this
+ * API. As a result, the user should be cognizent of the operating level at
+ * which they invoke this API.
+ */
+typedef void (*SCIC_CONTROLLER_COMPLETION_HANDLER)(
+ struct scic_sds_controller *controller
+ );
+
+/**
+ * struct scic_controller_handler_methods - This structure contains an
+ * interrupt handler and completion handler function pointers.
+ *
+ *
+ */
+struct scic_controller_handler_methods {
+ SCIC_CONTROLLER_INTERRUPT_HANDLER interrupt_handler;
+ SCIC_CONTROLLER_COMPLETION_HANDLER completion_handler;
+
+};
+
+/**
+ * scic_controller_construct() - This method will attempt to construct a
+ * controller object utilizing the supplied parameter information.
+ * @c: This parameter specifies the controller to be constructed.
+ * @scu_base: mapped base address of the scu registers
+ * @smu_base: mapped base address of the smu registers
+ *
+ * Indicate if the controller was successfully constructed or if it failed in
+ * some way. SCI_SUCCESS This value is returned if the controller was
+ * successfully constructed. SCI_WARNING_TIMER_CONFLICT This value is returned
+ * if the interrupt coalescence timer may cause SAS compliance issues for SMP
+ * Target mode response processing. SCI_FAILURE_UNSUPPORTED_CONTROLLER_TYPE
+ * This value is returned if the controller does not support the supplied type.
+ * SCI_FAILURE_UNSUPPORTED_INIT_DATA_VERSION This value is returned if the
+ * controller does not support the supplied initialization data version.
+ */
+enum sci_status scic_controller_construct(struct scic_sds_controller *c,
+ void __iomem *scu_base,
+ void __iomem *smu_base);
+
+/**
+ * scic_controller_enable_interrupts() - This method will enable all controller
+ * interrupts.
+ * @controller: This parameter specifies the controller for which to enable
+ * interrupts.
+ *
+ */
+void scic_controller_enable_interrupts(
+ struct scic_sds_controller *controller);
+
+/**
+ * scic_controller_disable_interrupts() - This method will disable all
+ * controller interrupts.
+ * @controller: This parameter specifies the controller for which to disable
+ * interrupts.
+ *
+ */
+void scic_controller_disable_interrupts(
+ struct scic_sds_controller *controller);
+
+/**
+ * scic_controller_get_handler_methods() - This method will return provide
+ * function pointers for the interrupt handler and completion handler. The
+ * interrupt handler is expected to be invoked at interrupt time. The
+ * completion handler is scheduled to run as a result of the interrupt
+ * handler. The completion handler performs the bulk work for processing
+ * silicon events.
+ * @interrupt_type: This parameter informs the core which type of
+ * interrupt/completion methods are being requested. These are the types:
+ * SCIC_LEGACY_LINE_INTERRUPT_TYPE, SCIC_MSIX_INTERRUPT_TYPE,
+ * SCIC_NO_INTERRUPTS (POLLING)
+ * @message_count: This parameter informs the core the number of MSI-X messages
+ * to be utilized. This parameter must be 0 when requesting legacy line
+ * based handlers.
+ * @handler_methods: The caller provides a pointer to a buffer of type
+ * struct scic_controller_handler_methods. The size depends on the combination of
+ * the interrupt_type and message_count input parameters:
+ * SCIC_LEGACY_LINE_INTERRUPT_TYPE: - size =
+ * sizeof(struct scic_controller_handler_methods) SCIC_MSIX_INTERRUPT_TYPE:
+ * sizeof(struct scic_controller_handler_methods)
+ * @handler_methods: SCIC fills out the caller's buffer with the appropriate
+ * interrupt and completion handlers based on the info provided in the
+ * interrupt_type and message_count input parameters. For
+ * SCIC_LEGACY_LINE_INTERRUPT_TYPE, the buffer receives a single
+ * struct scic_controller_handler_methods element regardless that the
+ * message_count parameter is zero. For SCIC_MSIX_INTERRUPT_TYPE, the buffer
+ * receives an array of elements of type struct scic_controller_handler_methods
+ * where the array size is equivalent to the message_count parameter. The
+ * array is zero-relative where entry zero corresponds to message-vector
+ * zero, entry one corresponds to message-vector one, and so forth.
+ *
+ * Indicate if the handler retrieval operation was successful. SCI_SUCCESS This
+ * value is returned if retrieval succeeded.
+ * SCI_FAILURE_UNSUPPORTED_MESSAGE_COUNT This value is returned if the user
+ * supplied an unsupported number of MSI-X messages. For legacy line interrupts
+ * the only valid value is 0.
+ */
+enum sci_status scic_controller_get_handler_methods(
+ enum scic_interrupt_type interrupt_type,
+ u16 message_count,
+ struct scic_controller_handler_methods *handler_methods);
+
+/**
+ * scic_controller_initialize() - This method will initialize the controller
+ * hardware managed by the supplied core controller object. This method
+ * will bring the physical controller hardware out of reset and enable the
+ * core to determine the capabilities of the hardware being managed. Thus,
+ * the core controller can determine it's exact physical (DMA capable)
+ * memory requirements.
+ * @controller: This parameter specifies the controller to be initialized.
+ *
+ * The SCI Core user must have called scic_controller_construct() on the
+ * supplied controller object previously. Indicate if the controller was
+ * successfully initialized or if it failed in some way. SCI_SUCCESS This value
+ * is returned if the controller hardware was successfully initialized.
+ */
+enum sci_status scic_controller_initialize(
+ struct scic_sds_controller *controller);
+
+/**
+ * scic_controller_get_suggested_start_timeout() - This method returns the
+ * suggested scic_controller_start() timeout amount. The user is free to
+ * use any timeout value, but this method provides the suggested minimum
+ * start timeout value. The returned value is based upon empirical
+ * information determined as a result of interoperability testing.
+ * @controller: the handle to the controller object for which to return the
+ * suggested start timeout.
+ *
+ * This method returns the number of milliseconds for the suggested start
+ * operation timeout.
+ */
+u32 scic_controller_get_suggested_start_timeout(
+ struct scic_sds_controller *controller);
+
+/**
+ * scic_controller_start() - This method will start the supplied core
+ * controller. This method will start the staggered spin up operation. The
+ * SCI User completion callback is called when the following conditions are
+ * met: -# the return status of this method is SCI_SUCCESS. -# after all of
+ * the phys have successfully started or been given the opportunity to start.
+ * @controller: the handle to the controller object to start.
+ * @timeout: This parameter specifies the number of milliseconds in which the
+ * start operation should complete.
+ *
+ * The SCI Core user must have filled in the physical memory descriptor
+ * structure via the sci_controller_get_memory_descriptor_list() method. The
+ * SCI Core user must have invoked the scic_controller_initialize() method
+ * prior to invoking this method. The controller must be in the INITIALIZED or
+ * STARTED state. Indicate if the controller start method succeeded or failed
+ * in some way. SCI_SUCCESS if the start operation succeeded.
+ * SCI_WARNING_ALREADY_IN_STATE if the controller is already in the STARTED
+ * state. SCI_FAILURE_INVALID_STATE if the controller is not either in the
+ * INITIALIZED or STARTED states. SCI_FAILURE_INVALID_MEMORY_DESCRIPTOR if
+ * there are inconsistent or invalid values in the supplied
+ * struct sci_physical_memory_descriptor array.
+ */
+enum sci_status scic_controller_start(
+ struct scic_sds_controller *controller,
+ u32 timeout);
+
+/**
+ * scic_controller_stop() - This method will stop an individual controller
+ * object.This method will invoke the associated user callback upon
+ * completion. The completion callback is called when the following
+ * conditions are met: -# the method return status is SCI_SUCCESS. -# the
+ * controller has been quiesced. This method will ensure that all IO
+ * requests are quiesced, phys are stopped, and all additional operation by
+ * the hardware is halted.
+ * @controller: the handle to the controller object to stop.
+ * @timeout: This parameter specifies the number of milliseconds in which the
+ * stop operation should complete.
+ *
+ * The controller must be in the STARTED or STOPPED state. Indicate if the
+ * controller stop method succeeded or failed in some way. SCI_SUCCESS if the
+ * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the
+ * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the
+ * controller is not either in the STARTED or STOPPED states.
+ */
+enum sci_status scic_controller_stop(
+ struct scic_sds_controller *controller,
+ u32 timeout);
+
+/**
+ * scic_controller_reset() - This method will reset the supplied core
+ * controller regardless of the state of said controller. This operation is
+ * considered destructive. In other words, all current operations are wiped
+ * out. No IO completions for outstanding devices occur. Outstanding IO
+ * requests are not aborted or completed at the actual remote device.
+ * @controller: the handle to the controller object to reset.
+ *
+ * Indicate if the controller reset method succeeded or failed in some way.
+ * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if
+ * the controller reset operation is unable to complete.
+ */
+enum sci_status scic_controller_reset(
+ struct scic_sds_controller *controller);
+
+/**
+ * scic_controller_start_io() - This method is called by the SCI user to
+ * send/start an IO request. If the method invocation is successful, then
+ * the IO request has been queued to the hardware for processing.
+ * @controller: the handle to the controller object for which to start an IO
+ * request.
+ * @remote_device: the handle to the remote device object for which to start an
+ * IO request.
+ * @io_request: the handle to the io request object to start.
+ * @io_tag: This parameter specifies a previously allocated IO tag that the
+ * user desires to be utilized for this request. This parameter is optional.
+ * The user is allowed to supply SCI_CONTROLLER_INVALID_IO_TAG as the value
+ * for this parameter.
+ *
+ * - IO tags are a protected resource. It is incumbent upon the SCI Core user
+ * to ensure that each of the methods that may allocate or free available IO
+ * tags are handled in a mutually exclusive manner. This method is one of said
+ * methods requiring proper critical code section protection (e.g. semaphore,
+ * spin-lock, etc.). - For SATA, the user is required to manage NCQ tags. As a
+ * result, it is expected the user will have set the NCQ tag field in the host
+ * to device register FIS prior to calling this method. There is also a
+ * requirement for the user to call scic_stp_io_set_ncq_tag() prior to invoking
+ * the scic_controller_start_io() method. scic_controller_allocate_tag() for
+ * more information on allocating a tag. Indicate if the controller
+ * successfully started the IO request. SCI_IO_SUCCESS if the IO request was
+ * successfully started. Determine the failure situations and return values.
+ */
+enum sci_io_status scic_controller_start_io(
+ struct scic_sds_controller *controller,
+ struct scic_sds_remote_device *remote_device,
+ struct scic_sds_request *io_request,
+ u16 io_tag);
+
+
+/**
+ * scic_controller_start_task() - This method is called by the SCIC user to
+ * send/start a framework task management request.
+ * @controller: the handle to the controller object for which to start the task
+ * management request.
+ * @remote_device: the handle to the remote device object for which to start
+ * the task management request.
+ * @task_request: the handle to the task request object to start.
+ * @io_tag: This parameter specifies a previously allocated IO tag that the
+ * user desires to be utilized for this request. Note this not the io_tag
+ * of the request being managed. It is to be utilized for the task request
+ * itself. This parameter is optional. The user is allowed to supply
+ * SCI_CONTROLLER_INVALID_IO_TAG as the value for this parameter.
+ *
+ * - IO tags are a protected resource. It is incumbent upon the SCI Core user
+ * to ensure that each of the methods that may allocate or free available IO
+ * tags are handled in a mutually exclusive manner. This method is one of said
+ * methods requiring proper critical code section protection (e.g. semaphore,
+ * spin-lock, etc.). - The user must synchronize this task with completion
+ * queue processing. If they are not synchronized then it is possible for the
+ * io requests that are being managed by the task request can complete before
+ * starting the task request. scic_controller_allocate_tag() for more
+ * information on allocating a tag. Indicate if the controller successfully
+ * started the IO request. SCI_TASK_SUCCESS if the task request was
+ * successfully started. SCI_TASK_FAILURE_REQUIRES_SCSI_ABORT This value is
+ * returned if there is/are task(s) outstanding that require termination or
+ * completion before this request can succeed.
+ */
+enum sci_task_status scic_controller_start_task(
+ struct scic_sds_controller *controller,
+ struct scic_sds_remote_device *remote_device,
+ struct scic_sds_request *task_request,
+ u16 io_tag);
+
+/**
+ * scic_controller_complete_task() - This method will perform core specific
+ * completion operations for task management request. After this method is
+ * invoked, the user should consider the task request as invalid until it is
+ * properly reused (i.e. re-constructed).
+ * @controller: The handle to the controller object for which to complete the
+ * task management request.
+ * @remote_device: The handle to the remote device object for which to complete
+ * the task management request.
+ * @task_request: the handle to the task management request object to complete.
+ *
+ * Indicate if the controller successfully completed the task management
+ * request. SCI_SUCCESS if the completion process was successful.
+ */
+enum sci_status scic_controller_complete_task(
+ struct scic_sds_controller *controller,
+ struct scic_sds_remote_device *remote_device,
+ struct scic_sds_request *task_request);
+
+
+/**
+ * scic_controller_terminate_request() - This method is called by the SCI Core
+ * user to terminate an ongoing (i.e. started) core IO request. This does
+ * not abort the IO request at the target, but rather removes the IO request
+ * from the host controller.
+ * @controller: the handle to the controller object for which to terminate a
+ * request.
+ * @remote_device: the handle to the remote device object for which to
+ * terminate a request.
+ * @request: the handle to the io or task management request object to
+ * terminate.
+ *
+ * Indicate if the controller successfully began the terminate process for the
+ * IO request. SCI_SUCCESS if the terminate process was successfully started
+ * for the request. Determine the failure situations and return values.
+ */
+enum sci_status scic_controller_terminate_request(
+ struct scic_sds_controller *controller,
+ struct scic_sds_remote_device *remote_device,
+ struct scic_sds_request *request);
+
+/**
+ * scic_controller_complete_io() - This method will perform core specific
+ * completion operations for an IO request. After this method is invoked,
+ * the user should consider the IO request as invalid until it is properly
+ * reused (i.e. re-constructed).
+ * @controller: The handle to the controller object for which to complete the
+ * IO request.
+ * @remote_device: The handle to the remote device object for which to complete
+ * the IO request.
+ * @io_request: the handle to the io request object to complete.
+ *
+ * - IO tags are a protected resource. It is incumbent upon the SCI Core user
+ * to ensure that each of the methods that may allocate or free available IO
+ * tags are handled in a mutually exclusive manner. This method is one of said
+ * methods requiring proper critical code section protection (e.g. semaphore,
+ * spin-lock, etc.). - If the IO tag for a request was allocated, by the SCI
+ * Core user, using the scic_controller_allocate_io_tag() method, then it is
+ * the responsibility of the caller to invoke the scic_controller_free_io_tag()
+ * method to free the tag (i.e. this method will not free the IO tag). Indicate
+ * if the controller successfully completed the IO request. SCI_SUCCESS if the
+ * completion process was successful.
+ */
+enum sci_status scic_controller_complete_io(
+ struct scic_sds_controller *controller,
+ struct scic_sds_remote_device *remote_device,
+ struct scic_sds_request *io_request);
+
+
+/**
+ * scic_controller_get_port_handle() - This method simply provides the user
+ * with a unique handle for a given SAS/SATA core port index.
+ * @controller: This parameter represents the handle to the controller object
+ * from which to retrieve a port (SAS or SATA) handle.
+ * @port_index: This parameter specifies the port index in the controller for
+ * which to retrieve the port handle. 0 <= port_index < maximum number of
+ * phys.
+ * @port_handle: This parameter specifies the retrieved port handle to be
+ * provided to the caller.
+ *
+ * Indicate if the retrieval of the port handle was successful. SCI_SUCCESS
+ * This value is returned if the retrieval was successful.
+ * SCI_FAILURE_INVALID_PORT This value is returned if the supplied port id is
+ * not in the supported range.
+ */
+enum sci_status scic_controller_get_port_handle(
+ struct scic_sds_controller *controller,
+ u8 port_index,
+ struct scic_sds_port **port_handle);
+
+/**
+ * scic_controller_get_phy_handle() - This method simply provides the user with
+ * a unique handle for a given SAS/SATA phy index/identifier.
+ * @controller: This parameter represents the handle to the controller object
+ * from which to retrieve a phy (SAS or SATA) handle.
+ * @phy_index: This parameter specifies the phy index in the controller for
+ * which to retrieve the phy handle. 0 <= phy_index < maximum number of phys.
+ * @phy_handle: This parameter specifies the retrieved phy handle to be
+ * provided to the caller.
+ *
+ * Indicate if the retrieval of the phy handle was successful. SCI_SUCCESS This
+ * value is returned if the retrieval was successful. SCI_FAILURE_INVALID_PHY
+ * This value is returned if the supplied phy id is not in the supported range.
+ */
+enum sci_status scic_controller_get_phy_handle(
+ struct scic_sds_controller *controller,
+ u8 phy_index,
+ struct scic_sds_phy **phy_handle);
+
+/**
+ * scic_controller_allocate_io_tag() - This method will allocate a tag from the
+ * pool of free IO tags. Direct allocation of IO tags by the SCI Core user
+ * is optional. The scic_controller_start_io() method will allocate an IO
+ * tag if this method is not utilized and the tag is not supplied to the IO
+ * construct routine. Direct allocation of IO tags may provide additional
+ * performance improvements in environments capable of supporting this usage
+ * model. Additionally, direct allocation of IO tags also provides
+ * additional flexibility to the SCI Core user. Specifically, the user may
+ * retain IO tags across the lives of multiple IO requests.
+ * @controller: the handle to the controller object for which to allocate the
+ * tag.
+ *
+ * IO tags are a protected resource. It is incumbent upon the SCI Core user to
+ * ensure that each of the methods that may allocate or free available IO tags
+ * are handled in a mutually exclusive manner. This method is one of said
+ * methods requiring proper critical code section protection (e.g. semaphore,
+ * spin-lock, etc.). An unsigned integer representing an available IO tag.
+ * SCI_CONTROLLER_INVALID_IO_TAG This value is returned if there are no
+ * currently available tags to be allocated. All return other values indicate a
+ * legitimate tag.
+ */
+u16 scic_controller_allocate_io_tag(
+ struct scic_sds_controller *controller);
+
+/**
+ * scic_controller_free_io_tag() - This method will free an IO tag to the pool
+ * of free IO tags. This method provides the SCI Core user more flexibility
+ * with regards to IO tags. The user may desire to keep an IO tag after an
+ * IO request has completed, because they plan on re-using the tag for a
+ * subsequent IO request. This method is only legal if the tag was
+ * allocated via scic_controller_allocate_io_tag().
+ * @controller: This parameter specifies the handle to the controller object
+ * for which to free/return the tag.
+ * @io_tag: This parameter represents the tag to be freed to the pool of
+ * available tags.
+ *
+ * - IO tags are a protected resource. It is incumbent upon the SCI Core user
+ * to ensure that each of the methods that may allocate or free available IO
+ * tags are handled in a mutually exclusive manner. This method is one of said
+ * methods requiring proper critical code section protection (e.g. semaphore,
+ * spin-lock, etc.). - If the IO tag for a request was allocated, by the SCI
+ * Core user, using the scic_controller_allocate_io_tag() method, then it is
+ * the responsibility of the caller to invoke this method to free the tag. This
+ * method returns an indication of whether the tag was successfully put back
+ * (freed) to the pool of available tags. SCI_SUCCESS This return value
+ * indicates the tag was successfully placed into the pool of available IO
+ * tags. SCI_FAILURE_INVALID_IO_TAG This value is returned if the supplied tag
+ * is not a valid IO tag value.
+ */
+enum sci_status scic_controller_free_io_tag(
+ struct scic_sds_controller *controller,
+ u16 io_tag);
+
+
+
+
+/**
+ * scic_controller_set_mode() - This method allows the user to configure the
+ * SCI core into either a performance mode or a memory savings mode.
+ * @controller: This parameter represents the handle to the controller object
+ * for which to update the operating mode.
+ * @mode: This parameter specifies the new mode for the controller.
+ *
+ * Indicate if the user successfully change the operating mode of the
+ * controller. SCI_SUCCESS The user successfully updated the mode.
+ */
+enum sci_status scic_controller_set_mode(
+ struct scic_sds_controller *controller,
+ enum sci_controller_mode mode);
+
+
+/**
+ * scic_controller_set_interrupt_coalescence() - This method allows the user to
+ * configure the interrupt coalescence.
+ * @controller: This parameter represents the handle to the controller object
+ * for which its interrupt coalesce register is overridden.
+ * @coalesce_number: Used to control the number of entries in the Completion
+ * Queue before an interrupt is generated. If the number of entries exceed
+ * this number, an interrupt will be generated. The valid range of the input
+ * is [0, 256]. A setting of 0 results in coalescing being disabled.
+ * @coalesce_timeout: Timeout value in microseconds. The valid range of the
+ * input is [0, 2700000] . A setting of 0 is allowed and results in no
+ * interrupt coalescing timeout.
+ *
+ * Indicate if the user successfully set the interrupt coalesce parameters.
+ * SCI_SUCCESS The user successfully updated the interrutp coalescence.
+ * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range.
+ */
+enum sci_status scic_controller_set_interrupt_coalescence(
+ struct scic_sds_controller *controller,
+ u32 coalesce_number,
+ u32 coalesce_timeout);
+
+struct device;
+struct scic_sds_controller *scic_controller_alloc(struct device *dev);
+
+
+#endif /* _SCIC_CONTROLLER_H_ */
+
diff --git a/drivers/scsi/isci/core/scic_io_request.h b/drivers/scsi/isci/core/scic_io_request.h
new file mode 100644
index 000000000000..7378f335066c
--- /dev/null
+++ b/drivers/scsi/isci/core/scic_io_request.h
@@ -0,0 +1,512 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCIC_IO_REQUEST_H_
+#define _SCIC_IO_REQUEST_H_
+
+/**
+ * This file contains the structures and interface methods that can be
+ * referenced and used by the SCI user for the SCI IO request object.
+ *
+ * Determine the failure situations and return values.
+ */
+
+
+#include "sci_types.h"
+#include "sci_status.h"
+#include "intel_sas.h"
+
+struct scic_sds_request;
+struct scic_sds_remote_device;
+struct scic_sds_controller;
+
+/**
+ * struct scic_io_parameters - This structure contains additional optional
+ * parameters for SSP IO requests. These parameters are utilized with the
+ * scic_io_request_construct_advanced_ssp() method.
+ *
+ * Add Block-guard/DIF, TLR
+ */
+struct scic_io_parameters {
+ /**
+ * This sub-structure contains SCSI specific features (for use with SSP
+ * IO requests).
+ */
+ struct {
+ /**
+ * Data Integrity Format (DIF) is also known as protection information
+ * or block-guard. This sub-structure contains DIF specific feature
+ * information for SSP IO requests.
+ */
+ struct {
+ void *placeholder;
+ } dif;
+
+ /**
+ * Transport Layer Retries (TLR) is an SSP protocol specific feature.
+ * This sub-structure contains Transport Layer Retries (TLR) specific
+ * feature information for SSP IO requests.
+ */
+ struct {
+ void *placeholder;
+ } tlr;
+
+ } scsi;
+
+};
+
+/**
+ * struct scic_passthru_request_callbacks - This structure contains the pointer
+ * to the callback functions for constructing the passthrough request common
+ * to SSP, SMP and STP. This structure must be set by the win sci layer
+ * before the passthrough build is called
+ *
+ *
+ */
+struct scic_passthru_request_callbacks {
+ /**
+ * Function pointer to get the phy identifier for passthrough request.
+ */
+ u32 (*scic_cb_passthru_get_phy_identifier)(void *, u8 *);
+ /**
+ * Function pointer to get the port identifier for passthrough request.
+ */
+ u32 (*scic_cb_passthru_get_port_identifier)(void *, u8 *);
+ /**
+ * Function pointer to get the connection rate for passthrough request.
+ */
+ u32 (*scic_cb_passthru_get_connection_rate)(void *, void *);
+ /**
+ * Function pointer to get the destination sas address for passthrough request.
+ */
+ void (*scic_cb_passthru_get_destination_sas_address)(void *, u8 **);
+ /**
+ * Function pointer to get the transfer length for passthrough request.
+ */
+ u32 (*scic_cb_passthru_get_transfer_length)(void *);
+ /**
+ * Function pointer to get the data direction for passthrough request.
+ */
+ u32 (*scic_cb_passthru_get_data_direction)(void *);
+
+};
+
+/**
+ * struct scic_ssp_passthru_request_callbacks - This structure contains the
+ * pointer to the callback functions for constructing the passthrough
+ * request specific to SSP. This structure must be set by the win sci layer
+ * before the passthrough build is called
+ *
+ *
+ */
+struct scic_ssp_passthru_request_callbacks {
+ /**
+ * Common callbacks for all Passthru requests
+ */
+ struct scic_passthru_request_callbacks common_callbacks;
+ /**
+ * Function pointer to get the lun for passthrough request.
+ */
+ void (*scic_cb_ssp_passthru_get_lun)(void *, u8 **);
+ /**
+ * Function pointer to get the cdb
+ */
+ void (*scic_cb_ssp_passthru_get_cdb)(void *, u32 *, u8 **, u32 *, u8 **);
+ /**
+ * Function pointer to get the task attribute for passthrough request.
+ */
+ u32 (*scic_cb_ssp_passthru_get_task_attribute)(void *);
+};
+
+/**
+ * struct scic_stp_passthru_request_callbacks - This structure contains the
+ * pointer to the callback functions for constructing the passthrough
+ * request specific to STP. This structure must be set by the win sci layer
+ * before the passthrough build is called
+ *
+ *
+ */
+struct scic_stp_passthru_request_callbacks {
+ /**
+ * Common callbacks for all Passthru requests
+ */
+ struct scic_passthru_request_callbacks common_callbacks;
+ /**
+ * Function pointer to get the protocol for passthrough request.
+ */
+ u8 (*scic_cb_stp_passthru_get_protocol)(void *);
+ /**
+ * Function pointer to get the resgister fis
+ */
+ void (*scic_cb_stp_passthru_get_register_fis)(void *, u8 **);
+ /**
+ * Function pointer to get the MULTIPLE_COUNT (bits 5,6,7 in Byte 1 in the SAT-specific SCSI extenstion in ATA Pass-through (0x85))
+ */
+ u8 (*scic_cb_stp_passthru_get_multiplecount)(void *);
+ /**
+ * Function pointer to get the EXTEND (bit 0 in Byte 1 the SAT-specific SCSI extenstion in ATA Pass-through (0x85))
+ */
+ u8 (*scic_cb_stp_passthru_get_extend)(void *);
+ /**
+ * Function pointer to get the CK_COND (bit 5 in Byte 2 the SAT-specific SCSI extenstion in ATA Pass-through (0x85))
+ */
+ u8 (*scic_cb_stp_passthru_get_ckcond)(void *);
+ /**
+ * Function pointer to get the T_DIR (bit 3 in Byte 2 the SAT-specific SCSI extenstion in ATA Pass-through (0x85))
+ */
+ u8 (*scic_cb_stp_passthru_get_tdir)(void *);
+ /**
+ * Function pointer to get the BYTE_BLOCK (bit 2 in Byte 2 the SAT-specific SCSI extenstion in ATA Pass-through (0x85))
+ */
+ u8 (*scic_cb_stp_passthru_get_byteblock)(void *);
+ /**
+ * Function pointer to get the T_LENGTH (bits 0,1 in Byte 2 the SAT-specific SCSI extenstion in ATA Pass-through (0x85))
+ */
+ u8 (*scic_cb_stp_passthru_get_tlength)(void *);
+
+};
+
+/**
+ * struct scic_smp_passthru_request_callbacks - This structure contains the
+ * pointer to the callback functions for constructing the passthrough
+ * request specific to SMP. This structure must be set by the win sci layer
+ * before the passthrough build is called
+ *
+ *
+ */
+struct scic_smp_passthru_request_callbacks {
+ /**
+ * Common callbacks for all Passthru requests
+ */
+ struct scic_passthru_request_callbacks common_callbacks;
+
+ /**
+ * Function pointer to get the length of the smp request and its length
+ */
+ u32 (*scic_cb_smp_passthru_get_request)(void *, u8 **);
+ /**
+ * Function pointer to get the frame type of the smp request
+ */
+ u8 (*scic_cb_smp_passthru_get_frame_type)(void *);
+ /**
+ * Function pointer to get the function in the the smp request
+ */
+ u8 (*scic_cb_smp_passthru_get_function)(void *);
+
+ /**
+ * Function pointer to get the "allocated response length" in the the smp request
+ */
+ u8 (*scic_cb_smp_passthru_get_allocated_response_length)(void *);
+
+};
+
+/**
+ * This enumeration specifies the transport protocol utilized for the request.
+ *
+ *
+ */
+typedef enum {
+ /**
+ * This enumeration constant indicates that no protocol has yet been
+ * set.
+ */
+ SCIC_NO_PROTOCOL,
+
+ /**
+ * This enumeration constant indicates that the protocol utilized
+ * is the Serial Management Protocol.
+ */
+ SCIC_SMP_PROTOCOL,
+
+ /**
+ * This enumeration constant indicates that the protocol utilized
+ * is the Serial SCSI Protocol.
+ */
+ SCIC_SSP_PROTOCOL,
+
+ /**
+ * This enumeration constant indicates that the protocol utilized
+ * is the Serial-ATA Tunneling Protocol.
+ */
+ SCIC_STP_PROTOCOL
+
+} SCIC_TRANSPORT_PROTOCOL;
+
+
+/**
+ * scic_io_request_get_object_size() - This method simply returns the size
+ * required to build an SCI based IO request object.
+ *
+ * Return the size of the SCI IO request object.
+ */
+u32 scic_io_request_get_object_size(
+ void);
+
+/**
+ * scic_io_request_construct() - This method is called by the SCI user to
+ * construct all SCI Core IO requests. Memory initialization and
+ * functionality common to all IO request types is performed in this method.
+ * @scic_controller: the handle to the core controller object for which to
+ * build an IO request.
+ * @scic_remote_device: the handle to the core remote device object for which
+ * to build an IO request.
+ * @io_tag: This parameter specifies the IO tag to be associated with this
+ * request. If SCI_CONTROLLER_INVALID_IO_TAG is passed, then a copy of the
+ * request is built internally. The request will be copied into the actual
+ * controller request memory when the IO tag is allocated internally during
+ * the scic_controller_start_io() method.
+ * @user_io_request_object: This parameter specifies the user IO request to be
+ * utilized during IO construction. This IO pointer will become the
+ * associated object for the core IO request object.
+ * @scic_io_request_memory: This parameter specifies the memory location to be
+ * utilized when building the core request.
+ * @new_scic_io_request_handle: This parameter specifies a pointer to the
+ * handle the core will expect in further interactions with the core IO
+ * request object.
+ *
+ * The SCI core implementation will create an association between the user IO
+ * request object and the core IO request object. Indicate if the controller
+ * successfully built the IO request. SCI_SUCCESS This value is returned if the
+ * IO request was successfully built.
+ */
+enum sci_status scic_io_request_construct(
+ struct scic_sds_controller *scic_controller,
+ struct scic_sds_remote_device *scic_remote_device,
+ u16 io_tag,
+ void *user_io_request_object,
+ void *scic_io_request_memory,
+ struct scic_sds_request **new_scic_io_request_handle);
+
+/**
+ * scic_io_request_construct_basic_ssp() - This method is called by the SCI
+ * user to build an SSP IO request.
+ * @scic_io_request: This parameter specifies the handle to the io request
+ * object to be built.
+ *
+ * - The user must have previously called scic_io_request_construct() on the
+ * supplied IO request. Indicate if the controller successfully built the IO
+ * request. SCI_SUCCESS This value is returned if the IO request was
+ * successfully built. SCI_FAILURE_UNSUPPORTED_PROTOCOL This value is returned
+ * if the remote_device does not support the SSP protocol.
+ * SCI_FAILURE_INVALID_ASSOCIATION This value is returned if the user did not
+ * properly set the association between the SCIC IO request and the user's IO
+ * request. Please refer to the sci_object_set_association() routine for more
+ * information.
+ */
+enum sci_status scic_io_request_construct_basic_ssp(
+ struct scic_sds_request *scic_io_request);
+
+
+
+
+
+/**
+ * scic_io_request_construct_basic_sata() - This method is called by the SCI
+ * Core user to build an STP IO request.
+ * @scic_io_request: This parameter specifies the handle to the io request
+ * object to be built.
+ *
+ * - The user must have previously called scic_io_request_construct() on the
+ * supplied IO request. Indicate if the controller successfully built the IO
+ * request. SCI_SUCCESS This value is returned if the IO request was
+ * successfully built. SCI_FAILURE_UNSUPPORTED_PROTOCOL This value is returned
+ * if the remote_device does not support the STP protocol.
+ * SCI_FAILURE_INVALID_ASSOCIATION This value is returned if the user did not
+ * properly set the association between the SCIC IO request and the user's IO
+ * request. Please refer to the sci_object_set_association() routine for more
+ * information.
+ */
+enum sci_status scic_io_request_construct_basic_sata(
+ struct scic_sds_request *scic_io_request);
+
+
+
+
+/**
+ * scic_io_request_construct_smp() - This method is called by the SCI user to
+ * build an SMP IO request.
+ * @scic_io_request: This parameter specifies the handle to the io request
+ * object to be built.
+ *
+ * - The user must have previously called scic_io_request_construct() on the
+ * supplied IO request. Indicate if the controller successfully built the IO
+ * request. SCI_SUCCESS This value is returned if the IO request was
+ * successfully built. SCI_FAILURE_UNSUPPORTED_PROTOCOL This value is returned
+ * if the remote_device does not support the SMP protocol.
+ * SCI_FAILURE_INVALID_ASSOCIATION This value is returned if the user did not
+ * properly set the association between the SCIC IO request and the user's IO
+ * request. Please refer to the sci_object_set_association() routine for more
+ * information.
+ */
+enum sci_status scic_io_request_construct_smp(
+ struct scic_sds_request *scic_io_request);
+
+
+
+/**
+ * scic_request_get_controller_status() - This method returns the controller
+ * specific IO/Task request status. These status values are unique to the
+ * specific controller being managed by the SCIC.
+ * @io_request: the handle to the IO or task management request object for
+ * which to retrieve the status.
+ *
+ * This method returns a value indicating the controller specific request
+ * status.
+ */
+u32 scic_request_get_controller_status(
+ struct scic_sds_request *io_request);
+
+
+
+/**
+ * scic_io_request_get_command_iu_address() - This method will return the
+ * address to the command information unit.
+ * @scic_io_request: This parameter specifies the handle to the io request
+ * object to be built.
+ *
+ * The address of the SSP/SMP command information unit.
+ */
+void *scic_io_request_get_command_iu_address(
+ struct scic_sds_request *scic_io_request);
+
+/**
+ * scic_io_request_get_response_iu_address() - This method will return the
+ * address to the response information unit. For an SSP request this buffer
+ * is only valid if the IO request is completed with the status
+ * SCI_FAILURE_IO_RESPONSE_VALID.
+ * @scic_io_request: This parameter specifies the handle to the io request
+ * object to be built.
+ *
+ * The address of the SSP/SMP response information unit.
+ */
+void *scic_io_request_get_response_iu_address(
+ struct scic_sds_request *scic_io_request);
+
+/**
+ * scic_io_request_get_io_tag() - This method will return the IO tag utilized
+ * by the IO request.
+ * @scic_io_request: This parameter specifies the handle to the io request
+ * object for which to return the IO tag.
+ *
+ * An unsigned integer representing the IO tag being utilized.
+ * SCI_CONTROLLER_INVALID_IO_TAG This value is returned if the IO does not
+ * currently have an IO tag allocated to it. All return other values indicate a
+ * legitimate tag.
+ */
+u16 scic_io_request_get_io_tag(
+ struct scic_sds_request *scic_io_request);
+
+
+/**
+ * scic_stp_io_request_set_ncq_tag() - This method will assign an NCQ tag to
+ * the io request object. The caller of this function must make sure that
+ * only valid NCQ tags are assigned to the io request object.
+ * @scic_io_request: This parameter specifies the handle to the io request
+ * object to which to assign the ncq tag.
+ * @ncq_tag: This parameter specifies the NCQ tag to be utilized for the
+ * supplied core IO request. It is up to the user to make sure that this is
+ * a valid NCQ tag.
+ *
+ * none This function is only valid for SATA NCQ requests.
+ */
+void scic_stp_io_request_set_ncq_tag(
+ struct scic_sds_request *scic_io_request,
+ u16 ncq_tag);
+
+/**
+ * scic_stp_io_request_get_h2d_reg_address() - This method will return the
+ * address of the host to device register fis region for the io request
+ * object.
+ * @scic_io_request: This parameter specifies the handle to the io request
+ * object from which to get the host to device register fis buffer.
+ *
+ * The address of the host to device register fis buffer in the io request
+ * object. This function is only valid for SATA requests.
+ */
+void *scic_stp_io_request_get_h2d_reg_address(
+ struct scic_sds_request *scic_io_request);
+
+/**
+ * scic_stp_io_request_get_d2h_reg_address() - This method will return the
+ * address of the device to host register fis region for the io request
+ * object.
+ * @scic_io_request: This parameter specifies teh handle to the io request
+ * object from which to get the device to host register fis buffer.
+ *
+ * The address fo the device to host register fis ending the io request. This
+ * function is only valid for SATA requests.
+ */
+void *scic_stp_io_request_get_d2h_reg_address(
+ struct scic_sds_request *scic_io_request);
+
+
+/**
+ * scic_io_request_get_number_of_bytes_transferred() - This method will return
+ * the number of bytes transferred from the SCU
+ * @scic_io_request: This parameter specifies the handle to the io request
+ * whose data length was not eqaul to the data length specified in the
+ * request. When the driver gets an early io completion status from the
+ * hardware, this routine should be called to get the actual number of bytes
+ * transferred
+ *
+ * The return is the number of bytes transferred when the data legth is not
+ * equal to the specified length in the io request
+ */
+u32 scic_io_request_get_number_of_bytes_transferred(
+ struct scic_sds_request *scic_io_request);
+
+
+#endif /* _SCIC_IO_REQUEST_H_ */
+
diff --git a/drivers/scsi/isci/core/scic_phy.h b/drivers/scsi/isci/core/scic_phy.h
new file mode 100644
index 000000000000..25a6140fa9e4
--- /dev/null
+++ b/drivers/scsi/isci/core/scic_phy.h
@@ -0,0 +1,303 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCIC_PHY_H_
+#define _SCIC_PHY_H_
+
+/**
+ * This file contains all of the interface methods that can be called by an
+ * SCIC user on a phy (SAS or SATA) object.
+ *
+ *
+ */
+
+
+#include "sci_types.h"
+#include "sci_status.h"
+
+#include "intel_sata.h"
+#include "intel_sas.h"
+
+struct scic_sds_phy;
+struct scic_sds_port;
+
+/**
+ * struct scic_phy_properties - This structure defines the properties common to
+ * all phys that can be retrieved.
+ *
+ *
+ */
+struct scic_phy_properties {
+ /**
+ * This field specifies the port that currently contains the
+ * supplied phy. This field may be set to SCI_INVALID_HANDLE
+ * if the phy is not currently contained in a port.
+ */
+ struct scic_sds_port *owning_port;
+
+ /**
+ * This field specifies the link rate at which the phy is
+ * currently operating.
+ */
+ enum sci_sas_link_rate negotiated_link_rate;
+
+ /**
+ * This field indicates the protocols supported by the phy.
+ */
+ struct sci_sas_identify_address_frame_protocols protocols;
+
+ /**
+ * This field specifies the index of the phy in relation to other
+ * phys within the controller. This index is zero relative.
+ */
+ u8 index;
+
+};
+
+/**
+ * struct scic_sas_phy_properties - This structure defines the properties,
+ * specific to a SAS phy, that can be retrieved.
+ *
+ *
+ */
+struct scic_sas_phy_properties {
+ /**
+ * This field delineates the Identify Address Frame received
+ * from the remote end point.
+ */
+ struct sci_sas_identify_address_frame received_iaf;
+
+ /**
+ * This field delineates the Phy capabilities structure received
+ * from the remote end point.
+ */
+ struct sas_capabilities received_capabilities;
+
+};
+
+/**
+ * struct scic_sata_phy_properties - This structure defines the properties,
+ * specific to a SATA phy, that can be retrieved.
+ *
+ *
+ */
+struct scic_sata_phy_properties {
+ /**
+ * This field delineates the signature FIS received from the
+ * attached target.
+ */
+ struct sata_fis_reg_d2h signature_fis;
+
+ /**
+ * This field specifies to the user if a port selector is connected
+ * on the specified phy.
+ */
+ bool is_port_selector_present;
+
+};
+
+/**
+ * enum scic_phy_counter_id - This enumeration depicts the various pieces of
+ * optional information that can be retrieved for a specific phy.
+ *
+ *
+ */
+enum scic_phy_counter_id {
+ /**
+ * This PHY information field tracks the number of frames received.
+ */
+ SCIC_PHY_COUNTER_RECEIVED_FRAME,
+
+ /**
+ * This PHY information field tracks the number of frames transmitted.
+ */
+ SCIC_PHY_COUNTER_TRANSMITTED_FRAME,
+
+ /**
+ * This PHY information field tracks the number of DWORDs received.
+ */
+ SCIC_PHY_COUNTER_RECEIVED_FRAME_WORD,
+
+ /**
+ * This PHY information field tracks the number of DWORDs transmitted.
+ */
+ SCIC_PHY_COUNTER_TRANSMITTED_FRAME_DWORD,
+
+ /**
+ * This PHY information field tracks the number of times DWORD
+ * synchronization was lost.
+ */
+ SCIC_PHY_COUNTER_LOSS_OF_SYNC_ERROR,
+
+ /**
+ * This PHY information field tracks the number of received DWORDs with
+ * running disparity errors.
+ */
+ SCIC_PHY_COUNTER_RECEIVED_DISPARITY_ERROR,
+
+ /**
+ * This PHY information field tracks the number of received frames with a
+ * CRC error (not including short or truncated frames).
+ */
+ SCIC_PHY_COUNTER_RECEIVED_FRAME_CRC_ERROR,
+
+ /**
+ * This PHY information field tracks the number of DONE (ACK/NAK TIMEOUT)
+ * primitives received.
+ */
+ SCIC_PHY_COUNTER_RECEIVED_DONE_ACK_NAK_TIMEOUT,
+
+ /**
+ * This PHY information field tracks the number of DONE (ACK/NAK TIMEOUT)
+ * primitives transmitted.
+ */
+ SCIC_PHY_COUNTER_TRANSMITTED_DONE_ACK_NAK_TIMEOUT,
+
+ /**
+ * This PHY information field tracks the number of times the inactivity
+ * timer for connections on the phy has been utilized.
+ */
+ SCIC_PHY_COUNTER_INACTIVITY_TIMER_EXPIRED,
+
+ /**
+ * This PHY information field tracks the number of DONE (CREDIT TIMEOUT)
+ * primitives received.
+ */
+ SCIC_PHY_COUNTER_RECEIVED_DONE_CREDIT_TIMEOUT,
+
+ /**
+ * This PHY information field tracks the number of DONE (CREDIT TIMEOUT)
+ * primitives transmitted.
+ */
+ SCIC_PHY_COUNTER_TRANSMITTED_DONE_CREDIT_TIMEOUT,
+
+ /**
+ * This PHY information field tracks the number of CREDIT BLOCKED
+ * primitives received.
+ * @note Depending on remote device implementation, credit blocks
+ * may occur regularly.
+ */
+ SCIC_PHY_COUNTER_RECEIVED_CREDIT_BLOCKED,
+
+ /**
+ * This PHY information field contains the number of short frames
+ * received. A short frame is simply a frame smaller then what is
+ * allowed by either the SAS or SATA specification.
+ */
+ SCIC_PHY_COUNTER_RECEIVED_SHORT_FRAME,
+
+ /**
+ * This PHY information field contains the number of frames received after
+ * credit has been exhausted.
+ */
+ SCIC_PHY_COUNTER_RECEIVED_FRAME_WITHOUT_CREDIT,
+
+ /**
+ * This PHY information field contains the number of frames received after
+ * a DONE has been received.
+ */
+ SCIC_PHY_COUNTER_RECEIVED_FRAME_AFTER_DONE,
+
+ /**
+ * This PHY information field contains the number of times the phy
+ * failed to achieve DWORD synchronization during speed negotiation.
+ */
+ SCIC_PHY_COUNTER_SN_DWORD_SYNC_ERROR
+};
+
+
+/**
+ * scic_sas_phy_get_properties() - This method will enable the user to retrieve
+ * information specific to a SAS phy, such as: the received identify address
+ * frame, received phy capabilities, etc.
+ * @phy: this parameter specifies the phy for which to retrieve properties.
+ * @properties: This parameter specifies the properties structure into which to
+ * copy the requested information.
+ *
+ * This method returns an indication as to whether the SAS phy properties were
+ * successfully retrieved. SCI_SUCCESS This value is returned if the SAS
+ * properties are successfully retrieved. SCI_FAILURE This value is returned if
+ * the SAS properties are not successfully retrieved (e.g. It's not a SAS Phy).
+ */
+enum sci_status scic_sas_phy_get_properties(
+ struct scic_sds_phy *phy,
+ struct scic_sas_phy_properties *properties);
+
+/**
+ * scic_sata_phy_get_properties() - This method will enable the user to
+ * retrieve information specific to a SATA phy, such as: the received
+ * signature FIS, if a port selector is present, etc.
+ * @phy: this parameter specifies the phy for which to retrieve properties.
+ * @properties: This parameter specifies the properties structure into which to
+ * copy the requested information.
+ *
+ * This method returns an indication as to whether the SATA phy properties were
+ * successfully retrieved. SCI_SUCCESS This value is returned if the SATA
+ * properties are successfully retrieved. SCI_FAILURE This value is returned if
+ * the SATA properties are not successfully retrieved (e.g. It's not a SATA
+ * Phy).
+ */
+enum sci_status scic_sata_phy_get_properties(
+ struct scic_sds_phy *phy,
+ struct scic_sata_phy_properties *properties);
+
+
+
+
+
+
+
+#endif /* _SCIC_PHY_H_ */
+
diff --git a/drivers/scsi/isci/core/scic_port.h b/drivers/scsi/isci/core/scic_port.h
new file mode 100644
index 000000000000..34d22c04aa56
--- /dev/null
+++ b/drivers/scsi/isci/core/scic_port.h
@@ -0,0 +1,213 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCIC_PORT_H_
+#define _SCIC_PORT_H_
+
+/**
+ * This file contains all of the interface methods that can be called by an SCI
+ * Core user on a SAS or SATA port.
+ *
+ *
+ */
+
+
+#include "sci_types.h"
+#include "sci_status.h"
+#include "intel_sas.h"
+
+struct scic_sds_port;
+
+enum SCIC_PORT_NOT_READY_REASON_CODE {
+ SCIC_PORT_NOT_READY_NO_ACTIVE_PHYS,
+ SCIC_PORT_NOT_READY_HARD_RESET_REQUESTED,
+ SCIC_PORT_NOT_READY_INVALID_PORT_CONFIGURATION,
+ SCIC_PORT_NOT_READY_RECONFIGURING,
+
+ SCIC_PORT_NOT_READY_REASON_CODE_MAX
+};
+
+/**
+ * struct scic_port_end_point_properties - This structure defines the
+ * properties that can be retrieved for each end-point local or remote
+ * (attached) port in the controller.
+ *
+ *
+ */
+struct scic_port_end_point_properties {
+ /**
+ * This field indicates the SAS address for the associated end
+ * point in the port.
+ */
+ struct sci_sas_address sas_address;
+
+ /**
+ * This field indicates the protocols supported by the associated
+ * end-point in the port.
+ */
+ struct sci_sas_identify_address_frame_protocols protocols;
+
+};
+
+/**
+ * struct scic_port_properties - This structure defines the properties that can
+ * be retrieved for each port in the controller.
+ *
+ *
+ */
+struct scic_port_properties {
+ /**
+ * This field specifies the logical index of the port (0 relative).
+ */
+ u32 index;
+
+ /**
+ * This field indicates the local end-point properties for port.
+ */
+ struct scic_port_end_point_properties local;
+
+ /**
+ * This field indicates the remote (attached) end-point properties
+ * for the port.
+ */
+ struct scic_port_end_point_properties remote;
+
+ /**
+ * This field specifies the phys contained inside the port.
+ */
+ u32 phy_mask;
+
+};
+
+/**
+ * scic_port_get_properties() - This method simply returns the properties
+ * regarding the port, such as: physical index, protocols, sas address, etc.
+ * @port: this parameter specifies the port for which to retrieve the physical
+ * index.
+ * @properties: This parameter specifies the properties structure into which to
+ * copy the requested information.
+ *
+ * Indicate if the user specified a valid port. SCI_SUCCESS This value is
+ * returned if the specified port was valid. SCI_FAILURE_INVALID_PORT This
+ * value is returned if the specified port is not valid. When this value is
+ * returned, no data is copied to the properties output parameter.
+ */
+enum sci_status scic_port_get_properties(
+ struct scic_sds_port *port,
+ struct scic_port_properties *properties);
+
+
+
+/**
+ * scic_port_start() - This method will make the port ready for operation.
+ * Prior to calling the start method IO operation is not possible.
+ * @port: This parameter specifies the port to be started.
+ *
+ * Indicate if the port was successfully started. SCI_SUCCESS This value is
+ * returned if the port was successfully started. SCI_WARNING_ALREADY_IN_STATE
+ * This value is returned if the port is in the process of starting.
+ * SCI_FAILURE_INVALID_PORT This value is returned if the supplied port is not
+ * valid. SCI_FAILURE_INVALID_STATE This value is returned if a start operation
+ * can't be completed due to the state of port.
+ */
+enum sci_status scic_port_start(
+ struct scic_sds_port *port);
+
+/**
+ * scic_port_stop() - This method will make the port no longer ready for
+ * operation. After invoking this method IO operation is not possible.
+ * @port: This parameter specifies the port to be stopped.
+ *
+ * Indicate if the port was successfully stopped. SCI_SUCCESS This value is
+ * returned if the port was successfully stopped. SCI_WARNING_ALREADY_IN_STATE
+ * This value is returned if the port is already stopped or in the process of
+ * stopping. SCI_FAILURE_INVALID_PORT This value is returned if the supplied
+ * port is not valid. SCI_FAILURE_INVALID_STATE This value is returned if a
+ * stop operation can't be completed due to the state of port.
+ */
+enum sci_status scic_port_stop(
+ struct scic_sds_port *port);
+
+/**
+ * scic_port_hard_reset() - This method will request the SCI implementation to
+ * perform a HARD RESET on the SAS Port. If/When the HARD RESET completes
+ * the SCI user will be notified via an SCI OS callback indicating a direct
+ * attached device was found.
+ * @port: a handle corresponding to the SAS port to be hard reset.
+ * @reset_timeout: This parameter specifies the number of milliseconds in which
+ * the port reset operation should complete.
+ *
+ * The SCI User callback in SCIC_USER_CALLBACKS_T will only be called once for
+ * each phy in the SAS Port at completion of the hard reset sequence. Return a
+ * status indicating whether the hard reset started successfully. SCI_SUCCESS
+ * This value is returned if the hard reset operation started successfully.
+ */
+enum sci_status scic_port_hard_reset(
+ struct scic_sds_port *port,
+ u32 reset_timeout);
+
+/**
+ * scic_port_enable_broadcast_change_notification() - This API method enables
+ * the broadcast change notification from underneath hardware.
+ * @port: The port upon which broadcast change notifications (BCN) are to be
+ * enabled.
+ *
+ */
+void scic_port_enable_broadcast_change_notification(
+ struct scic_sds_port *port);
+
+
+#endif /* _SCIC_PORT_H_ */
+
diff --git a/drivers/scsi/isci/core/scic_remote_device.h b/drivers/scsi/isci/core/scic_remote_device.h
new file mode 100644
index 000000000000..e8c04592763e
--- /dev/null
+++ b/drivers/scsi/isci/core/scic_remote_device.h
@@ -0,0 +1,295 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCIC_REMOTE_DEVICE_H_
+#define _SCIC_REMOTE_DEVICE_H_
+
+/**
+ * This file contains all of the interface methods that can be called by an
+ * SCIC user on the device object.
+ *
+ *
+ */
+
+
+#include "sci_types.h"
+#include "sci_status.h"
+#include "intel_sas.h"
+
+struct scic_sds_port;
+struct scic_sds_remote_device;
+
+/**
+ *
+ *
+ *
+ */
+enum scic_remote_device_not_ready_reason_code {
+ SCIC_REMOTE_DEVICE_NOT_READY_START_REQUESTED,
+ SCIC_REMOTE_DEVICE_NOT_READY_STOP_REQUESTED,
+ SCIC_REMOTE_DEVICE_NOT_READY_SATA_REQUEST_STARTED,
+ SCIC_REMOTE_DEVICE_NOT_READY_SATA_SDB_ERROR_FIS_RECEIVED,
+ SCIC_REMOTE_DEVICE_NOT_READY_SMP_REQUEST_STARTED,
+
+ SCIC_REMOTE_DEVICE_NOT_READY_REASON_CODE_MAX
+
+};
+
+/**
+ * scic_remote_device_get_object_size() - This method simply returns the
+ * maximum memory space needed to store a remote device object.
+ *
+ * a positive integer value indicating the size (in bytes) of the remote device
+ * object.
+ */
+u32 scic_remote_device_get_object_size(
+ void);
+
+struct scic_sds_port;
+struct scic_sds_remote_device;
+/**
+ * scic_remote_device_construct() - This method will perform the construction
+ * common to all remote device objects.
+ * @sci_port: SAS/SATA port through which this device is accessed.
+ * @sci_dev: remote device to construct
+ *
+ * It isn't necessary to call scic_remote_device_destruct() for device objects
+ * that have only called this method for construction. Once subsequent
+ * construction methods have been invoked (e.g.
+ * scic_remote_device_da_construct()), then destruction should occur. none
+ */
+void scic_remote_device_construct(struct scic_sds_port *sci_port,
+ struct scic_sds_remote_device *sci_dev);
+
+/**
+ * scic_remote_device_da_construct() - This method will construct a
+ * SCIC_REMOTE_DEVICE object for a direct attached (da) device. The
+ * information (e.g. IAF, Signature FIS, etc.) necessary to build the device
+ * is known to the SCI Core since it is contained in the scic_phy object.
+ * @remote_device: This parameter specifies the remote device to be destructed.
+ *
+ * The user must have previously called scic_remote_device_construct() Remote
+ * device objects are a limited resource. As such, they must be protected.
+ * Thus calls to construct and destruct are mutually exclusive and
+ * non-reentrant. Indicate if the remote device was successfully constructed.
+ * SCI_SUCCESS Returned if the device was successfully constructed.
+ * SCI_FAILURE_DEVICE_EXISTS Returned if the device has already been
+ * constructed. If it's an additional phy for the target, then call
+ * scic_remote_device_da_add_phy(). SCI_FAILURE_UNSUPPORTED_PROTOCOL Returned
+ * if the supplied parameters necessitate creation of a remote device for which
+ * the protocol is not supported by the underlying controller hardware.
+ * SCI_FAILURE_INSUFFICIENT_RESOURCES This value is returned if the core
+ * controller associated with the supplied parameters is unable to support
+ * additional remote devices.
+ */
+enum sci_status scic_remote_device_da_construct(
+ struct scic_sds_remote_device *remote_device);
+
+/**
+ * scic_remote_device_ea_construct() - This method will construct an
+ * SCIC_REMOTE_DEVICE object for an expander attached (ea) device from an
+ * SMP Discover Response.
+ * @remote_device: This parameter specifies the remote device to be destructed.
+ * @discover_response: This parameter specifies the SMP Discovery Response to
+ * be used in device creation.
+ *
+ * The user must have previously called scic_remote_device_construct() Remote
+ * device objects are a limited resource. As such, they must be protected.
+ * Thus calls to construct and destruct are mutually exclusive and
+ * non-reentrant. Indicate if the remote device was successfully constructed.
+ * SCI_SUCCESS Returned if the device was successfully constructed.
+ * SCI_FAILURE_DEVICE_EXISTS Returned if the device has already been
+ * constructed. If it's an additional phy for the target, then call
+ * scic_ea_remote_device_add_phy(). SCI_FAILURE_UNSUPPORTED_PROTOCOL Returned
+ * if the supplied parameters necessitate creation of a remote device for which
+ * the protocol is not supported by the underlying controller hardware.
+ * SCI_FAILURE_INSUFFICIENT_RESOURCES This value is returned if the core
+ * controller associated with the supplied parameters is unable to support
+ * additional remote devices.
+ */
+enum sci_status scic_remote_device_ea_construct(
+ struct scic_sds_remote_device *remote_device,
+ struct smp_response_discover *discover_response);
+
+/**
+ * scic_remote_device_destruct() - This method is utilized to free up a core's
+ * remote device object.
+ * @remote_device: This parameter specifies the remote device to be destructed.
+ *
+ * Remote device objects are a limited resource. As such, they must be
+ * protected. Thus calls to construct and destruct are mutually exclusive and
+ * non-reentrant. The return value shall indicate if the device was
+ * successfully destructed or if some failure occurred. enum sci_status This value
+ * is returned if the device is successfully destructed.
+ * SCI_FAILURE_INVALID_REMOTE_DEVICE This value is returned if the supplied
+ * device isn't valid (e.g. it's already been destoryed, the handle isn't
+ * valid, etc.).
+ */
+enum sci_status scic_remote_device_destruct(
+ struct scic_sds_remote_device *remote_device);
+
+
+
+
+
+/**
+ * scic_remote_device_start() - This method will start the supplied remote
+ * device. This method enables normal IO requests to flow through to the
+ * remote device.
+ * @remote_device: This parameter specifies the device to be started.
+ * @timeout: This parameter specifies the number of milliseconds in which the
+ * start operation should complete.
+ *
+ * An indication of whether the device was successfully started. SCI_SUCCESS
+ * This value is returned if the device was successfully started.
+ * SCI_FAILURE_INVALID_PHY This value is returned if the user attempts to start
+ * the device when there have been no phys added to it.
+ */
+enum sci_status scic_remote_device_start(
+ struct scic_sds_remote_device *remote_device,
+ u32 timeout);
+
+/**
+ * scic_remote_device_stop() - This method will stop both transmission and
+ * reception of link activity for the supplied remote device. This method
+ * disables normal IO requests from flowing through to the remote device.
+ * @remote_device: This parameter specifies the device to be stopped.
+ * @timeout: This parameter specifies the number of milliseconds in which the
+ * stop operation should complete.
+ *
+ * An indication of whether the device was successfully stopped. SCI_SUCCESS
+ * This value is returned if the transmission and reception for the device was
+ * successfully stopped.
+ */
+enum sci_status scic_remote_device_stop(
+ struct scic_sds_remote_device *remote_device,
+ u32 timeout);
+
+/**
+ * scic_remote_device_reset() - This method will reset the device making it
+ * ready for operation. This method must be called anytime the device is
+ * reset either through a SMP phy control or a port hard reset request.
+ * @remote_device: This parameter specifies the device to be reset.
+ *
+ * This method does not actually cause the device hardware to be reset. This
+ * method resets the software object so that it will be operational after a
+ * device hardware reset completes. An indication of whether the device reset
+ * was accepted. SCI_SUCCESS This value is returned if the device reset is
+ * started.
+ */
+enum sci_status scic_remote_device_reset(
+ struct scic_sds_remote_device *remote_device);
+
+/**
+ * scic_remote_device_reset_complete() - This method informs the device object
+ * that the reset operation is complete and the device can resume operation
+ * again.
+ * @remote_device: This parameter specifies the device which is to be informed
+ * of the reset complete operation.
+ *
+ * An indication that the device is resuming operation. SCI_SUCCESS the device
+ * is resuming operation.
+ */
+enum sci_status scic_remote_device_reset_complete(
+ struct scic_sds_remote_device *remote_device);
+
+
+
+/**
+ * scic_remote_device_get_connection_rate() - This method simply returns the
+ * link rate at which communications to the remote device occur.
+ * @remote_device: This parameter specifies the device for which to get the
+ * connection rate.
+ *
+ * Return the link rate at which we transfer for the supplied remote device.
+ */
+enum sci_sas_link_rate scic_remote_device_get_connection_rate(
+ struct scic_sds_remote_device *remote_device);
+
+/**
+ * scic_remote_device_get_protocols() - This method will indicate which
+ * protocols are supported by this remote device.
+ * @remote_device: This parameter specifies the device for which to return the
+ * protocol.
+ * @protocols: This parameter specifies the output values, from the remote
+ * device object, which indicate the protocols supported by the supplied
+ * remote_device.
+ *
+ * The type of protocols supported by this device. The values are returned as
+ * part of a bit mask in order to allow for multi-protocol support.
+ */
+void scic_remote_device_get_protocols(
+ struct scic_sds_remote_device *remote_device,
+ struct smp_discover_response_protocols *protocols);
+
+
+#if !defined(DISABLE_ATAPI)
+/**
+ * scic_remote_device_is_atapi() -
+ * @this_device: The device whose type is to be decided.
+ *
+ * This method first decide whether a device is a stp target, then decode the
+ * signature fis of a DA STP device to tell whether it is a standard end disk
+ * or an ATAPI device. bool Indicate a device is ATAPI device or not.
+ */
+bool scic_remote_device_is_atapi(
+ struct scic_sds_remote_device *device_handle);
+#else /* !defined(DISABLE_ATAPI) */
+#define scic_remote_device_is_atapi(device_handle) false
+#endif /* !defined(DISABLE_ATAPI) */
+
+
+#endif /* _SCIC_REMOTE_DEVICE_H_ */
+
diff --git a/drivers/scsi/isci/core/scic_sds_controller.c b/drivers/scsi/isci/core/scic_sds_controller.c
new file mode 100644
index 000000000000..35f7796df661
--- /dev/null
+++ b/drivers/scsi/isci/core/scic_sds_controller.c
@@ -0,0 +1,4147 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/device.h>
+#include "scic_controller.h"
+#include "scic_phy.h"
+#include "scic_port.h"
+#include "scic_remote_device.h"
+#include "scic_sds_controller.h"
+#include "scic_sds_controller_registers.h"
+#include "scic_sds_pci.h"
+#include "scic_sds_phy.h"
+#include "scic_sds_port_configuration_agent.h"
+#include "scic_sds_port.h"
+#include "scic_sds_remote_device.h"
+#include "scic_sds_request.h"
+#include "scic_user_callback.h"
+#include "sci_environment.h"
+#include "sci_util.h"
+#include "scu_completion_codes.h"
+#include "scu_constants.h"
+#include "scu_event_codes.h"
+#include "scu_remote_node_context.h"
+#include "scu_task_context.h"
+#include "scu_unsolicited_frame.h"
+
+#define SCU_CONTEXT_RAM_INIT_STALL_TIME 200
+
+/**
+ * smu_dcc_get_max_ports() -
+ *
+ * This macro returns the maximum number of logical ports supported by the
+ * hardware. The caller passes in the value read from the device context
+ * capacity register and this macro will mash and shift the value appropriately.
+ */
+#define smu_dcc_get_max_ports(dcc_value) \
+ (\
+ (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
+ >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \
+ )
+
+/**
+ * smu_dcc_get_max_task_context() -
+ *
+ * This macro returns the maximum number of task contexts supported by the
+ * hardware. The caller passes in the value read from the device context
+ * capacity register and this macro will mash and shift the value appropriately.
+ */
+#define smu_dcc_get_max_task_context(dcc_value) \
+ (\
+ (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
+ >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \
+ )
+
+/**
+ * smu_dcc_get_max_remote_node_context() -
+ *
+ * This macro returns the maximum number of remote node contexts supported by
+ * the hardware. The caller passes in the value read from the device context
+ * capacity register and this macro will mash and shift the value appropriately.
+ */
+#define smu_dcc_get_max_remote_node_context(dcc_value) \
+ (\
+ (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
+ >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \
+ )
+
+
+static void scic_sds_controller_power_control_timer_handler(
+ void *controller);
+#define SCIC_SDS_CONTROLLER_MIN_TIMER_COUNT 3
+#define SCIC_SDS_CONTROLLER_MAX_TIMER_COUNT 3
+
+/**
+ *
+ *
+ * The number of milliseconds to wait for a phy to start.
+ */
+#define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT 100
+
+/**
+ *
+ *
+ * The number of milliseconds to wait while a given phy is consuming power
+ * before allowing another set of phys to consume power. Ultimately, this will
+ * be specified by OEM parameter.
+ */
+#define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500
+
+/**
+ * COMPLETION_QUEUE_CYCLE_BIT() -
+ *
+ * This macro will return the cycle bit of the completion queue entry
+ */
+#define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000)
+
+/**
+ * NORMALIZE_GET_POINTER() -
+ *
+ * This macro will normalize the completion queue get pointer so its value can
+ * be used as an index into an array
+ */
+#define NORMALIZE_GET_POINTER(x) \
+ ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK)
+
+/**
+ * NORMALIZE_PUT_POINTER() -
+ *
+ * This macro will normalize the completion queue put pointer so its value can
+ * be used as an array inde
+ */
+#define NORMALIZE_PUT_POINTER(x) \
+ ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK)
+
+
+/**
+ * NORMALIZE_GET_POINTER_CYCLE_BIT() -
+ *
+ * This macro will normalize the completion queue cycle pointer so it matches
+ * the completion queue cycle bit
+ */
+#define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \
+ ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
+
+/**
+ * NORMALIZE_EVENT_POINTER() -
+ *
+ * This macro will normalize the completion queue event entry so its value can
+ * be used as an index.
+ */
+#define NORMALIZE_EVENT_POINTER(x) \
+ (\
+ ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \
+ >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \
+ )
+
+/**
+ * INCREMENT_COMPLETION_QUEUE_GET() -
+ *
+ * This macro will increment the controllers completion queue index value and
+ * possibly toggle the cycle bit if the completion queue index wraps back to 0.
+ */
+#define INCREMENT_COMPLETION_QUEUE_GET(controller, index, cycle) \
+ INCREMENT_QUEUE_GET(\
+ (index), \
+ (cycle), \
+ (controller)->completion_queue_entries, \
+ SMU_CQGR_CYCLE_BIT \
+ )
+
+/**
+ * INCREMENT_EVENT_QUEUE_GET() -
+ *
+ * This macro will increment the controllers event queue index value and
+ * possibly toggle the event cycle bit if the event queue index wraps back to 0.
+ */
+#define INCREMENT_EVENT_QUEUE_GET(controller, index, cycle) \
+ INCREMENT_QUEUE_GET(\
+ (index), \
+ (cycle), \
+ (controller)->completion_event_entries, \
+ SMU_CQGR_EVENT_CYCLE_BIT \
+ )
+
+struct sci_base_memory_descriptor_list *
+sci_controller_get_memory_descriptor_list_handle(struct scic_sds_controller *scic)
+{
+ return &scic->parent.mdl;
+}
+
+/*
+ * ****************************************************************************-
+ * * SCIC SDS Controller Initialization Methods
+ * ****************************************************************************- */
+
+/**
+ * This timer is used to start another phy after we have given up on the
+ * previous phy to transition to the ready state.
+ *
+ *
+ */
+static void scic_sds_controller_phy_startup_timeout_handler(
+ void *controller)
+{
+ enum sci_status status;
+ struct scic_sds_controller *this_controller;
+
+ this_controller = (struct scic_sds_controller *)controller;
+
+ this_controller->phy_startup_timer_pending = false;
+
+ status = SCI_FAILURE;
+
+ while (status != SCI_SUCCESS) {
+ status = scic_sds_controller_start_next_phy(this_controller);
+ }
+}
+
+/**
+ *
+ *
+ * This method initializes the phy startup operations for controller start.
+ */
+void scic_sds_controller_initialize_phy_startup(
+ struct scic_sds_controller *this_controller)
+{
+ this_controller->phy_startup_timer = scic_cb_timer_create(
+ this_controller,
+ scic_sds_controller_phy_startup_timeout_handler,
+ this_controller
+ );
+
+ this_controller->next_phy_to_start = 0;
+ this_controller->phy_startup_timer_pending = false;
+}
+
+/**
+ *
+ *
+ * This method initializes the power control operations for the controller
+ * object.
+ */
+void scic_sds_controller_initialize_power_control(
+ struct scic_sds_controller *this_controller)
+{
+ this_controller->power_control.timer = scic_cb_timer_create(
+ this_controller,
+ scic_sds_controller_power_control_timer_handler,
+ this_controller
+ );
+
+ memset(
+ this_controller->power_control.requesters,
+ 0,
+ sizeof(this_controller->power_control.requesters)
+ );
+
+ this_controller->power_control.phys_waiting = 0;
+}
+
+/* --------------------------------------------------------------------------- */
+
+#define SCU_REMOTE_NODE_CONTEXT_ALIGNMENT (32)
+#define SCU_TASK_CONTEXT_ALIGNMENT (256)
+#define SCU_UNSOLICITED_FRAME_ADDRESS_ALIGNMENT (64)
+#define SCU_UNSOLICITED_FRAME_BUFFER_ALIGNMENT (1024)
+#define SCU_UNSOLICITED_FRAME_HEADER_ALIGNMENT (64)
+
+/* --------------------------------------------------------------------------- */
+
+/**
+ * This method builds the memory descriptor table for this controller.
+ * @this_controller: This parameter specifies the controller object for which
+ * to build the memory table.
+ *
+ */
+static void scic_sds_controller_build_memory_descriptor_table(
+ struct scic_sds_controller *this_controller)
+{
+ sci_base_mde_construct(
+ &this_controller->memory_descriptors[SCU_MDE_COMPLETION_QUEUE],
+ SCU_COMPLETION_RAM_ALIGNMENT,
+ (sizeof(u32) * this_controller->completion_queue_entries),
+ (SCI_MDE_ATTRIBUTE_CACHEABLE | SCI_MDE_ATTRIBUTE_PHYSICALLY_CONTIGUOUS)
+ );
+
+ sci_base_mde_construct(
+ &this_controller->memory_descriptors[SCU_MDE_REMOTE_NODE_CONTEXT],
+ SCU_REMOTE_NODE_CONTEXT_ALIGNMENT,
+ this_controller->remote_node_entries * sizeof(union scu_remote_node_context),
+ SCI_MDE_ATTRIBUTE_PHYSICALLY_CONTIGUOUS
+ );
+
+ sci_base_mde_construct(
+ &this_controller->memory_descriptors[SCU_MDE_TASK_CONTEXT],
+ SCU_TASK_CONTEXT_ALIGNMENT,
+ this_controller->task_context_entries * sizeof(struct scu_task_context),
+ SCI_MDE_ATTRIBUTE_PHYSICALLY_CONTIGUOUS
+ );
+
+ /*
+ * The UF buffer address table size must be programmed to a power
+ * of 2. Find the first power of 2 that is equal to or greater then
+ * the number of unsolicited frame buffers to be utilized. */
+ scic_sds_unsolicited_frame_control_set_address_table_count(
+ &this_controller->uf_control
+ );
+
+ sci_base_mde_construct(
+ &this_controller->memory_descriptors[SCU_MDE_UF_BUFFER],
+ SCU_UNSOLICITED_FRAME_BUFFER_ALIGNMENT,
+ scic_sds_unsolicited_frame_control_get_mde_size(this_controller->uf_control),
+ SCI_MDE_ATTRIBUTE_PHYSICALLY_CONTIGUOUS
+ );
+}
+
+/**
+ * This method validates the driver supplied memory descriptor table.
+ * @this_controller:
+ *
+ * enum sci_status
+ */
+enum sci_status scic_sds_controller_validate_memory_descriptor_table(
+ struct scic_sds_controller *this_controller)
+{
+ bool mde_list_valid;
+
+ mde_list_valid = sci_base_mde_is_valid(
+ &this_controller->memory_descriptors[SCU_MDE_COMPLETION_QUEUE],
+ SCU_COMPLETION_RAM_ALIGNMENT,
+ (sizeof(u32) * this_controller->completion_queue_entries),
+ (SCI_MDE_ATTRIBUTE_CACHEABLE | SCI_MDE_ATTRIBUTE_PHYSICALLY_CONTIGUOUS)
+ );
+
+ if (mde_list_valid == false)
+ return SCI_FAILURE_UNSUPPORTED_INFORMATION_FIELD;
+
+ mde_list_valid = sci_base_mde_is_valid(
+ &this_controller->memory_descriptors[SCU_MDE_REMOTE_NODE_CONTEXT],
+ SCU_REMOTE_NODE_CONTEXT_ALIGNMENT,
+ this_controller->remote_node_entries * sizeof(union scu_remote_node_context),
+ SCI_MDE_ATTRIBUTE_PHYSICALLY_CONTIGUOUS
+ );
+
+ if (mde_list_valid == false)
+ return SCI_FAILURE_UNSUPPORTED_INFORMATION_FIELD;
+
+ mde_list_valid = sci_base_mde_is_valid(
+ &this_controller->memory_descriptors[SCU_MDE_TASK_CONTEXT],
+ SCU_TASK_CONTEXT_ALIGNMENT,
+ this_controller->task_context_entries * sizeof(struct scu_task_context),
+ SCI_MDE_ATTRIBUTE_PHYSICALLY_CONTIGUOUS
+ );
+
+ if (mde_list_valid == false)
+ return SCI_FAILURE_UNSUPPORTED_INFORMATION_FIELD;
+
+ mde_list_valid = sci_base_mde_is_valid(
+ &this_controller->memory_descriptors[SCU_MDE_UF_BUFFER],
+ SCU_UNSOLICITED_FRAME_BUFFER_ALIGNMENT,
+ scic_sds_unsolicited_frame_control_get_mde_size(this_controller->uf_control),
+ SCI_MDE_ATTRIBUTE_PHYSICALLY_CONTIGUOUS
+ );
+
+ if (mde_list_valid == false)
+ return SCI_FAILURE_UNSUPPORTED_INFORMATION_FIELD;
+
+ return SCI_SUCCESS;
+}
+
+/**
+ * This method initializes the controller with the physical memory addresses
+ * that are used to communicate with the driver.
+ * @this_controller:
+ *
+ */
+void scic_sds_controller_ram_initialization(
+ struct scic_sds_controller *this_controller)
+{
+ struct sci_physical_memory_descriptor *mde;
+
+ /*
+ * The completion queue is actually placed in cacheable memory
+ * Therefore it no longer comes out of memory in the MDL. */
+ mde = &this_controller->memory_descriptors[SCU_MDE_COMPLETION_QUEUE];
+ this_controller->completion_queue = (u32 *)mde->virtual_address;
+ SMU_CQBAR_WRITE(this_controller, mde->physical_address);
+
+ /*
+ * Program the location of the Remote Node Context table
+ * into the SCU. */
+ mde = &this_controller->memory_descriptors[SCU_MDE_REMOTE_NODE_CONTEXT];
+ this_controller->remote_node_context_table = (union scu_remote_node_context *)
+ mde->virtual_address;
+ SMU_RNCBAR_WRITE(this_controller, mde->physical_address);
+
+ /* Program the location of the Task Context table into the SCU. */
+ mde = &this_controller->memory_descriptors[SCU_MDE_TASK_CONTEXT];
+ this_controller->task_context_table = (struct scu_task_context *)
+ mde->virtual_address;
+ SMU_HTTBAR_WRITE(this_controller, mde->physical_address);
+
+ mde = &this_controller->memory_descriptors[SCU_MDE_UF_BUFFER];
+ scic_sds_unsolicited_frame_control_construct(
+ &this_controller->uf_control, mde, this_controller
+ );
+
+ /*
+ * Inform the silicon as to the location of the UF headers and
+ * address table. */
+ SCU_UFHBAR_WRITE(
+ this_controller,
+ this_controller->uf_control.headers.physical_address);
+ SCU_PUFATHAR_WRITE(
+ this_controller,
+ this_controller->uf_control.address_table.physical_address);
+}
+
+/**
+ * This method initializes the task context data for the controller.
+ * @this_controller:
+ *
+ */
+void scic_sds_controller_assign_task_entries(
+ struct scic_sds_controller *this_controller)
+{
+ u32 task_assignment;
+
+ /*
+ * Assign all the TCs to function 0
+ * TODO: Do we actually need to read this register to write it back? */
+ task_assignment = SMU_TCA_READ(this_controller, 0);
+
+ task_assignment =
+ (
+ task_assignment
+ | (SMU_TCA_GEN_VAL(STARTING, 0))
+ | (SMU_TCA_GEN_VAL(ENDING, this_controller->task_context_entries - 1))
+ | (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE))
+ );
+
+ SMU_TCA_WRITE(this_controller, 0, task_assignment);
+}
+
+/**
+ * This method initializes the hardware completion queue.
+ *
+ *
+ */
+void scic_sds_controller_initialize_completion_queue(
+ struct scic_sds_controller *this_controller)
+{
+ u32 index;
+ u32 completion_queue_control_value;
+ u32 completion_queue_get_value;
+ u32 completion_queue_put_value;
+
+ this_controller->completion_queue_get = 0;
+
+ completion_queue_control_value = (
+ SMU_CQC_QUEUE_LIMIT_SET(this_controller->completion_queue_entries - 1)
+ | SMU_CQC_EVENT_LIMIT_SET(this_controller->completion_event_entries - 1)
+ );
+
+ SMU_CQC_WRITE(this_controller, completion_queue_control_value);
+
+ /* Set the completion queue get pointer and enable the queue */
+ completion_queue_get_value = (
+ (SMU_CQGR_GEN_VAL(POINTER, 0))
+ | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0))
+ | (SMU_CQGR_GEN_BIT(ENABLE))
+ | (SMU_CQGR_GEN_BIT(EVENT_ENABLE))
+ );
+
+ SMU_CQGR_WRITE(this_controller, completion_queue_get_value);
+
+ /* Set the completion queue put pointer */
+ completion_queue_put_value = (
+ (SMU_CQPR_GEN_VAL(POINTER, 0))
+ | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0))
+ );
+
+ SMU_CQPR_WRITE(this_controller, completion_queue_put_value);
+
+ /* Initialize the cycle bit of the completion queue entries */
+ for (index = 0; index < this_controller->completion_queue_entries; index++) {
+ /*
+ * If get.cycle_bit != completion_queue.cycle_bit
+ * its not a valid completion queue entry
+ * so at system start all entries are invalid */
+ this_controller->completion_queue[index] = 0x80000000;
+ }
+}
+
+/**
+ * This method initializes the hardware unsolicited frame queue.
+ *
+ *
+ */
+void scic_sds_controller_initialize_unsolicited_frame_queue(
+ struct scic_sds_controller *this_controller)
+{
+ u32 frame_queue_control_value;
+ u32 frame_queue_get_value;
+ u32 frame_queue_put_value;
+
+ /* Write the queue size */
+ frame_queue_control_value =
+ SCU_UFQC_GEN_VAL(QUEUE_SIZE, this_controller->uf_control.address_table.count);
+
+ SCU_UFQC_WRITE(this_controller, frame_queue_control_value);
+
+ /* Setup the get pointer for the unsolicited frame queue */
+ frame_queue_get_value = (
+ SCU_UFQGP_GEN_VAL(POINTER, 0)
+ | SCU_UFQGP_GEN_BIT(ENABLE_BIT)
+ );
+
+ SCU_UFQGP_WRITE(this_controller, frame_queue_get_value);
+
+ /* Setup the put pointer for the unsolicited frame queue */
+ frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0);
+
+ SCU_UFQPP_WRITE(this_controller, frame_queue_put_value);
+}
+
+/**
+ * This method enables the hardware port task scheduler.
+ *
+ *
+ */
+void scic_sds_controller_enable_port_task_scheduler(
+ struct scic_sds_controller *this_controller)
+{
+ u32 port_task_scheduler_value;
+
+ port_task_scheduler_value = SCU_PTSGCR_READ(this_controller);
+
+ port_task_scheduler_value |=
+ (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) | SCU_PTSGCR_GEN_BIT(PTSG_ENABLE));
+
+ SCU_PTSGCR_WRITE(this_controller, port_task_scheduler_value);
+}
+
+/* --------------------------------------------------------------------------- */
+
+/**
+ *
+ *
+ * This macro is used to delay between writes to the AFE registers during AFE
+ * initialization.
+ */
+#define AFE_REGISTER_WRITE_DELAY 10
+
+static bool is_a0(void)
+{
+ return isci_si_rev == ISCI_SI_REVA0;
+}
+
+static bool is_a2(void)
+{
+ return isci_si_rev == ISCI_SI_REVA2;
+}
+
+static bool is_b0(void)
+{
+ return isci_si_rev > ISCI_SI_REVA2;
+}
+
+/* Initialize the AFE for this phy index. We need to read the AFE setup from
+ * the OEM parameters none
+ */
+void scic_sds_controller_afe_initialization(struct scic_sds_controller *scic)
+{
+ u32 afe_status;
+ u32 phy_id;
+
+ /* Clear DFX Status registers */
+ scu_afe_register_write(scic, afe_dfx_master_control0, 0x0081000f);
+ scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
+
+ /* Configure bias currents to normal */
+ if (is_a0())
+ scu_afe_register_write(scic, afe_bias_control, 0x00005500);
+ else
+ scu_afe_register_write(scic, afe_bias_control, 0x00005A00);
+
+
+ scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
+
+ /* Enable PLL */
+ if (is_b0())
+ scu_afe_register_write(scic, afe_pll_control0, 0x80040A08);
+ else
+ scu_afe_register_write(scic, afe_pll_control0, 0x80040908);
+
+ scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
+
+ /* Wait for the PLL to lock */
+ do {
+ afe_status = scu_afe_register_read(
+ scic, afe_common_block_status);
+ scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
+ } while ((afe_status & 0x00001000) == 0);
+
+ if (is_b0()) {
+ /* Shorten SAS SNW lock time (RxLock timer value from 76 us to 50 us) */
+ scu_afe_register_write(scic, afe_pmsn_master_control0, 0x7bcc96ad);
+ scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
+ }
+
+ for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
+ if (is_b0()) {
+ /* Configure transmitter SSC parameters */
+ scu_afe_txreg_write(scic, phy_id, afe_tx_ssc_control, 0x00030000);
+ scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
+ } else {
+ /*
+ * All defaults, except the Receive Word Alignament/Comma Detect
+ * Enable....(0xe800) */
+ scu_afe_txreg_write(scic, phy_id, afe_xcvr_control0, 0x00004512);
+ scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
+
+ scu_afe_txreg_write(scic, phy_id, afe_xcvr_control1, 0x0050100F);
+ scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
+ }
+
+ /*
+ * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
+ * & increase TX int & ext bias 20%....(0xe85c) */
+ if (is_a0())
+ scu_afe_txreg_write(scic, phy_id, afe_channel_control, 0x000003D4);
+ else if (is_a2())
+ scu_afe_txreg_write(scic, phy_id, afe_channel_control, 0x000003F0);
+ else {
+ /* Power down TX and RX (PWRDNTX and PWRDNRX) */
+ scu_afe_txreg_write(scic, phy_id, afe_channel_control, 0x000003d7);
+ scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
+
+ /*
+ * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
+ * & increase TX int & ext bias 20%....(0xe85c) */
+ scu_afe_txreg_write(scic, phy_id, afe_channel_control, 0x000003d4);
+ }
+ scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
+
+ if (is_a0() || is_a2()) {
+ /* Enable TX equalization (0xe824) */
+ scu_afe_txreg_write(scic, phy_id, afe_tx_control, 0x00040000);
+ scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
+ }
+
+ /*
+ * RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0, TPD=0x0(TX Power On),
+ * RDD=0x0(RX Detect Enabled) ....(0xe800) */
+ scu_afe_txreg_write(scic, phy_id, afe_xcvr_control0, 0x00004100);
+ scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
+
+ /* Leave DFE/FFE on */
+ if (is_a0())
+ scu_afe_txreg_write(scic, phy_id, afe_rx_ssc_control0, 0x3F09983F);
+ else if (is_a2())
+ scu_afe_txreg_write(scic, phy_id, afe_rx_ssc_control0, 0x3F11103F);
+ else {
+ scu_afe_txreg_write(scic, phy_id, afe_rx_ssc_control0, 0x3F11103F);
+ scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
+ /* Enable TX equalization (0xe824) */
+ scu_afe_txreg_write(scic, phy_id, afe_tx_control, 0x00040000);
+ }
+ scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
+
+ scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control0, 0x000E7C03);
+ scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
+
+ scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control1, 0x000E7C03);
+ scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
+
+ scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control2, 0x000E7C03);
+ scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
+
+ scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control3, 0x000E7C03);
+ scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
+ }
+
+ /* Transfer control to the PEs */
+ scu_afe_register_write(scic, afe_dfx_master_control0, 0x00010f00);
+ scic_cb_stall_execution(AFE_REGISTER_WRITE_DELAY);
+}
+
+/*
+ * ****************************************************************************-
+ * * SCIC SDS Controller Internal Start/Stop Routines
+ * ****************************************************************************- */
+
+
+/**
+ * This method will attempt to transition into the ready state for the
+ * controller and indicate that the controller start operation has completed
+ * if all criteria are met.
+ * @this_controller: This parameter indicates the controller object for which
+ * to transition to ready.
+ * @status: This parameter indicates the status value to be pass into the call
+ * to scic_cb_controller_start_complete().
+ *
+ * none.
+ */
+static void scic_sds_controller_transition_to_ready(
+ struct scic_sds_controller *this_controller,
+ enum sci_status status)
+{
+ if (this_controller->parent.state_machine.current_state_id
+ == SCI_BASE_CONTROLLER_STATE_STARTING) {
+ /*
+ * We move into the ready state, because some of the phys/ports
+ * may be up and operational. */
+ sci_base_state_machine_change_state(
+ scic_sds_controller_get_base_state_machine(this_controller),
+ SCI_BASE_CONTROLLER_STATE_READY
+ );
+
+ scic_cb_controller_start_complete(this_controller, status);
+ }
+}
+
+/**
+ * This method is the general timeout handler for the controller. It will take
+ * the correct timetout action based on the current controller state
+ */
+void scic_sds_controller_timeout_handler(
+ struct scic_sds_controller *scic)
+{
+ enum sci_base_controller_states current_state;
+
+ current_state = sci_base_state_machine_get_state(
+ scic_sds_controller_get_base_state_machine(scic));
+
+ if (current_state == SCI_BASE_CONTROLLER_STATE_STARTING) {
+ scic_sds_controller_transition_to_ready(
+ scic, SCI_FAILURE_TIMEOUT);
+ } else if (current_state == SCI_BASE_CONTROLLER_STATE_STOPPING) {
+ sci_base_state_machine_change_state(
+ scic_sds_controller_get_base_state_machine(scic),
+ SCI_BASE_CONTROLLER_STATE_FAILED);
+ scic_cb_controller_stop_complete(scic, SCI_FAILURE_TIMEOUT);
+ } else /* / @todo Now what do we want to do in this case? */
+ dev_err(scic_to_dev(scic),
+ "%s: Controller timer fired when controller was not "
+ "in a state being timed.\n",
+ __func__);
+}
+
+/**
+ * scic_sds_controller_get_port_configuration_mode
+ * @this_controller: This is the controller to use to determine if we are using
+ * manual or automatic port configuration.
+ *
+ * SCIC_PORT_CONFIGURATION_MODE
+ */
+enum SCIC_PORT_CONFIGURATION_MODE scic_sds_controller_get_port_configuration_mode(
+ struct scic_sds_controller *this_controller)
+{
+ u32 index;
+ enum SCIC_PORT_CONFIGURATION_MODE mode;
+
+ mode = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE;
+
+ for (index = 0; index < SCI_MAX_PORTS; index++) {
+ if (this_controller->oem_parameters.sds1.ports[index].phy_mask != 0) {
+ mode = SCIC_PORT_MANUAL_CONFIGURATION_MODE;
+ break;
+ }
+ }
+
+ return mode;
+}
+
+enum sci_status scic_sds_controller_stop_ports(struct scic_sds_controller *scic)
+{
+ u32 index;
+ enum sci_status port_status;
+ enum sci_status status = SCI_SUCCESS;
+
+ for (index = 0; index < scic->logical_port_entries; index++) {
+ port_status = scic_port_stop(&scic->port_table[index]);
+
+ if ((port_status != SCI_SUCCESS) &&
+ (port_status != SCI_FAILURE_INVALID_STATE)) {
+ status = SCI_FAILURE;
+
+ dev_warn(scic_to_dev(scic),
+ "%s: Controller stop operation failed to "
+ "stop port %d because of status %d.\n",
+ __func__,
+ scic->port_table[index].logical_port_index,
+ port_status);
+ }
+ }
+
+ return status;
+}
+
+/**
+ *
+ *
+ *
+ */
+static void scic_sds_controller_phy_timer_start(
+ struct scic_sds_controller *this_controller)
+{
+ scic_cb_timer_start(
+ this_controller,
+ this_controller->phy_startup_timer,
+ SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
+ );
+
+ this_controller->phy_startup_timer_pending = true;
+}
+
+/**
+ *
+ *
+ *
+ */
+void scic_sds_controller_phy_timer_stop(
+ struct scic_sds_controller *this_controller)
+{
+ scic_cb_timer_stop(
+ this_controller,
+ this_controller->phy_startup_timer
+ );
+
+ this_controller->phy_startup_timer_pending = false;
+}
+
+/**
+ * This method is called internally by the controller object to start the next
+ * phy on the controller. If all the phys have been starte, then this
+ * method will attempt to transition the controller to the READY state and
+ * inform the user (scic_cb_controller_start_complete()).
+ * @this_controller: This parameter specifies the controller object for which
+ * to start the next phy.
+ *
+ * enum sci_status
+ */
+enum sci_status scic_sds_controller_start_next_phy(
+ struct scic_sds_controller *this_controller)
+{
+ enum sci_status status;
+
+ status = SCI_SUCCESS;
+
+ if (this_controller->phy_startup_timer_pending == false) {
+ if (this_controller->next_phy_to_start == SCI_MAX_PHYS) {
+ bool is_controller_start_complete = true;
+ struct scic_sds_phy *the_phy;
+ u8 index;
+
+ for (index = 0; index < SCI_MAX_PHYS; index++) {
+ the_phy = &this_controller->phy_table[index];
+
+ if (scic_sds_phy_get_port(the_phy) != SCI_INVALID_HANDLE) {
+ /**
+ * The controller start operation is complete if and only
+ * if:
+ * - all links have been given an opportunity to start
+ * - have no indication of a connected device
+ * - have an indication of a connected device and it has
+ * finished the link training process.
+ */
+ if (
+ (
+ (the_phy->is_in_link_training == false)
+ && (the_phy->parent.state_machine.current_state_id
+ == SCI_BASE_PHY_STATE_INITIAL)
+ )
+ || (
+ (the_phy->is_in_link_training == false)
+ && (the_phy->parent.state_machine.current_state_id
+ == SCI_BASE_PHY_STATE_STOPPED)
+ )
+ || (
+ (the_phy->is_in_link_training == true)
+ && (the_phy->parent.state_machine.current_state_id
+ == SCI_BASE_PHY_STATE_STARTING)
+ )
+ ) {
+ is_controller_start_complete = false;
+ break;
+ }
+ }
+ }
+
+ /*
+ * The controller has successfully finished the start process.
+ * Inform the SCI Core user and transition to the READY state. */
+ if (is_controller_start_complete == true) {
+ scic_sds_controller_transition_to_ready(
+ this_controller, SCI_SUCCESS
+ );
+ scic_sds_controller_phy_timer_stop(this_controller);
+ }
+ } else {
+ struct scic_sds_phy *the_phy;
+
+ the_phy = &this_controller->phy_table[this_controller->next_phy_to_start];
+
+ if (
+ scic_sds_controller_get_port_configuration_mode(this_controller)
+ == SCIC_PORT_MANUAL_CONFIGURATION_MODE
+ ) {
+ if (scic_sds_phy_get_port(the_phy) == SCI_INVALID_HANDLE) {
+ this_controller->next_phy_to_start++;
+
+ /*
+ * Caution recursion ahead be forwarned
+ *
+ * The PHY was never added to a PORT in MPC mode so start the next phy in sequence
+ * This phy will never go link up and will not draw power the OEM parameters either
+ * configured the phy incorrectly for the PORT or it was never assigned to a PORT */
+ return scic_sds_controller_start_next_phy(this_controller);
+ }
+ }
+
+ status = scic_sds_phy_start(the_phy);
+
+ if (status == SCI_SUCCESS) {
+ scic_sds_controller_phy_timer_start(this_controller);
+ } else {
+ dev_warn(scic_to_dev(this_controller),
+ "%s: Controller stop operation failed "
+ "to stop phy %d because of status "
+ "%d.\n",
+ __func__,
+ this_controller->phy_table[this_controller->next_phy_to_start].phy_index,
+ status);
+ }
+
+ this_controller->next_phy_to_start++;
+ }
+ }
+
+ return status;
+}
+
+/**
+ *
+ * @this_controller:
+ *
+ * enum sci_status
+ */
+enum sci_status scic_sds_controller_stop_phys(
+ struct scic_sds_controller *this_controller)
+{
+ u32 index;
+ enum sci_status status;
+ enum sci_status phy_status;
+
+ status = SCI_SUCCESS;
+
+ for (index = 0; index < SCI_MAX_PHYS; index++) {
+ phy_status = scic_sds_phy_stop(&this_controller->phy_table[index]);
+
+ if (
+ (phy_status != SCI_SUCCESS)
+ && (phy_status != SCI_FAILURE_INVALID_STATE)
+ ) {
+ status = SCI_FAILURE;
+
+ dev_warn(scic_to_dev(this_controller),
+ "%s: Controller stop operation failed to stop "
+ "phy %d because of status %d.\n",
+ __func__,
+ this_controller->phy_table[index].phy_index, phy_status);
+ }
+ }
+
+ return status;
+}
+
+/**
+ *
+ * @this_controller:
+ *
+ * enum sci_status
+ */
+enum sci_status scic_sds_controller_stop_devices(
+ struct scic_sds_controller *this_controller)
+{
+ u32 index;
+ enum sci_status status;
+ enum sci_status device_status;
+
+ status = SCI_SUCCESS;
+
+ for (index = 0; index < this_controller->remote_node_entries; index++) {
+ if (this_controller->device_table[index] != SCI_INVALID_HANDLE) {
+ /* / @todo What timeout value do we want to provide to this request? */
+ device_status = scic_remote_device_stop(this_controller->device_table[index], 0);
+
+ if ((device_status != SCI_SUCCESS) &&
+ (device_status != SCI_FAILURE_INVALID_STATE)) {
+ dev_warn(scic_to_dev(this_controller),
+ "%s: Controller stop operation failed "
+ "to stop device 0x%p because of "
+ "status %d.\n",
+ __func__,
+ this_controller->device_table[index], device_status);
+ }
+ }
+ }
+
+ return status;
+}
+
+/*
+ * ****************************************************************************-
+ * * SCIC SDS Controller Power Control (Staggered Spinup)
+ * ****************************************************************************- */
+
+/**
+ *
+ *
+ * This method starts the power control timer for this controller object.
+ */
+static void scic_sds_controller_power_control_timer_start(
+ struct scic_sds_controller *this_controller)
+{
+ scic_cb_timer_start(
+ this_controller, this_controller->power_control.timer,
+ SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL
+ );
+
+ this_controller->power_control.timer_started = true;
+}
+
+/**
+ *
+ *
+ *
+ */
+static void scic_sds_controller_power_control_timer_handler(
+ void *controller)
+{
+ struct scic_sds_controller *this_controller;
+
+ this_controller = (struct scic_sds_controller *)controller;
+
+ if (this_controller->power_control.phys_waiting == 0) {
+ this_controller->power_control.timer_started = false;
+ } else {
+ struct scic_sds_phy *the_phy = NULL;
+ u8 i;
+
+ for (i = 0;
+ (i < SCI_MAX_PHYS)
+ && (this_controller->power_control.phys_waiting != 0);
+ i++) {
+ if (this_controller->power_control.requesters[i] != NULL) {
+ the_phy = this_controller->power_control.requesters[i];
+ this_controller->power_control.requesters[i] = NULL;
+ this_controller->power_control.phys_waiting--;
+ break;
+ }
+ }
+
+ /*
+ * It doesn't matter if the power list is empty, we need to start the
+ * timer in case another phy becomes ready. */
+ scic_sds_controller_power_control_timer_start(this_controller);
+
+ scic_sds_phy_consume_power_handler(the_phy);
+ }
+}
+
+/**
+ * This method inserts the phy in the stagger spinup control queue.
+ * @this_controller:
+ *
+ *
+ */
+void scic_sds_controller_power_control_queue_insert(
+ struct scic_sds_controller *this_controller,
+ struct scic_sds_phy *the_phy)
+{
+ BUG_ON(the_phy == NULL);
+
+ if (
+ (this_controller->power_control.timer_started)
+ && (this_controller->power_control.requesters[the_phy->phy_index] == NULL)
+ ) {
+ this_controller->power_control.requesters[the_phy->phy_index] = the_phy;
+ this_controller->power_control.phys_waiting++;
+ } else {
+ scic_sds_controller_power_control_timer_start(this_controller);
+ scic_sds_phy_consume_power_handler(the_phy);
+ }
+}
+
+/**
+ * This method removes the phy from the stagger spinup control queue.
+ * @this_controller:
+ *
+ *
+ */
+void scic_sds_controller_power_control_queue_remove(
+ struct scic_sds_controller *this_controller,
+ struct scic_sds_phy *the_phy)
+{
+ BUG_ON(the_phy == NULL);
+
+ if (this_controller->power_control.requesters[the_phy->phy_index] != NULL) {
+ this_controller->power_control.phys_waiting--;
+ }
+
+ this_controller->power_control.requesters[the_phy->phy_index] = NULL;
+}
+
+/*
+ * ****************************************************************************-
+ * * SCIC SDS Controller Completion Routines
+ * ****************************************************************************- */
+
+/**
+ * This method returns a true value if the completion queue has entries that
+ * can be processed
+ * @this_controller:
+ *
+ * bool true if the completion queue has entries to process false if the
+ * completion queue has no entries to process
+ */
+static bool scic_sds_controller_completion_queue_has_entries(
+ struct scic_sds_controller *this_controller)
+{
+ u32 get_value = this_controller->completion_queue_get;
+ u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK;
+
+ if (
+ NORMALIZE_GET_POINTER_CYCLE_BIT(get_value)
+ == COMPLETION_QUEUE_CYCLE_BIT(this_controller->completion_queue[get_index])
+ ) {
+ return true;
+ }
+
+ return false;
+}
+
+/* --------------------------------------------------------------------------- */
+
+/**
+ * This method processes a task completion notification. This is called from
+ * within the controller completion handler.
+ * @this_controller:
+ * @completion_entry:
+ *
+ */
+static void scic_sds_controller_task_completion(
+ struct scic_sds_controller *this_controller,
+ u32 completion_entry)
+{
+ u32 index;
+ struct scic_sds_request *io_request;
+
+ index = SCU_GET_COMPLETION_INDEX(completion_entry);
+ io_request = this_controller->io_request_table[index];
+
+ /* Make sure that we really want to process this IO request */
+ if (
+ (io_request != SCI_INVALID_HANDLE)
+ && (io_request->io_tag != SCI_CONTROLLER_INVALID_IO_TAG)
+ && (
+ scic_sds_io_tag_get_sequence(io_request->io_tag)
+ == this_controller->io_request_sequence[index]
+ )
+ ) {
+ /* Yep this is a valid io request pass it along to the io request handler */
+ scic_sds_io_request_tc_completion(io_request, completion_entry);
+ }
+}
+
+/**
+ * This method processes an SDMA completion event. This is called from within
+ * the controller completion handler.
+ * @this_controller:
+ * @completion_entry:
+ *
+ */
+static void scic_sds_controller_sdma_completion(
+ struct scic_sds_controller *this_controller,
+ u32 completion_entry)
+{
+ u32 index;
+ struct scic_sds_request *io_request;
+ struct scic_sds_remote_device *device;
+
+ index = SCU_GET_COMPLETION_INDEX(completion_entry);
+
+ switch (scu_get_command_request_type(completion_entry)) {
+ case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC:
+ case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC:
+ io_request = this_controller->io_request_table[index];
+ dev_warn(scic_to_dev(this_controller),
+ "%s: SCIC SDS Completion type SDMA %x for io request "
+ "%p\n",
+ __func__,
+ completion_entry,
+ io_request);
+ /* @todo For a post TC operation we need to fail the IO
+ * request
+ */
+ break;
+
+ case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC:
+ case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC:
+ case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC:
+ device = this_controller->device_table[index];
+ dev_warn(scic_to_dev(this_controller),
+ "%s: SCIC SDS Completion type SDMA %x for remote "
+ "device %p\n",
+ __func__,
+ completion_entry,
+ device);
+ /* @todo For a port RNC operation we need to fail the
+ * device
+ */
+ break;
+
+ default:
+ dev_warn(scic_to_dev(this_controller),
+ "%s: SCIC SDS Completion unknown SDMA completion "
+ "type %x\n",
+ __func__,
+ completion_entry);
+ break;
+
+ }
+}
+
+/**
+ *
+ * @this_controller:
+ * @completion_entry:
+ *
+ * This method processes an unsolicited frame message. This is called from
+ * within the controller completion handler. none
+ */
+static void scic_sds_controller_unsolicited_frame(
+ struct scic_sds_controller *this_controller,
+ u32 completion_entry)
+{
+ u32 index;
+ u32 frame_index;
+
+ struct scu_unsolicited_frame_header *frame_header;
+ struct scic_sds_phy *phy;
+ struct scic_sds_remote_device *device;
+
+ enum sci_status result = SCI_FAILURE;
+
+ frame_index = SCU_GET_FRAME_INDEX(completion_entry);
+
+ frame_header
+ = this_controller->uf_control.buffers.array[frame_index].header;
+ this_controller->uf_control.buffers.array[frame_index].state
+ = UNSOLICITED_FRAME_IN_USE;
+
+ if (SCU_GET_FRAME_ERROR(completion_entry)) {
+ /*
+ * / @todo If the IAF frame or SIGNATURE FIS frame has an error will
+ * / this cause a problem? We expect the phy initialization will
+ * / fail if there is an error in the frame. */
+ scic_sds_controller_release_frame(this_controller, frame_index);
+ return;
+ }
+
+ if (frame_header->is_address_frame) {
+ index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry);
+ phy = &this_controller->phy_table[index];
+ if (phy != NULL) {
+ result = scic_sds_phy_frame_handler(phy, frame_index);
+ }
+ } else {
+
+ index = SCU_GET_COMPLETION_INDEX(completion_entry);
+
+ if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
+ /*
+ * This is a signature fis or a frame from a direct attached SATA
+ * device that has not yet been created. In either case forwared
+ * the frame to the PE and let it take care of the frame data. */
+ index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry);
+ phy = &this_controller->phy_table[index];
+ result = scic_sds_phy_frame_handler(phy, frame_index);
+ } else {
+ if (index < this_controller->remote_node_entries)
+ device = this_controller->device_table[index];
+ else
+ device = NULL;
+
+ if (device != NULL)
+ result = scic_sds_remote_device_frame_handler(device, frame_index);
+ else
+ scic_sds_controller_release_frame(this_controller, frame_index);
+ }
+ }
+
+ if (result != SCI_SUCCESS) {
+ /*
+ * / @todo Is there any reason to report some additional error message
+ * / when we get this failure notifiction? */
+ }
+}
+
+/**
+ * This method processes an event completion entry. This is called from within
+ * the controller completion handler.
+ * @this_controller:
+ * @completion_entry:
+ *
+ */
+static void scic_sds_controller_event_completion(
+ struct scic_sds_controller *this_controller,
+ u32 completion_entry)
+{
+ u32 index;
+ struct scic_sds_request *io_request;
+ struct scic_sds_remote_device *device;
+ struct scic_sds_phy *phy;
+
+ index = SCU_GET_COMPLETION_INDEX(completion_entry);
+
+ switch (scu_get_event_type(completion_entry)) {
+ case SCU_EVENT_TYPE_SMU_COMMAND_ERROR:
+ /* / @todo The driver did something wrong and we need to fix the condtion. */
+ dev_err(scic_to_dev(this_controller),
+ "%s: SCIC Controller 0x%p received SMU command error "
+ "0x%x\n",
+ __func__,
+ this_controller,
+ completion_entry);
+ break;
+
+ case SCU_EVENT_TYPE_SMU_PCQ_ERROR:
+ case SCU_EVENT_TYPE_SMU_ERROR:
+ case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR:
+ /*
+ * / @todo This is a hardware failure and its likely that we want to
+ * / reset the controller. */
+ dev_err(scic_to_dev(this_controller),
+ "%s: SCIC Controller 0x%p received fatal controller "
+ "event 0x%x\n",
+ __func__,
+ this_controller,
+ completion_entry);
+ break;
+
+ case SCU_EVENT_TYPE_TRANSPORT_ERROR:
+ io_request = this_controller->io_request_table[index];
+ scic_sds_io_request_event_handler(io_request, completion_entry);
+ break;
+
+ case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT:
+ switch (scu_get_event_specifier(completion_entry)) {
+ case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE:
+ case SCU_EVENT_SPECIFIC_TASK_TIMEOUT:
+ io_request = this_controller->io_request_table[index];
+ if (io_request != SCI_INVALID_HANDLE)
+ scic_sds_io_request_event_handler(io_request, completion_entry);
+ else
+ dev_warn(scic_to_dev(this_controller),
+ "%s: SCIC Controller 0x%p received "
+ "event 0x%x for io request object "
+ "that doesnt exist.\n",
+ __func__,
+ this_controller,
+ completion_entry);
+
+ break;
+
+ case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT:
+ device = this_controller->device_table[index];
+ if (device != SCI_INVALID_HANDLE)
+ scic_sds_remote_device_event_handler(device, completion_entry);
+ else
+ dev_warn(scic_to_dev(this_controller),
+ "%s: SCIC Controller 0x%p received "
+ "event 0x%x for remote device object "
+ "that doesnt exist.\n",
+ __func__,
+ this_controller,
+ completion_entry);
+
+ break;
+ }
+ break;
+
+ case SCU_EVENT_TYPE_BROADCAST_CHANGE:
+ /*
+ * direct the broadcast change event to the phy first and then let
+ * the phy redirect the broadcast change to the port object */
+ case SCU_EVENT_TYPE_ERR_CNT_EVENT:
+ /*
+ * direct error counter event to the phy object since that is where
+ * we get the event notification. This is a type 4 event. */
+ case SCU_EVENT_TYPE_OSSP_EVENT:
+ index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry);
+ phy = &this_controller->phy_table[index];
+ scic_sds_phy_event_handler(phy, completion_entry);
+ break;
+
+ case SCU_EVENT_TYPE_RNC_SUSPEND_TX:
+ case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX:
+ case SCU_EVENT_TYPE_RNC_OPS_MISC:
+ if (index < this_controller->remote_node_entries) {
+ device = this_controller->device_table[index];
+
+ if (device != NULL)
+ scic_sds_remote_device_event_handler(device, completion_entry);
+ } else
+ dev_err(scic_to_dev(this_controller),
+ "%s: SCIC Controller 0x%p received event 0x%x "
+ "for remote device object 0x%0x that doesnt "
+ "exist.\n",
+ __func__,
+ this_controller,
+ completion_entry,
+ index);
+
+ break;
+
+ default:
+ dev_warn(scic_to_dev(this_controller),
+ "%s: SCIC Controller received unknown event code %x\n",
+ __func__,
+ completion_entry);
+ break;
+ }
+}
+
+/**
+ * This method is a private routine for processing the completion queue entries.
+ * @this_controller:
+ *
+ */
+static void scic_sds_controller_process_completions(
+ struct scic_sds_controller *this_controller)
+{
+ u32 completion_count = 0;
+ u32 completion_entry;
+ u32 get_index;
+ u32 get_cycle;
+ u32 event_index;
+ u32 event_cycle;
+
+ dev_dbg(scic_to_dev(this_controller),
+ "%s: completion queue begining get:0x%08x\n",
+ __func__,
+ this_controller->completion_queue_get);
+
+ /* Get the component parts of the completion queue */
+ get_index = NORMALIZE_GET_POINTER(this_controller->completion_queue_get);
+ get_cycle = SMU_CQGR_CYCLE_BIT & this_controller->completion_queue_get;
+
+ event_index = NORMALIZE_EVENT_POINTER(this_controller->completion_queue_get);
+ event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & this_controller->completion_queue_get;
+
+ while (
+ NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle)
+ == COMPLETION_QUEUE_CYCLE_BIT(this_controller->completion_queue[get_index])
+ ) {
+ completion_count++;
+
+ completion_entry = this_controller->completion_queue[get_index];
+ INCREMENT_COMPLETION_QUEUE_GET(this_controller, get_index, get_cycle);
+
+ dev_dbg(scic_to_dev(this_controller),
+ "%s: completion queue entry:0x%08x\n",
+ __func__,
+ completion_entry);
+
+ switch (SCU_GET_COMPLETION_TYPE(completion_entry)) {
+ case SCU_COMPLETION_TYPE_TASK:
+ scic_sds_controller_task_completion(this_controller, completion_entry);
+ break;
+
+ case SCU_COMPLETION_TYPE_SDMA:
+ scic_sds_controller_sdma_completion(this_controller, completion_entry);
+ break;
+
+ case SCU_COMPLETION_TYPE_UFI:
+ scic_sds_controller_unsolicited_frame(this_controller, completion_entry);
+ break;
+
+ case SCU_COMPLETION_TYPE_EVENT:
+ INCREMENT_EVENT_QUEUE_GET(this_controller, event_index, event_cycle);
+ scic_sds_controller_event_completion(this_controller, completion_entry);
+ break;
+
+ case SCU_COMPLETION_TYPE_NOTIFY:
+ /*
+ * Presently we do the same thing with a notify event that we do with the
+ * other event codes. */
+ INCREMENT_EVENT_QUEUE_GET(this_controller, event_index, event_cycle);
+ scic_sds_controller_event_completion(this_controller, completion_entry);
+ break;
+
+ default:
+ dev_warn(scic_to_dev(this_controller),
+ "%s: SCIC Controller received unknown "
+ "completion type %x\n",
+ __func__,
+ completion_entry);
+ break;
+ }
+ }
+
+ /* Update the get register if we completed one or more entries */
+ if (completion_count > 0) {
+ this_controller->completion_queue_get =
+ SMU_CQGR_GEN_BIT(ENABLE)
+ | SMU_CQGR_GEN_BIT(EVENT_ENABLE)
+ | event_cycle | SMU_CQGR_GEN_VAL(EVENT_POINTER, event_index)
+ | get_cycle | SMU_CQGR_GEN_VAL(POINTER, get_index);
+
+ SMU_CQGR_WRITE(this_controller,
+ this_controller->completion_queue_get);
+ }
+
+ dev_dbg(scic_to_dev(this_controller),
+ "%s: completion queue ending get:0x%08x\n",
+ __func__,
+ this_controller->completion_queue_get);
+
+}
+
+/**
+ * This method is a private routine for processing the completion queue entries.
+ * @this_controller:
+ *
+ */
+static void scic_sds_controller_transitioned_process_completions(
+ struct scic_sds_controller *this_controller)
+{
+ u32 completion_count = 0;
+ u32 completion_entry;
+ u32 get_index;
+ u32 get_cycle;
+ u32 event_index;
+ u32 event_cycle;
+
+ dev_dbg(scic_to_dev(this_controller),
+ "%s: completion queue begining get:0x%08x\n",
+ __func__,
+ this_controller->completion_queue_get);
+
+ /* Get the component parts of the completion queue */
+ get_index = NORMALIZE_GET_POINTER(this_controller->completion_queue_get);
+ get_cycle = SMU_CQGR_CYCLE_BIT & this_controller->completion_queue_get;
+
+ event_index = NORMALIZE_EVENT_POINTER(this_controller->completion_queue_get);
+ event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & this_controller->completion_queue_get;
+
+ while (
+ NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle)
+ == COMPLETION_QUEUE_CYCLE_BIT(
+ this_controller->completion_queue[get_index])
+ ) {
+ completion_count++;
+
+ completion_entry = this_controller->completion_queue[get_index];
+ INCREMENT_COMPLETION_QUEUE_GET(this_controller, get_index, get_cycle);
+
+ dev_dbg(scic_to_dev(this_controller),
+ "%s: completion queue entry:0x%08x\n",
+ __func__,
+ completion_entry);
+
+ switch (SCU_GET_COMPLETION_TYPE(completion_entry)) {
+ case SCU_COMPLETION_TYPE_TASK:
+ scic_sds_controller_task_completion(this_controller, completion_entry);
+ break;
+
+ case SCU_COMPLETION_TYPE_NOTIFY:
+ case SCU_COMPLETION_TYPE_EVENT:
+ /*
+ * Presently we do the same thing with a notify event that we
+ * do with the other event codes. */
+ INCREMENT_EVENT_QUEUE_GET(this_controller, event_index, event_cycle);
+ /* Fall-through */
+
+ case SCU_COMPLETION_TYPE_SDMA:
+ case SCU_COMPLETION_TYPE_UFI:
+ default:
+ dev_warn(scic_to_dev(this_controller),
+ "%s: SCIC Controller ignoring completion type "
+ "%x\n",
+ __func__,
+ completion_entry);
+ break;
+ }
+ }
+
+ /* Update the get register if we completed one or more entries */
+ if (completion_count > 0) {
+ this_controller->completion_queue_get =
+ SMU_CQGR_GEN_BIT(ENABLE)
+ | SMU_CQGR_GEN_BIT(EVENT_ENABLE)
+ | event_cycle | SMU_CQGR_GEN_VAL(EVENT_POINTER, event_index)
+ | get_cycle | SMU_CQGR_GEN_VAL(POINTER, get_index);
+
+ SMU_CQGR_WRITE(this_controller, this_controller->completion_queue_get);
+ }
+
+ dev_dbg(scic_to_dev(this_controller),
+ "%s: completion queue ending get:0x%08x\n",
+ __func__,
+ this_controller->completion_queue_get);
+}
+
+/*
+ * ****************************************************************************-
+ * * SCIC SDS Controller Interrupt and Completion functions
+ * ****************************************************************************- */
+
+/**
+ * This method provides standard (common) processing of interrupts for polling
+ * and legacy based interrupts.
+ * @controller:
+ * @interrupt_status:
+ *
+ * This method returns a boolean (bool) indication as to whether an completions
+ * are pending to be processed. true if an interrupt is to be processed false
+ * if no interrupt was pending
+ */
+static bool scic_sds_controller_standard_interrupt_handler(
+ struct scic_sds_controller *this_controller,
+ u32 interrupt_status)
+{
+ bool is_completion_needed = false;
+
+ if ((interrupt_status & SMU_ISR_QUEUE_ERROR) ||
+ ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) &&
+ (!scic_sds_controller_completion_queue_has_entries(
+ this_controller)))) {
+ /*
+ * We have a fatal error on the read of the completion queue bar
+ * OR
+ * We have a fatal error there is nothing in the completion queue
+ * but we have a report from the hardware that the queue is full
+ * / @todo how do we request the a controller reset */
+ is_completion_needed = true;
+ this_controller->encountered_fatal_error = true;
+ }
+
+ if (scic_sds_controller_completion_queue_has_entries(this_controller)) {
+ is_completion_needed = true;
+ }
+
+ return is_completion_needed;
+}
+
+/**
+ * This is the method provided to handle polling for interrupts for the
+ * controller object.
+ *
+ * bool true if an interrupt is to be processed false if no interrupt was
+ * pending
+ */
+static bool scic_sds_controller_polling_interrupt_handler(
+ struct scic_sds_controller *scic)
+{
+ u32 interrupt_status;
+
+ /*
+ * In INTERRUPT_POLLING_MODE we exit the interrupt handler if the
+ * hardware indicates nothing is pending. Since we are not being
+ * called from a real interrupt, we don't want to confuse the hardware
+ * by servicing the completion queue before the hardware indicates it
+ * is ready. We'll simply wait for another polling interval and check
+ * again.
+ */
+ interrupt_status = SMU_ISR_READ(scic);
+ if ((interrupt_status &
+ (SMU_ISR_COMPLETION |
+ SMU_ISR_QUEUE_ERROR |
+ SMU_ISR_QUEUE_SUSPEND)) == 0) {
+ return false;
+ }
+
+ return scic_sds_controller_standard_interrupt_handler(
+ scic, interrupt_status);
+}
+
+/**
+ * This is the method provided to handle completions when interrupt polling is
+ * in use.
+ */
+static void scic_sds_controller_polling_completion_handler(
+ struct scic_sds_controller *scic)
+{
+ if (scic->encountered_fatal_error == true) {
+ dev_err(scic_to_dev(scic),
+ "%s: SCIC Controller has encountered a fatal error.\n",
+ __func__);
+
+ sci_base_state_machine_change_state(
+ scic_sds_controller_get_base_state_machine(scic),
+ SCI_BASE_CONTROLLER_STATE_FAILED);
+ } else if (scic_sds_controller_completion_queue_has_entries(scic)) {
+ if (scic->restrict_completions == false)
+ scic_sds_controller_process_completions(scic);
+ else
+ scic_sds_controller_transitioned_process_completions(
+ scic);
+ }
+
+ /*
+ * The interrupt handler does not adjust the CQ's
+ * get pointer. So, SCU's INTx pin stays asserted during the
+ * interrupt handler even though it tries to clear the interrupt
+ * source. Therefore, the completion handler must ensure that the
+ * interrupt source is cleared. Otherwise, we get a spurious
+ * interrupt for which the interrupt handler will not issue a
+ * corresponding completion event. Also, we unmask interrupts.
+ */
+ SMU_ISR_WRITE(
+ scic,
+ (u32)(SMU_ISR_COMPLETION | SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)
+ );
+}
+
+/**
+ * This is the method provided to handle legacy interrupts for the controller
+ * object.
+ *
+ * bool true if an interrupt is processed false if no interrupt was processed
+ */
+static bool scic_sds_controller_legacy_interrupt_handler(
+ struct scic_sds_controller *scic)
+{
+ u32 interrupt_status;
+ bool is_completion_needed;
+
+ interrupt_status = SMU_ISR_READ(scic);
+ is_completion_needed = scic_sds_controller_standard_interrupt_handler(
+ scic, interrupt_status);
+
+ return is_completion_needed;
+}
+
+
+/**
+ * This is the method provided to handle legacy completions it is expected that
+ * the SCI User will call this completion handler anytime the interrupt
+ * handler reports that it has handled an interrupt.
+ */
+static void scic_sds_controller_legacy_completion_handler(
+ struct scic_sds_controller *scic)
+{
+ scic_sds_controller_polling_completion_handler(scic);
+ SMU_IMR_WRITE(scic, 0x00000000);
+}
+
+/**
+ * This is the method provided to handle an MSIX interrupt message when there
+ * is just a single MSIX message being provided by the hardware. This mode
+ * of operation is single vector mode.
+ *
+ * bool true if an interrupt is processed false if no interrupt was processed
+ */
+static bool scic_sds_controller_single_vector_interrupt_handler(
+ struct scic_sds_controller *scic)
+{
+ u32 interrupt_status;
+
+ /*
+ * Mask the interrupts
+ * There is a race in the hardware that could cause us not to be notified
+ * of an interrupt completion if we do not take this step. We will unmask
+ * the interrupts in the completion routine. */
+ SMU_IMR_WRITE(scic, 0xFFFFFFFF);
+
+ interrupt_status = SMU_ISR_READ(scic);
+ interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND);
+
+ if ((interrupt_status == 0) &&
+ scic_sds_controller_completion_queue_has_entries(scic)) {
+ /*
+ * There is at least one completion queue entry to process so we can
+ * return a success and ignore for now the case of an error interrupt */
+ SMU_ISR_WRITE(scic, SMU_ISR_COMPLETION);
+ return true;
+ }
+
+ if (interrupt_status != 0) {
+ /*
+ * There is an error interrupt pending so let it through and handle
+ * in the callback */
+ return true;
+ }
+
+ /*
+ * Clear any offending interrupts since we could not find any to handle
+ * and unmask them all */
+ SMU_ISR_WRITE(scic, 0x00000000);
+ SMU_IMR_WRITE(scic, 0x00000000);
+
+ return false;
+}
+
+/**
+ * This is the method provided to handle completions for a single MSIX message.
+ */
+static void scic_sds_controller_single_vector_completion_handler(
+ struct scic_sds_controller *scic)
+{
+ u32 interrupt_status;
+
+ interrupt_status = SMU_ISR_READ(scic);
+ interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND);
+
+ if (interrupt_status & SMU_ISR_QUEUE_ERROR) {
+ dev_err(scic_to_dev(scic),
+ "%s: SCIC Controller has encountered a fatal error.\n",
+ __func__);
+
+ /*
+ * We have a fatal condition and must reset the controller
+ * Leave the interrupt mask in place and get the controller reset */
+ sci_base_state_machine_change_state(
+ scic_sds_controller_get_base_state_machine(scic),
+ SCI_BASE_CONTROLLER_STATE_FAILED);
+ return;
+ }
+
+ if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) &&
+ !scic_sds_controller_completion_queue_has_entries(scic)) {
+ dev_err(scic_to_dev(scic),
+ "%s: SCIC Controller has encountered a fatal error.\n",
+ __func__);
+
+ /*
+ * We have a fatal condtion and must reset the controller
+ * Leave the interrupt mask in place and get the controller reset */
+ sci_base_state_machine_change_state(
+ scic_sds_controller_get_base_state_machine(scic),
+ SCI_BASE_CONTROLLER_STATE_FAILED);
+ return;
+ }
+
+ if (scic_sds_controller_completion_queue_has_entries(scic)) {
+ scic_sds_controller_process_completions(scic);
+
+ /*
+ * We dont care which interrupt got us to processing the completion queu
+ * so clear them both. */
+ SMU_ISR_WRITE(
+ scic,
+ (SMU_ISR_COMPLETION | SMU_ISR_QUEUE_SUSPEND));
+ }
+
+ SMU_IMR_WRITE(scic, 0x00000000);
+}
+
+/**
+ * This is the method provided to handle a MSIX message for a normal completion.
+ *
+ * bool true if an interrupt is processed false if no interrupt was processed
+ */
+static bool scic_sds_controller_normal_vector_interrupt_handler(
+ struct scic_sds_controller *scic)
+{
+ if (scic_sds_controller_completion_queue_has_entries(scic)) {
+ return true;
+ } else {
+ /*
+ * we have a spurious interrupt it could be that we have already
+ * emptied the completion queue from a previous interrupt */
+ SMU_ISR_WRITE(scic, SMU_ISR_COMPLETION);
+
+ /*
+ * There is a race in the hardware that could cause us not to be notified
+ * of an interrupt completion if we do not take this step. We will mask
+ * then unmask the interrupts so if there is another interrupt pending
+ * the clearing of the interrupt source we get the next interrupt message. */
+ SMU_IMR_WRITE(scic, 0xFF000000);
+ SMU_IMR_WRITE(scic, 0x00000000);
+ }
+
+ return false;
+}
+
+/**
+ * This is the method provided to handle the completions for a normal MSIX
+ * message.
+ */
+static void scic_sds_controller_normal_vector_completion_handler(
+ struct scic_sds_controller *scic)
+{
+ /* Empty out the completion queue */
+ if (scic_sds_controller_completion_queue_has_entries(scic))
+ scic_sds_controller_process_completions(scic);
+
+ /* Clear the interrupt and enable all interrupts again */
+ SMU_ISR_WRITE(scic, SMU_ISR_COMPLETION);
+ /* Could we write the value of SMU_ISR_COMPLETION? */
+ SMU_IMR_WRITE(scic, 0xFF000000);
+ SMU_IMR_WRITE(scic, 0x00000000);
+}
+
+/**
+ * This is the method provided to handle the error MSIX message interrupt.
+ * This is the normal operating mode for the hardware if MSIX is enabled.
+ *
+ * bool true if an interrupt is processed false if no interrupt was processed
+ */
+static bool scic_sds_controller_error_vector_interrupt_handler(
+ struct scic_sds_controller *scic)
+{
+ u32 interrupt_status;
+
+ interrupt_status = SMU_ISR_READ(scic);
+ interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND);
+
+ if (interrupt_status != 0) {
+ /*
+ * There is an error interrupt pending so let it through and handle
+ * in the callback */
+ return true;
+ }
+
+ /*
+ * There is a race in the hardware that could cause us not to be notified
+ * of an interrupt completion if we do not take this step. We will mask
+ * then unmask the error interrupts so if there was another interrupt
+ * pending we will be notified.
+ * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */
+ SMU_IMR_WRITE(scic, 0x000000FF);
+ SMU_IMR_WRITE(scic, 0x00000000);
+
+ return false;
+}
+
+/**
+ * This is the method provided to handle the error completions when the
+ * hardware is using two MSIX messages.
+ */
+static void scic_sds_controller_error_vector_completion_handler(
+ struct scic_sds_controller *scic)
+{
+ u32 interrupt_status;
+
+ interrupt_status = SMU_ISR_READ(scic);
+
+ if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) &&
+ scic_sds_controller_completion_queue_has_entries(scic)) {
+
+ scic_sds_controller_process_completions(scic);
+ SMU_ISR_WRITE(scic, SMU_ISR_QUEUE_SUSPEND);
+
+ } else {
+ dev_err(scic_to_dev(scic),
+ "%s: SCIC Controller reports CRC error on completion "
+ "ISR %x\n",
+ __func__,
+ interrupt_status);
+
+ sci_base_state_machine_change_state(
+ scic_sds_controller_get_base_state_machine(scic),
+ SCI_BASE_CONTROLLER_STATE_FAILED);
+
+ return;
+ }
+
+ /*
+ * If we dont process any completions I am not sure that we want to do this.
+ * We are in the middle of a hardware fault and should probably be reset. */
+ SMU_IMR_WRITE(scic, 0x00000000);
+}
+
+
+/*
+ * ****************************************************************************-
+ * * SCIC SDS Controller External Methods
+ * ****************************************************************************- */
+
+/**
+ * This method returns the sizeof the SCIC SDS Controller Object
+ */
+u32 scic_sds_controller_get_object_size(void)
+{
+ return sizeof(struct scic_sds_controller);
+}
+
+
+void scic_sds_controller_link_up(
+ struct scic_sds_controller *scic,
+ struct scic_sds_port *sci_port,
+ struct scic_sds_phy *sci_phy)
+{
+ scic_sds_controller_phy_handler_t link_up;
+ u32 state;
+
+ state = scic->parent.state_machine.current_state_id;
+ link_up = scic_sds_controller_state_handler_table[state].link_up;
+
+ if (link_up)
+ link_up(scic, sci_port, sci_phy);
+ else
+ dev_warn(scic_to_dev(scic),
+ "%s: SCIC Controller linkup event from phy %d in "
+ "unexpected state %d\n",
+ __func__,
+ sci_phy->phy_index,
+ sci_base_state_machine_get_state(
+ scic_sds_controller_get_base_state_machine(
+ scic)));
+}
+
+
+void scic_sds_controller_link_down(
+ struct scic_sds_controller *scic,
+ struct scic_sds_port *sci_port,
+ struct scic_sds_phy *sci_phy)
+{
+ u32 state;
+ scic_sds_controller_phy_handler_t link_down;
+
+ state = scic->parent.state_machine.current_state_id;
+ link_down = scic_sds_controller_state_handler_table[state].link_down;
+
+ if (link_down)
+ link_down(scic, sci_port, sci_phy);
+ else
+ dev_warn(scic_to_dev(scic),
+ "%s: SCIC Controller linkdown event from phy %d in "
+ "unexpected state %d\n",
+ __func__,
+ sci_phy->phy_index,
+ sci_base_state_machine_get_state(
+ scic_sds_controller_get_base_state_machine(
+ scic)));
+}
+
+/**
+ * This method will write to the SCU PCP register the request value. The method
+ * is used to suspend/resume ports, devices, and phys.
+ * @this_controller:
+ *
+ *
+ */
+void scic_sds_controller_post_request(
+ struct scic_sds_controller *this_controller,
+ u32 request)
+{
+ dev_dbg(scic_to_dev(this_controller),
+ "%s: SCIC Controller 0x%p post request 0x%08x\n",
+ __func__,
+ this_controller,
+ request);
+
+ SMU_PCP_WRITE(this_controller, request);
+}
+
+/**
+ * This method will copy the soft copy of the task context into the physical
+ * memory accessible by the controller.
+ * @this_controller: This parameter specifies the controller for which to copy
+ * the task context.
+ * @this_request: This parameter specifies the request for which the task
+ * context is being copied.
+ *
+ * After this call is made the SCIC_SDS_IO_REQUEST object will always point to
+ * the physical memory version of the task context. Thus, all subsequent
+ * updates to the task context are performed in the TC table (i.e. DMAable
+ * memory). none
+ */
+void scic_sds_controller_copy_task_context(
+ struct scic_sds_controller *this_controller,
+ struct scic_sds_request *this_request)
+{
+ struct scu_task_context *task_context_buffer;
+
+ task_context_buffer = scic_sds_controller_get_task_context_buffer(
+ this_controller, this_request->io_tag
+ );
+
+ memcpy(
+ task_context_buffer,
+ this_request->task_context_buffer,
+ SCI_FIELD_OFFSET(struct scu_task_context, sgl_snapshot_ac)
+ );
+
+ /*
+ * Now that the soft copy of the TC has been copied into the TC
+ * table accessible by the silicon. Thus, any further changes to
+ * the TC (e.g. TC termination) occur in the appropriate location. */
+ this_request->task_context_buffer = task_context_buffer;
+}
+
+/**
+ * This method returns the task context buffer for the given io tag.
+ * @this_controller:
+ * @io_tag:
+ *
+ * struct scu_task_context*
+ */
+struct scu_task_context *scic_sds_controller_get_task_context_buffer(
+ struct scic_sds_controller *this_controller,
+ u16 io_tag
+ ) {
+ u16 task_index = scic_sds_io_tag_get_index(io_tag);
+
+ if (task_index < this_controller->task_context_entries) {
+ return &this_controller->task_context_table[task_index];
+ }
+
+ return NULL;
+}
+
+/**
+ * This method returnst the sequence value from the io tag value
+ * @this_controller:
+ * @io_tag:
+ *
+ * u16
+ */
+
+/**
+ * This method returns the IO request associated with the tag value
+ * @this_controller:
+ * @io_tag:
+ *
+ * SCIC_SDS_IO_REQUEST_T* NULL if there is no valid IO request at the tag value
+ */
+struct scic_sds_request *scic_sds_controller_get_io_request_from_tag(
+ struct scic_sds_controller *this_controller,
+ u16 io_tag
+ ) {
+ u16 task_index;
+ u16 task_sequence;
+
+ task_index = scic_sds_io_tag_get_index(io_tag);
+
+ if (task_index < this_controller->task_context_entries) {
+ if (this_controller->io_request_table[task_index] != SCI_INVALID_HANDLE) {
+ task_sequence = scic_sds_io_tag_get_sequence(io_tag);
+
+ if (task_sequence == this_controller->io_request_sequence[task_index]) {
+ return this_controller->io_request_table[task_index];
+ }
+ }
+ }
+
+ return SCI_INVALID_HANDLE;
+}
+
+/**
+ * This method allocates remote node index and the reserves the remote node
+ * context space for use. This method can fail if there are no more remote
+ * node index available.
+ * @this_controller: This is the controller object which contains the set of
+ * free remote node ids
+ * @the_devce: This is the device object which is requesting the a remote node
+ * id
+ * @node_id: This is the remote node id that is assinged to the device if one
+ * is available
+ *
+ * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote
+ * node index available.
+ */
+enum sci_status scic_sds_controller_allocate_remote_node_context(
+ struct scic_sds_controller *this_controller,
+ struct scic_sds_remote_device *the_device,
+ u16 *node_id)
+{
+ u16 node_index;
+ u32 remote_node_count = scic_sds_remote_device_node_count(the_device);
+
+ node_index = scic_sds_remote_node_table_allocate_remote_node(
+ &this_controller->available_remote_nodes, remote_node_count
+ );
+
+ if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
+ this_controller->device_table[node_index] = the_device;
+
+ *node_id = node_index;
+
+ return SCI_SUCCESS;
+ }
+
+ return SCI_FAILURE_INSUFFICIENT_RESOURCES;
+}
+
+/**
+ * This method frees the remote node index back to the available pool. Once
+ * this is done the remote node context buffer is no longer valid and can
+ * not be used.
+ * @this_controller:
+ * @the_device:
+ * @node_id:
+ *
+ */
+void scic_sds_controller_free_remote_node_context(
+ struct scic_sds_controller *this_controller,
+ struct scic_sds_remote_device *the_device,
+ u16 node_id)
+{
+ u32 remote_node_count = scic_sds_remote_device_node_count(the_device);
+
+ if (this_controller->device_table[node_id] == the_device) {
+ this_controller->device_table[node_id] = SCI_INVALID_HANDLE;
+
+ scic_sds_remote_node_table_release_remote_node_index(
+ &this_controller->available_remote_nodes, remote_node_count, node_id
+ );
+ }
+}
+
+/**
+ * This method returns the union scu_remote_node_context for the specified remote
+ * node id.
+ * @this_controller:
+ * @node_id:
+ *
+ * union scu_remote_node_context*
+ */
+union scu_remote_node_context *scic_sds_controller_get_remote_node_context_buffer(
+ struct scic_sds_controller *this_controller,
+ u16 node_id
+ ) {
+ if (
+ (node_id < this_controller->remote_node_entries)
+ && (this_controller->device_table[node_id] != SCI_INVALID_HANDLE)
+ ) {
+ return &this_controller->remote_node_context_table[node_id];
+ }
+
+ return NULL;
+}
+
+/**
+ *
+ * @resposne_buffer: This is the buffer into which the D2H register FIS will be
+ * constructed.
+ * @frame_header: This is the frame header returned by the hardware.
+ * @frame_buffer: This is the frame buffer returned by the hardware.
+ *
+ * This method will combind the frame header and frame buffer to create a SATA
+ * D2H register FIS none
+ */
+void scic_sds_controller_copy_sata_response(
+ void *response_buffer,
+ void *frame_header,
+ void *frame_buffer)
+{
+ memcpy(
+ response_buffer,
+ frame_header,
+ sizeof(u32)
+ );
+
+ memcpy(
+ (char *)((char *)response_buffer + sizeof(u32)),
+ frame_buffer,
+ sizeof(struct sata_fis_reg_d2h) - sizeof(u32)
+ );
+}
+
+/**
+ * This method releases the frame once this is done the frame is available for
+ * re-use by the hardware. The data contained in the frame header and frame
+ * buffer is no longer valid. The UF queue get pointer is only updated if UF
+ * control indicates this is appropriate.
+ * @this_controller:
+ * @frame_index:
+ *
+ */
+void scic_sds_controller_release_frame(
+ struct scic_sds_controller *this_controller,
+ u32 frame_index)
+{
+ if (scic_sds_unsolicited_frame_control_release_frame(
+ &this_controller->uf_control, frame_index) == true)
+ SCU_UFQGP_WRITE(this_controller, this_controller->uf_control.get);
+}
+
+/**
+ * This method sets user parameters and OEM parameters to default values.
+ * Users can override these values utilizing the scic_user_parameters_set()
+ * and scic_oem_parameters_set() methods.
+ * @controller: This parameter specifies the controller for which to set the
+ * configuration parameters to their default values.
+ *
+ */
+static void scic_sds_controller_set_default_config_parameters(
+ struct scic_sds_controller *this_controller)
+{
+ u16 index;
+
+ /* Default to no SSC operation. */
+ this_controller->oem_parameters.sds1.controller.do_enable_ssc = false;
+
+ /* Initialize all of the port parameter information to narrow ports. */
+ for (index = 0; index < SCI_MAX_PORTS; index++) {
+ this_controller->oem_parameters.sds1.ports[index].phy_mask = 0;
+ }
+
+ /* Initialize all of the phy parameter information. */
+ for (index = 0; index < SCI_MAX_PHYS; index++) {
+ /*
+ * Default to 3G (i.e. Gen 2) for now. User can override if
+ * they choose. */
+ this_controller->user_parameters.sds1.phys[index].max_speed_generation = 2;
+
+ /*
+ * Previous Vitesse based expanders had a arbitration issue that
+ * is worked around by having the upper 32-bits of SAS address
+ * with a value greater then the Vitesse company identifier.
+ * Hence, usage of 0x5FCFFFFF. */
+ this_controller->oem_parameters.sds1.phys[index].sas_address.low
+ = 0x00000001;
+ this_controller->oem_parameters.sds1.phys[index].sas_address.high
+ = 0x5FCFFFFF;
+ }
+
+ this_controller->user_parameters.sds1.stp_inactivity_timeout = 5;
+ this_controller->user_parameters.sds1.ssp_inactivity_timeout = 5;
+ this_controller->user_parameters.sds1.stp_max_occupancy_timeout = 5;
+ this_controller->user_parameters.sds1.ssp_max_occupancy_timeout = 20;
+ this_controller->user_parameters.sds1.no_outbound_task_timeout = 5;
+
+}
+
+
+enum sci_status scic_controller_construct(struct scic_sds_controller *controller,
+ void __iomem *scu_base,
+ void __iomem *smu_base)
+{
+ u8 index;
+
+ sci_base_controller_construct(
+ &controller->parent,
+ scic_sds_controller_state_table,
+ controller->memory_descriptors,
+ ARRAY_SIZE(controller->memory_descriptors),
+ NULL
+ );
+
+ controller->scu_registers = scu_base;
+ controller->smu_registers = smu_base;
+
+ scic_sds_port_configuration_agent_construct(&controller->port_agent);
+
+ /* Construct the ports for this controller */
+ for (index = 0; index < SCI_MAX_PORTS; index++)
+ scic_sds_port_construct(&controller->port_table[index],
+ index, controller);
+ scic_sds_port_construct(&controller->port_table[index],
+ SCIC_SDS_DUMMY_PORT, controller);
+
+ /* Construct the phys for this controller */
+ for (index = 0; index < SCI_MAX_PHYS; index++) {
+ /* Add all the PHYs to the dummy port */
+ scic_sds_phy_construct(
+ &controller->phy_table[index],
+ &controller->port_table[SCI_MAX_PORTS],
+ index
+ );
+ }
+
+ controller->invalid_phy_mask = 0;
+
+ /* Set the default maximum values */
+ controller->completion_event_entries = SCU_EVENT_COUNT;
+ controller->completion_queue_entries = SCU_COMPLETION_QUEUE_COUNT;
+ controller->remote_node_entries = SCI_MAX_REMOTE_DEVICES;
+ controller->logical_port_entries = SCI_MAX_PORTS;
+ controller->task_context_entries = SCU_IO_REQUEST_COUNT;
+ controller->uf_control.buffers.count = SCU_UNSOLICITED_FRAME_COUNT;
+ controller->uf_control.address_table.count = SCU_UNSOLICITED_FRAME_COUNT;
+
+ /* Initialize the User and OEM parameters to default values. */
+ scic_sds_controller_set_default_config_parameters(controller);
+
+ return SCI_SUCCESS;
+}
+
+/* --------------------------------------------------------------------------- */
+
+enum sci_status scic_controller_initialize(
+ struct scic_sds_controller *scic)
+{
+ enum sci_status status = SCI_FAILURE_INVALID_STATE;
+ sci_base_controller_handler_t initialize;
+ u32 state;
+
+ state = scic->parent.state_machine.current_state_id;
+ initialize = scic_sds_controller_state_handler_table[state].base.initialize;
+
+ if (initialize)
+ status = initialize(&scic->parent);
+ else
+ dev_warn(scic_to_dev(scic),
+ "%s: SCIC Controller initialize operation requested "
+ "in invalid state %d\n",
+ __func__,
+ sci_base_state_machine_get_state(
+ scic_sds_controller_get_base_state_machine(
+ scic)));
+
+ return status;
+}
+
+/* --------------------------------------------------------------------------- */
+
+u32 scic_controller_get_suggested_start_timeout(
+ struct scic_sds_controller *sc)
+{
+ /* Validate the user supplied parameters. */
+ if (sc == SCI_INVALID_HANDLE)
+ return 0;
+
+ /*
+ * The suggested minimum timeout value for a controller start operation:
+ *
+ * Signature FIS Timeout
+ * + Phy Start Timeout
+ * + Number of Phy Spin Up Intervals
+ * ---------------------------------
+ * Number of milliseconds for the controller start operation.
+ *
+ * NOTE: The number of phy spin up intervals will be equivalent
+ * to the number of phys divided by the number phys allowed
+ * per interval - 1 (once OEM parameters are supported).
+ * Currently we assume only 1 phy per interval. */
+
+ return (SCIC_SDS_SIGNATURE_FIS_TIMEOUT
+ + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
+ + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL));
+}
+
+/* --------------------------------------------------------------------------- */
+
+enum sci_status scic_controller_start(
+ struct scic_sds_controller *scic,
+ u32 timeout)
+{
+ enum sci_status status = SCI_FAILURE_INVALID_STATE;
+ sci_base_controller_timed_handler_t start;
+ u32 state;
+
+ state = scic->parent.state_machine.current_state_id;
+ start = scic_sds_controller_state_handler_table[state].base.start;
+
+ if (start)
+ status = start(&scic->parent, timeout);
+ else
+ dev_warn(scic_to_dev(scic),
+ "%s: SCIC Controller start operation requested in "
+ "invalid state %d\n",
+ __func__,
+ sci_base_state_machine_get_state(
+ scic_sds_controller_get_base_state_machine(
+ scic)));
+
+ return status;
+}
+
+/* --------------------------------------------------------------------------- */
+
+enum sci_status scic_controller_stop(
+ struct scic_sds_controller *scic,
+ u32 timeout)
+{
+ enum sci_status status = SCI_FAILURE_INVALID_STATE;
+ sci_base_controller_timed_handler_t stop;
+ u32 state;
+
+ state = scic->parent.state_machine.current_state_id;
+ stop = scic_sds_controller_state_handler_table[state].base.stop;
+
+ if (stop)
+ status = stop(&scic->parent, timeout);
+ else
+ dev_warn(scic_to_dev(scic),
+ "%s: SCIC Controller stop operation requested in "
+ "invalid state %d\n",
+ __func__,
+ sci_base_state_machine_get_state(
+ scic_sds_controller_get_base_state_machine(
+ scic)));
+
+ return status;
+}
+
+/* --------------------------------------------------------------------------- */
+
+enum sci_status scic_controller_reset(
+ struct scic_sds_controller *scic)
+{
+ enum sci_status status = SCI_FAILURE_INVALID_STATE;
+ sci_base_controller_handler_t reset;
+ u32 state;
+
+ state = scic->parent.state_machine.current_state_id;
+ reset = scic_sds_controller_state_handler_table[state].base.reset;
+
+ if (reset)
+ status = reset(&scic->parent);
+ else
+ dev_warn(scic_to_dev(scic),
+ "%s: SCIC Controller reset operation requested in "
+ "invalid state %d\n",
+ __func__,
+ sci_base_state_machine_get_state(
+ scic_sds_controller_get_base_state_machine(
+ scic)));
+
+ return status;
+}
+
+/* --------------------------------------------------------------------------- */
+
+enum sci_status scic_controller_get_handler_methods(
+ enum scic_interrupt_type interrupt_type,
+ u16 message_count,
+ struct scic_controller_handler_methods *handler_methods)
+{
+ enum sci_status status = SCI_FAILURE_UNSUPPORTED_MESSAGE_COUNT;
+
+ switch (interrupt_type) {
+ case SCIC_LEGACY_LINE_INTERRUPT_TYPE:
+ if (message_count == 0) {
+ handler_methods[0].interrupt_handler
+ = scic_sds_controller_legacy_interrupt_handler;
+ handler_methods[0].completion_handler
+ = scic_sds_controller_legacy_completion_handler;
+
+ status = SCI_SUCCESS;
+ }
+ break;
+
+ case SCIC_MSIX_INTERRUPT_TYPE:
+ if (message_count == 1) {
+ handler_methods[0].interrupt_handler
+ = scic_sds_controller_single_vector_interrupt_handler;
+ handler_methods[0].completion_handler
+ = scic_sds_controller_single_vector_completion_handler;
+
+ status = SCI_SUCCESS;
+ } else if (message_count == 2) {
+ handler_methods[0].interrupt_handler
+ = scic_sds_controller_normal_vector_interrupt_handler;
+ handler_methods[0].completion_handler
+ = scic_sds_controller_normal_vector_completion_handler;
+
+ handler_methods[1].interrupt_handler
+ = scic_sds_controller_error_vector_interrupt_handler;
+ handler_methods[1].completion_handler
+ = scic_sds_controller_error_vector_completion_handler;
+
+ status = SCI_SUCCESS;
+ }
+ break;
+
+ case SCIC_NO_INTERRUPTS:
+ if (message_count == 0) {
+
+ handler_methods[0].interrupt_handler
+ = scic_sds_controller_polling_interrupt_handler;
+ handler_methods[0].completion_handler
+ = scic_sds_controller_polling_completion_handler;
+
+ status = SCI_SUCCESS;
+ }
+ break;
+
+ default:
+ status = SCI_FAILURE_INVALID_PARAMETER_VALUE;
+ break;
+ }
+
+ return status;
+}
+
+/* --------------------------------------------------------------------------- */
+
+enum sci_io_status scic_controller_start_io(
+ struct scic_sds_controller *scic,
+ struct scic_sds_remote_device *remote_device,
+ struct scic_sds_request *io_request,
+ u16 io_tag)
+{
+ u32 state;
+ sci_base_controller_start_request_handler_t start_io;
+
+ state = scic->parent.state_machine.current_state_id;
+ start_io = scic_sds_controller_state_handler_table[state].base.start_io;
+
+ return start_io(&scic->parent,
+ (struct sci_base_remote_device *) remote_device,
+ (struct sci_base_request *)io_request, io_tag);
+}
+
+/* --------------------------------------------------------------------------- */
+
+enum sci_status scic_controller_terminate_request(
+ struct scic_sds_controller *scic,
+ struct scic_sds_remote_device *remote_device,
+ struct scic_sds_request *request)
+{
+ sci_base_controller_request_handler_t terminate_request;
+ u32 state;
+
+ state = scic->parent.state_machine.current_state_id;
+ terminate_request = scic_sds_controller_state_handler_table[state].terminate_request;
+
+ return terminate_request(&scic->parent,
+ (struct sci_base_remote_device *)remote_device,
+ (struct sci_base_request *)request);
+}
+
+/* --------------------------------------------------------------------------- */
+
+enum sci_status scic_controller_complete_io(
+ struct scic_sds_controller *scic,
+ struct scic_sds_remote_device *remote_device,
+ struct scic_sds_request *io_request)
+{
+ u32 state;
+ sci_base_controller_request_handler_t complete_io;
+
+ state = scic->parent.state_machine.current_state_id;
+ complete_io = scic_sds_controller_state_handler_table[state].base.complete_io;
+
+ return complete_io(&scic->parent,
+ (struct sci_base_remote_device *)remote_device,
+ (struct sci_base_request *)io_request);
+}
+
+/* --------------------------------------------------------------------------- */
+
+
+enum sci_task_status scic_controller_start_task(
+ struct scic_sds_controller *scic,
+ struct scic_sds_remote_device *remote_device,
+ struct scic_sds_request *task_request,
+ u16 task_tag)
+{
+ u32 state;
+ sci_base_controller_start_request_handler_t start_task;
+ enum sci_task_status status = SCI_TASK_FAILURE_INVALID_STATE;
+
+ state = scic->parent.state_machine.current_state_id;
+ start_task = scic_sds_controller_state_handler_table[state].base.start_task;
+
+ if (start_task)
+ status = start_task(&scic->parent,
+ (struct sci_base_remote_device *)remote_device,
+ (struct sci_base_request *)task_request,
+ task_tag);
+ else
+ dev_warn(scic_to_dev(scic),
+ "%s: SCIC Controller starting task from invalid "
+ "state\n",
+ __func__);
+
+ return status;
+}
+
+/* --------------------------------------------------------------------------- */
+
+enum sci_status scic_controller_complete_task(
+ struct scic_sds_controller *scic,
+ struct scic_sds_remote_device *remote_device,
+ struct scic_sds_request *task_request)
+{
+ u32 state;
+ sci_base_controller_request_handler_t complete_task;
+ enum sci_status status = SCI_FAILURE_INVALID_STATE;
+
+ state = scic->parent.state_machine.current_state_id;
+ complete_task = scic_sds_controller_state_handler_table[state].base.complete_task;
+
+ if (complete_task)
+ status = complete_task(&scic->parent,
+ (struct sci_base_remote_device *)remote_device,
+ (struct sci_base_request *)task_request);
+ else
+ dev_warn(scic_to_dev(scic),
+ "%s: SCIC Controller completing task from invalid "
+ "state\n",
+ __func__);
+
+ return status;
+}
+
+
+/* --------------------------------------------------------------------------- */
+
+enum sci_status scic_controller_get_port_handle(
+ struct scic_sds_controller *scic,
+ u8 port_index,
+ struct scic_sds_port **port_handle)
+{
+ if (port_index < scic->logical_port_entries) {
+ *port_handle = &scic->port_table[port_index];
+
+ return SCI_SUCCESS;
+ }
+
+ return SCI_FAILURE_INVALID_PORT;
+}
+
+/* --------------------------------------------------------------------------- */
+
+enum sci_status scic_controller_get_phy_handle(
+ struct scic_sds_controller *scic,
+ u8 phy_index,
+ struct scic_sds_phy **phy_handle)
+{
+ if (phy_index < ARRAY_SIZE(scic->phy_table)) {
+ *phy_handle = &scic->phy_table[phy_index];
+
+ return SCI_SUCCESS;
+ }
+
+ dev_err(scic_to_dev(scic),
+ "%s: Controller:0x%p PhyId:0x%x invalid phy index\n",
+ __func__, scic, phy_index);
+
+ return SCI_FAILURE_INVALID_PHY;
+}
+
+/* --------------------------------------------------------------------------- */
+
+u16 scic_controller_allocate_io_tag(
+ struct scic_sds_controller *scic)
+{
+ u16 task_context;
+ u16 sequence_count;
+
+ if (!sci_pool_empty(scic->tci_pool)) {
+ sci_pool_get(scic->tci_pool, task_context);
+
+ sequence_count = scic->io_request_sequence[task_context];
+
+ return scic_sds_io_tag_construct(sequence_count, task_context);
+ }
+
+ return SCI_CONTROLLER_INVALID_IO_TAG;
+}
+
+/* --------------------------------------------------------------------------- */
+
+enum sci_status scic_controller_free_io_tag(
+ struct scic_sds_controller *scic,
+ u16 io_tag)
+{
+ u16 sequence;
+ u16 index;
+
+ BUG_ON(io_tag == SCI_CONTROLLER_INVALID_IO_TAG);
+
+ sequence = scic_sds_io_tag_get_sequence(io_tag);
+ index = scic_sds_io_tag_get_index(io_tag);
+
+ if (!sci_pool_full(scic->tci_pool)) {
+ if (sequence == scic->io_request_sequence[index]) {
+ scic_sds_io_sequence_increment(
+ scic->io_request_sequence[index]);
+
+ sci_pool_put(scic->tci_pool, index);
+
+ return SCI_SUCCESS;
+ }
+ }
+
+ return SCI_FAILURE_INVALID_IO_TAG;
+}
+
+/* --------------------------------------------------------------------------- */
+
+void scic_controller_enable_interrupts(
+ struct scic_sds_controller *scic)
+{
+ BUG_ON(scic->smu_registers == NULL);
+ SMU_IMR_WRITE(scic, 0x00000000);
+}
+
+/* --------------------------------------------------------------------------- */
+
+void scic_controller_disable_interrupts(
+ struct scic_sds_controller *scic)
+{
+ BUG_ON(scic->smu_registers == NULL);
+ SMU_IMR_WRITE(scic, 0xffffffff);
+}
+
+/* --------------------------------------------------------------------------- */
+
+enum sci_status scic_controller_set_mode(
+ struct scic_sds_controller *scic,
+ enum sci_controller_mode operating_mode)
+{
+ enum sci_status status = SCI_SUCCESS;
+
+ if ((scic->parent.state_machine.current_state_id ==
+ SCI_BASE_CONTROLLER_STATE_INITIALIZING) ||
+ (scic->parent.state_machine.current_state_id ==
+ SCI_BASE_CONTROLLER_STATE_INITIALIZED)) {
+ switch (operating_mode) {
+ case SCI_MODE_SPEED:
+ scic->remote_node_entries = SCI_MAX_REMOTE_DEVICES;
+ scic->task_context_entries = SCU_IO_REQUEST_COUNT;
+ scic->uf_control.buffers.count =
+ SCU_UNSOLICITED_FRAME_COUNT;
+ scic->completion_event_entries = SCU_EVENT_COUNT;
+ scic->completion_queue_entries =
+ SCU_COMPLETION_QUEUE_COUNT;
+ scic_sds_controller_build_memory_descriptor_table(scic);
+ break;
+
+ case SCI_MODE_SIZE:
+ scic->remote_node_entries = SCI_MIN_REMOTE_DEVICES;
+ scic->task_context_entries = SCI_MIN_IO_REQUESTS;
+ scic->uf_control.buffers.count =
+ SCU_MIN_UNSOLICITED_FRAMES;
+ scic->completion_event_entries = SCU_MIN_EVENTS;
+ scic->completion_queue_entries =
+ SCU_MIN_COMPLETION_QUEUE_ENTRIES;
+ scic_sds_controller_build_memory_descriptor_table(scic);
+ break;
+
+ default:
+ status = SCI_FAILURE_INVALID_PARAMETER_VALUE;
+ break;
+ }
+ } else
+ status = SCI_FAILURE_INVALID_STATE;
+
+ return status;
+}
+
+/**
+ * scic_sds_controller_reset_hardware() -
+ *
+ * This method will reset the controller hardware.
+ */
+void scic_sds_controller_reset_hardware(
+ struct scic_sds_controller *scic)
+{
+ /* Disable interrupts so we dont take any spurious interrupts */
+ scic_controller_disable_interrupts(scic);
+
+ /* Reset the SCU */
+ SMU_SMUSRCR_WRITE(scic, 0xFFFFFFFF);
+
+ /* Delay for 1ms to before clearing the CQP and UFQPR. */
+ scic_cb_stall_execution(1000);
+
+ /* The write to the CQGR clears the CQP */
+ SMU_CQGR_WRITE(scic, 0x00000000);
+
+ /* The write to the UFQGP clears the UFQPR */
+ SCU_UFQGP_WRITE(scic, 0x00000000);
+}
+
+/* --------------------------------------------------------------------------- */
+
+enum sci_status scic_user_parameters_set(
+ struct scic_sds_controller *scic,
+ union scic_user_parameters *scic_parms)
+{
+ if (
+ (scic->parent.state_machine.current_state_id
+ == SCI_BASE_CONTROLLER_STATE_RESET)
+ || (scic->parent.state_machine.current_state_id
+ == SCI_BASE_CONTROLLER_STATE_INITIALIZING)
+ || (scic->parent.state_machine.current_state_id
+ == SCI_BASE_CONTROLLER_STATE_INITIALIZED)
+ ) {
+ u16 index;
+
+ /*
+ * Validate the user parameters. If they are not legal, then
+ * return a failure. */
+ for (index = 0; index < SCI_MAX_PHYS; index++) {
+ if (!
+ (scic_parms->sds1.phys[index].max_speed_generation
+ <= SCIC_SDS_PARM_MAX_SPEED
+ && scic_parms->sds1.phys[index].max_speed_generation
+ > SCIC_SDS_PARM_NO_SPEED
+ )
+ )
+ return SCI_FAILURE_INVALID_PARAMETER_VALUE;
+ }
+
+ memcpy(&scic->user_parameters, scic_parms, sizeof(*scic_parms));
+
+ return SCI_SUCCESS;
+ }
+
+ return SCI_FAILURE_INVALID_STATE;
+}
+
+/* --------------------------------------------------------------------------- */
+
+void scic_user_parameters_get(
+ struct scic_sds_controller *scic,
+ union scic_user_parameters *scic_parms)
+{
+ memcpy(scic_parms, (&scic->user_parameters), sizeof(*scic_parms));
+}
+
+/* --------------------------------------------------------------------------- */
+
+enum sci_status scic_oem_parameters_set(
+ struct scic_sds_controller *scic,
+ union scic_oem_parameters *scic_parms)
+{
+ if (
+ (scic->parent.state_machine.current_state_id
+ == SCI_BASE_CONTROLLER_STATE_RESET)
+ || (scic->parent.state_machine.current_state_id
+ == SCI_BASE_CONTROLLER_STATE_INITIALIZING)
+ || (scic->parent.state_machine.current_state_id
+ == SCI_BASE_CONTROLLER_STATE_INITIALIZED)
+ ) {
+ u16 index;
+
+ /*
+ * Validate the oem parameters. If they are not legal, then
+ * return a failure. */
+ for (index = 0; index < SCI_MAX_PORTS; index++) {
+ if (scic_parms->sds1.ports[index].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX) {
+ return SCI_FAILURE_INVALID_PARAMETER_VALUE;
+ }
+ }
+
+ for (index = 0; index < SCI_MAX_PHYS; index++) {
+ if (
+ scic_parms->sds1.phys[index].sas_address.high == 0
+ && scic_parms->sds1.phys[index].sas_address.low == 0
+ ) {
+ return SCI_FAILURE_INVALID_PARAMETER_VALUE;
+ }
+ }
+
+ memcpy(&scic->oem_parameters, scic_parms, sizeof(*scic_parms));
+ return SCI_SUCCESS;
+ }
+
+ return SCI_FAILURE_INVALID_STATE;
+}
+
+/* --------------------------------------------------------------------------- */
+
+void scic_oem_parameters_get(
+ struct scic_sds_controller *scic,
+ union scic_oem_parameters *scic_parms)
+{
+ memcpy(scic_parms, (&scic->oem_parameters), sizeof(*scic_parms));
+}
+
+/* --------------------------------------------------------------------------- */
+
+
+#define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853
+#define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280
+#define INTERRUPT_COALESCE_TIMEOUT_MAX_US 2700000
+#define INTERRUPT_COALESCE_NUMBER_MAX 256
+#define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN 7
+#define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX 28
+
+enum sci_status scic_controller_set_interrupt_coalescence(
+ struct scic_sds_controller *scic_controller,
+ u32 coalesce_number,
+ u32 coalesce_timeout)
+{
+ u8 timeout_encode = 0;
+ u32 min = 0;
+ u32 max = 0;
+
+ /* Check if the input parameters fall in the range. */
+ if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX)
+ return SCI_FAILURE_INVALID_PARAMETER_VALUE;
+
+ /*
+ * Defined encoding for interrupt coalescing timeout:
+ * Value Min Max Units
+ * ----- --- --- -----
+ * 0 - - Disabled
+ * 1 13.3 20.0 ns
+ * 2 26.7 40.0
+ * 3 53.3 80.0
+ * 4 106.7 160.0
+ * 5 213.3 320.0
+ * 6 426.7 640.0
+ * 7 853.3 1280.0
+ * 8 1.7 2.6 us
+ * 9 3.4 5.1
+ * 10 6.8 10.2
+ * 11 13.7 20.5
+ * 12 27.3 41.0
+ * 13 54.6 81.9
+ * 14 109.2 163.8
+ * 15 218.5 327.7
+ * 16 436.9 655.4
+ * 17 873.8 1310.7
+ * 18 1.7 2.6 ms
+ * 19 3.5 5.2
+ * 20 7.0 10.5
+ * 21 14.0 21.0
+ * 22 28.0 41.9
+ * 23 55.9 83.9
+ * 24 111.8 167.8
+ * 25 223.7 335.5
+ * 26 447.4 671.1
+ * 27 894.8 1342.2
+ * 28 1.8 2.7 s
+ * Others Undefined */
+
+ /*
+ * Use the table above to decide the encode of interrupt coalescing timeout
+ * value for register writing. */
+ if (coalesce_timeout == 0)
+ timeout_encode = 0;
+ else{
+ /* make the timeout value in unit of (10 ns). */
+ coalesce_timeout = coalesce_timeout * 100;
+ min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10;
+ max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10;
+
+ /* get the encode of timeout for register writing. */
+ for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN;
+ timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX;
+ timeout_encode++) {
+ if (min <= coalesce_timeout && max > coalesce_timeout)
+ break;
+ else if (coalesce_timeout >= max && coalesce_timeout < min * 2
+ && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) {
+ if ((coalesce_timeout - max) < (2 * min - coalesce_timeout))
+ break;
+ else{
+ timeout_encode++;
+ break;
+ }
+ } else {
+ max = max * 2;
+ min = min * 2;
+ }
+ }
+
+ if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1)
+ /* the value is out of range. */
+ return SCI_FAILURE_INVALID_PARAMETER_VALUE;
+ }
+
+ SMU_ICC_WRITE(
+ scic_controller,
+ (SMU_ICC_GEN_VAL(NUMBER, coalesce_number) |
+ SMU_ICC_GEN_VAL(TIMER, timeout_encode))
+ );
+
+ scic_controller->interrupt_coalesce_number = (u16)coalesce_number;
+ scic_controller->interrupt_coalesce_timeout = coalesce_timeout / 100;
+
+ return SCI_SUCCESS;
+}
+
+
+struct scic_sds_controller *scic_controller_alloc(struct device *dev)
+{
+ return devm_kzalloc(dev, sizeof(struct scic_sds_controller), GFP_KERNEL);
+}
+
+/*
+ * *****************************************************************************
+ * * DEFAULT STATE HANDLERS
+ * ***************************************************************************** */
+
+/**
+ *
+ * @controller: This is struct sci_base_controller object which is cast into a
+ * struct scic_sds_controller object.
+ * @remote_device: This is struct sci_base_remote_device which, if it was used, would
+ * be cast to a struct scic_sds_remote_device.
+ * @io_request: This is the struct sci_base_request which, if it was used, would be
+ * cast to a SCIC_SDS_IO_REQUEST.
+ * @io_tag: This is the IO tag to be assigned to the IO request or
+ * SCI_CONTROLLER_INVALID_IO_TAG.
+ *
+ * This method is called when the struct scic_sds_controller default start io/task
+ * handler is in place. - Issue a warning message enum sci_status
+ * SCI_FAILURE_INVALID_STATE
+ */
+static enum sci_status scic_sds_controller_default_start_operation_handler(
+ struct sci_base_controller *controller,
+ struct sci_base_remote_device *remote_device,
+ struct sci_base_request *io_request,
+ u16 io_tag)
+{
+ struct scic_sds_controller *this_controller;
+
+ this_controller = (struct scic_sds_controller *)controller;
+
+ dev_warn(scic_to_dev(this_controller),
+ "%s: SCIC Controller requested to start an io/task from "
+ "invalid state %d\n",
+ __func__,
+ sci_base_state_machine_get_state(
+ scic_sds_controller_get_base_state_machine(
+ this_controller)));
+
+ return SCI_FAILURE_INVALID_STATE;
+}
+
+/**
+ *
+ * @controller: This is struct sci_base_controller object which is cast into a
+ * struct scic_sds_controller object.
+ * @remote_device: This is struct sci_base_remote_device which, if it was used, would
+ * be cast to a struct scic_sds_remote_device.
+ * @io_request: This is the struct sci_base_request which, if it was used, would be
+ * cast to a SCIC_SDS_IO_REQUEST.
+ *
+ * This method is called when the struct scic_sds_controller default request handler
+ * is in place. - Issue a warning message enum sci_status SCI_FAILURE_INVALID_STATE
+ */
+static enum sci_status scic_sds_controller_default_request_handler(
+ struct sci_base_controller *controller,
+ struct sci_base_remote_device *remote_device,
+ struct sci_base_request *io_request)
+{
+ struct scic_sds_controller *this_controller;
+
+ this_controller = (struct scic_sds_controller *)controller;
+
+ dev_warn(scic_to_dev(this_controller),
+ "%s: SCIC Controller request operation from invalid state %d\n",
+ __func__,
+ sci_base_state_machine_get_state(
+ scic_sds_controller_get_base_state_machine(
+ this_controller)));
+
+ return SCI_FAILURE_INVALID_STATE;
+}
+
+/*
+ * *****************************************************************************
+ * * GENERAL (COMMON) STATE HANDLERS
+ * ***************************************************************************** */
+
+/**
+ *
+ * @controller: The struct sci_base_controller object which is cast into a
+ * struct scic_sds_controller object.
+ *
+ * This method is called when the struct scic_sds_controller is in the ready state
+ * reset handler is in place. - Transition to
+ * SCI_BASE_CONTROLLER_STATE_RESETTING enum sci_status SCI_SUCCESS
+ */
+static enum sci_status scic_sds_controller_general_reset_handler(
+ struct sci_base_controller *controller)
+{
+ struct scic_sds_controller *this_controller;
+
+ this_controller = (struct scic_sds_controller *)controller;
+
+ /*
+ * The reset operation is not a graceful cleanup just perform the state
+ * transition. */
+ sci_base_state_machine_change_state(
+ scic_sds_controller_get_base_state_machine(this_controller),
+ SCI_BASE_CONTROLLER_STATE_RESETTING
+ );
+
+ return SCI_SUCCESS;
+}
+
+/*
+ * *****************************************************************************
+ * * RESET STATE HANDLERS
+ * ***************************************************************************** */
+
+/**
+ *
+ * @controller: This is the struct sci_base_controller object which is cast into a
+ * struct scic_sds_controller object.
+ *
+ * This method is the struct scic_sds_controller initialize handler for the reset
+ * state. - Currently this function does nothing enum sci_status SCI_FAILURE This
+ * function is not yet implemented and is a valid request from the reset state.
+ */
+static enum sci_status scic_sds_controller_reset_state_initialize_handler(
+ struct sci_base_controller *controller)
+{
+ u32 index;
+ enum sci_status result = SCI_SUCCESS;
+ struct scic_sds_controller *this_controller;
+
+ this_controller = (struct scic_sds_controller *)controller;
+
+ sci_base_state_machine_change_state(
+ scic_sds_controller_get_base_state_machine(this_controller),
+ SCI_BASE_CONTROLLER_STATE_INITIALIZING
+ );
+
+ this_controller->timeout_timer = scic_cb_timer_create(
+ this_controller,
+ (void (*)(void *))scic_sds_controller_timeout_handler,
+ (void (*)(void *))controller);
+
+ scic_sds_controller_initialize_phy_startup(this_controller);
+
+ scic_sds_controller_initialize_power_control(this_controller);
+
+ /*
+ * There is nothing to do here for B0 since we do not have to
+ * program the AFE registers.
+ * / @todo The AFE settings are supposed to be correct for the B0 but
+ * / presently they seem to be wrong. */
+ scic_sds_controller_afe_initialization(this_controller);
+
+ if (SCI_SUCCESS == result) {
+ u32 status;
+ u32 terminate_loop;
+
+ /* Take the hardware out of reset */
+ SMU_SMUSRCR_WRITE(this_controller, 0x00000000);
+
+ /*
+ * / @todo Provide meaningfull error code for hardware failure
+ * result = SCI_FAILURE_CONTROLLER_HARDWARE; */
+ result = SCI_FAILURE;
+ terminate_loop = 100;
+
+ while (terminate_loop-- && (result != SCI_SUCCESS)) {
+ /* Loop until the hardware reports success */
+ scic_cb_stall_execution(SCU_CONTEXT_RAM_INIT_STALL_TIME);
+ status = SMU_SMUCSR_READ(this_controller);
+
+ if ((status & SCU_RAM_INIT_COMPLETED) == SCU_RAM_INIT_COMPLETED) {
+ result = SCI_SUCCESS;
+ }
+ }
+ }
+
+ if (result == SCI_SUCCESS) {
+ u32 max_supported_ports;
+ u32 max_supported_devices;
+ u32 max_supported_io_requests;
+ u32 device_context_capacity;
+
+ /*
+ * Determine what are the actaul device capacities that the
+ * hardware will support */
+ device_context_capacity = SMU_DCC_READ(this_controller);
+
+ max_supported_ports =
+ smu_dcc_get_max_ports(device_context_capacity);
+ max_supported_devices =
+ smu_dcc_get_max_remote_node_context(device_context_capacity);
+ max_supported_io_requests =
+ smu_dcc_get_max_task_context(device_context_capacity);
+
+ /* Make all PEs that are unassigned match up with the logical ports */
+ for (index = 0; index < max_supported_ports; index++) {
+ scu_register_write(
+ this_controller,
+ this_controller->scu_registers->peg0.ptsg.protocol_engine[index],
+ index
+ );
+ }
+
+ /* Record the smaller of the two capacity values */
+ this_controller->logical_port_entries =
+ min(max_supported_ports, this_controller->logical_port_entries);
+
+ this_controller->task_context_entries =
+ min(max_supported_io_requests, this_controller->task_context_entries);
+
+ this_controller->remote_node_entries =
+ min(max_supported_devices, this_controller->remote_node_entries);
+
+ /*
+ * Now that we have the correct hardware reported minimum values
+ * build the MDL for the controller. Default to a performance
+ * configuration. */
+ scic_controller_set_mode(this_controller, SCI_MODE_SPEED);
+ }
+
+ /* Initialize hardware PCI Relaxed ordering in DMA engines */
+ if (result == SCI_SUCCESS) {
+ u32 dma_configuration;
+
+ /* Configure the payload DMA */
+ dma_configuration = SCU_PDMACR_READ(this_controller);
+ dma_configuration |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
+ SCU_PDMACR_WRITE(this_controller, dma_configuration);
+
+ /* Configure the control DMA */
+ dma_configuration = SCU_CDMACR_READ(this_controller);
+ dma_configuration |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
+ SCU_CDMACR_WRITE(this_controller, dma_configuration);
+ }
+
+ /*
+ * Initialize the PHYs before the PORTs because the PHY registers
+ * are accessed during the port initialization. */
+ if (result == SCI_SUCCESS) {
+ /* Initialize the phys */
+ for (index = 0;
+ (result == SCI_SUCCESS) && (index < SCI_MAX_PHYS);
+ index++) {
+ result = scic_sds_phy_initialize(
+ &this_controller->phy_table[index],
+ &this_controller->scu_registers->peg0.pe[index].ll
+ );
+ }
+ }
+
+ if (result == SCI_SUCCESS) {
+ /* Initialize the logical ports */
+ for (index = 0;
+ (index < this_controller->logical_port_entries)
+ && (result == SCI_SUCCESS);
+ index++) {
+ result = scic_sds_port_initialize(
+ &this_controller->port_table[index],
+ &this_controller->scu_registers->peg0.pe[index].tl,
+ &this_controller->scu_registers->peg0.ptsg.port[index],
+ &this_controller->scu_registers->peg0.ptsg.protocol_engine,
+ &this_controller->scu_registers->peg0.viit[index]
+ );
+ }
+ }
+
+ if (SCI_SUCCESS == result) {
+ result = scic_sds_port_configuration_agent_initialize(
+ this_controller,
+ &this_controller->port_agent
+ );
+ }
+
+ /* Advance the controller state machine */
+ if (result == SCI_SUCCESS) {
+ sci_base_state_machine_change_state(
+ scic_sds_controller_get_base_state_machine(this_controller),
+ SCI_BASE_CONTROLLER_STATE_INITIALIZED
+ );
+ } else {
+ sci_base_state_machine_change_state(
+ scic_sds_controller_get_base_state_machine(this_controller),
+ SCI_BASE_CONTROLLER_STATE_FAILED
+ );
+ }
+
+ return result;
+}
+
+/*
+ * *****************************************************************************
+ * * INITIALIZED STATE HANDLERS
+ * ***************************************************************************** */
+
+/**
+ *
+ * @controller: This is the struct sci_base_controller object which is cast into a
+ * struct scic_sds_controller object.
+ * @timeout: This is the allowed time for the controller object to reach the
+ * started state.
+ *
+ * This method is the struct scic_sds_controller start handler for the initialized
+ * state. - Validate we have a good memory descriptor table - Initialze the
+ * physical memory before programming the hardware - Program the SCU hardware
+ * with the physical memory addresses passed in the memory descriptor table. -
+ * Initialzie the TCi pool - Initialize the RNi pool - Initialize the
+ * completion queue - Initialize the unsolicited frame data - Take the SCU port
+ * task scheduler out of reset - Start the first phy object. - Transition to
+ * SCI_BASE_CONTROLLER_STATE_STARTING. enum sci_status SCI_SUCCESS if all of the
+ * controller start operations complete
+ * SCI_FAILURE_UNSUPPORTED_INFORMATION_FIELD if one or more of the memory
+ * descriptor fields is invalid.
+ */
+static enum sci_status scic_sds_controller_initialized_state_start_handler(
+ struct sci_base_controller *controller,
+ u32 timeout)
+{
+ u16 index;
+ enum sci_status result;
+ struct scic_sds_controller *this_controller;
+
+ this_controller = (struct scic_sds_controller *)controller;
+
+ /* Make sure that the SCI User filled in the memory descriptor table correctly */
+ result = scic_sds_controller_validate_memory_descriptor_table(this_controller);
+
+ if (result == SCI_SUCCESS) {
+ /* The memory descriptor list looks good so program the hardware */
+ scic_sds_controller_ram_initialization(this_controller);
+ }
+
+ if (SCI_SUCCESS == result) {
+ /* Build the TCi free pool */
+ sci_pool_initialize(this_controller->tci_pool);
+ for (index = 0; index < this_controller->task_context_entries; index++) {
+ sci_pool_put(this_controller->tci_pool, index);
+ }
+
+ /* Build the RNi free pool */
+ scic_sds_remote_node_table_initialize(
+ &this_controller->available_remote_nodes,
+ this_controller->remote_node_entries
+ );
+ }
+
+ if (SCI_SUCCESS == result) {
+ /*
+ * Before anything else lets make sure we will not be interrupted
+ * by the hardware. */
+ scic_controller_disable_interrupts(this_controller);
+
+ /* Enable the port task scheduler */
+ scic_sds_controller_enable_port_task_scheduler(this_controller);
+
+ /* Assign all the task entries to this controller physical function */
+ scic_sds_controller_assign_task_entries(this_controller);
+
+ /* Now initialze the completion queue */
+ scic_sds_controller_initialize_completion_queue(this_controller);
+
+ /* Initialize the unsolicited frame queue for use */
+ scic_sds_controller_initialize_unsolicited_frame_queue(this_controller);
+ }
+
+ if (SCI_SUCCESS == result) {
+ scic_sds_controller_start_next_phy(this_controller);
+
+ scic_cb_timer_start(this_controller,
+ this_controller->timeout_timer,
+ timeout);
+
+ sci_base_state_machine_change_state(
+ scic_sds_controller_get_base_state_machine(this_controller),
+ SCI_BASE_CONTROLLER_STATE_STARTING
+ );
+ }
+
+ return result;
+}
+
+/*
+ * *****************************************************************************
+ * * INITIALIZED STATE HANDLERS
+ * ***************************************************************************** */
+
+/**
+ *
+ * @controller: This is struct scic_sds_controller which receives the link up
+ * notification.
+ * @port: This is struct scic_sds_port with which the phy is associated.
+ * @phy: This is the struct scic_sds_phy which has gone link up.
+ *
+ * This method is called when the struct scic_sds_controller is in the starting state
+ * link up handler is called. This method will perform the following: - Stop
+ * the phy timer - Start the next phy - Report the link up condition to the
+ * port object none
+ */
+static void scic_sds_controller_starting_state_link_up_handler(
+ struct scic_sds_controller *this_controller,
+ struct scic_sds_port *port,
+ struct scic_sds_phy *phy)
+{
+ scic_sds_controller_phy_timer_stop(this_controller);
+
+ this_controller->port_agent.link_up_handler(
+ this_controller, &this_controller->port_agent, port, phy
+ );
+ /* scic_sds_port_link_up(port, phy); */
+
+ scic_sds_controller_start_next_phy(this_controller);
+}
+
+/**
+ *
+ * @controller: This is struct scic_sds_controller which receives the link down
+ * notification.
+ * @port: This is struct scic_sds_port with which the phy is associated.
+ * @phy: This is the struct scic_sds_phy which has gone link down.
+ *
+ * This method is called when the struct scic_sds_controller is in the starting state
+ * link down handler is called. - Report the link down condition to the port
+ * object none
+ */
+static void scic_sds_controller_starting_state_link_down_handler(
+ struct scic_sds_controller *this_controller,
+ struct scic_sds_port *port,
+ struct scic_sds_phy *phy)
+{
+ this_controller->port_agent.link_down_handler(
+ this_controller, &this_controller->port_agent, port, phy
+ );
+ /* scic_sds_port_link_down(port, phy); */
+}
+
+/*
+ * *****************************************************************************
+ * * READY STATE HANDLERS
+ * ***************************************************************************** */
+
+/**
+ *
+ * @controller: The struct sci_base_controller object which is cast into a
+ * struct scic_sds_controller object.
+ * @timeout: The timeout for when the stop operation should report a failure.
+ *
+ * This method is called when the struct scic_sds_controller is in the ready state
+ * stop handler is called. - Start the timeout timer - Transition to
+ * SCI_BASE_CONTROLLER_STATE_STOPPING. enum sci_status SCI_SUCCESS
+ */
+static enum sci_status scic_sds_controller_ready_state_stop_handler(
+ struct sci_base_controller *controller,
+ u32 timeout)
+{
+ struct scic_sds_controller *this_controller;
+
+ this_controller = (struct scic_sds_controller *)controller;
+
+ scic_cb_timer_start(this_controller,
+ this_controller->timeout_timer,
+ timeout);
+
+ sci_base_state_machine_change_state(
+ scic_sds_controller_get_base_state_machine(this_controller),
+ SCI_BASE_CONTROLLER_STATE_STOPPING
+ );
+
+ return SCI_SUCCESS;
+}
+
+/**
+ *
+ * @controller: This is struct sci_base_controller object which is cast into a
+ * struct scic_sds_controller object.
+ * @remote_device: This is struct sci_base_remote_device which is cast to a
+ * struct scic_sds_remote_device object.
+ * @io_request: This is the struct sci_base_request which is cast to a
+ * SCIC_SDS_IO_REQUEST object.
+ * @io_tag: This is the IO tag to be assigned to the IO request or
+ * SCI_CONTROLLER_INVALID_IO_TAG.
+ *
+ * This method is called when the struct scic_sds_controller is in the ready state and
+ * the start io handler is called. - Start the io request on the remote device
+ * - if successful - assign the io_request to the io_request_table - post the
+ * request to the hardware enum sci_status SCI_SUCCESS if the start io operation
+ * succeeds SCI_FAILURE_INSUFFICIENT_RESOURCES if the IO tag could not be
+ * allocated for the io request. SCI_FAILURE_INVALID_STATE if one or more
+ * objects are not in a valid state to accept io requests. How does the io_tag
+ * parameter get assigned to the io request?
+ */
+static enum sci_status scic_sds_controller_ready_state_start_io_handler(
+ struct sci_base_controller *controller,
+ struct sci_base_remote_device *remote_device,
+ struct sci_base_request *io_request,
+ u16 io_tag)
+{
+ enum sci_status status;
+
+ struct scic_sds_controller *this_controller;
+ struct scic_sds_request *the_request;
+ struct scic_sds_remote_device *the_device;
+
+ this_controller = (struct scic_sds_controller *)controller;
+ the_request = (struct scic_sds_request *)io_request;
+ the_device = (struct scic_sds_remote_device *)remote_device;
+
+ status = scic_sds_remote_device_start_io(this_controller, the_device, the_request);
+
+ if (status == SCI_SUCCESS) {
+ this_controller->io_request_table[
+ scic_sds_io_tag_get_index(the_request->io_tag)] = the_request;
+
+ scic_sds_controller_post_request(
+ this_controller,
+ scic_sds_request_get_post_context(the_request)
+ );
+ }
+
+ return status;
+}
+
+/**
+ *
+ * @controller: This is struct sci_base_controller object which is cast into a
+ * struct scic_sds_controller object.
+ * @remote_device: This is struct sci_base_remote_device which is cast to a
+ * struct scic_sds_remote_device object.
+ * @io_request: This is the struct sci_base_request which is cast to a
+ * SCIC_SDS_IO_REQUEST object.
+ *
+ * This method is called when the struct scic_sds_controller is in the ready state and
+ * the complete io handler is called. - Complete the io request on the remote
+ * device - if successful - remove the io_request to the io_request_table
+ * enum sci_status SCI_SUCCESS if the start io operation succeeds
+ * SCI_FAILURE_INVALID_STATE if one or more objects are not in a valid state to
+ * accept io requests.
+ */
+static enum sci_status scic_sds_controller_ready_state_complete_io_handler(
+ struct sci_base_controller *controller,
+ struct sci_base_remote_device *remote_device,
+ struct sci_base_request *io_request)
+{
+ u16 index;
+ enum sci_status status;
+ struct scic_sds_controller *this_controller;
+ struct scic_sds_request *the_request;
+ struct scic_sds_remote_device *the_device;
+
+ this_controller = (struct scic_sds_controller *)controller;
+ the_request = (struct scic_sds_request *)io_request;
+ the_device = (struct scic_sds_remote_device *)remote_device;
+
+ status = scic_sds_remote_device_complete_io(
+ this_controller, the_device, the_request);
+
+ if (status == SCI_SUCCESS) {
+ index = scic_sds_io_tag_get_index(the_request->io_tag);
+ this_controller->io_request_table[index] = SCI_INVALID_HANDLE;
+ }
+
+ return status;
+}
+
+/**
+ *
+ * @controller: This is struct sci_base_controller object which is cast into a
+ * struct scic_sds_controller object.
+ * @remote_device: This is struct sci_base_remote_device which is cast to a
+ * struct scic_sds_remote_device object.
+ * @io_request: This is the struct sci_base_request which is cast to a
+ * SCIC_SDS_IO_REQUEST object.
+ *
+ * This method is called when the struct scic_sds_controller is in the ready state and
+ * the continue io handler is called. enum sci_status
+ */
+static enum sci_status scic_sds_controller_ready_state_continue_io_handler(
+ struct sci_base_controller *controller,
+ struct sci_base_remote_device *remote_device,
+ struct sci_base_request *io_request)
+{
+ struct scic_sds_controller *this_controller;
+ struct scic_sds_request *the_request;
+
+ the_request = (struct scic_sds_request *)io_request;
+ this_controller = (struct scic_sds_controller *)controller;
+
+ this_controller->io_request_table[
+ scic_sds_io_tag_get_index(the_request->io_tag)] = the_request;
+
+ scic_sds_controller_post_request(
+ this_controller,
+ scic_sds_request_get_post_context(the_request)
+ );
+
+ return SCI_SUCCESS;
+}
+
+/**
+ *
+ * @controller: This is struct sci_base_controller object which is cast into a
+ * struct scic_sds_controller object.
+ * @remote_device: This is struct sci_base_remote_device which is cast to a
+ * struct scic_sds_remote_device object.
+ * @io_request: This is the struct sci_base_request which is cast to a
+ * SCIC_SDS_IO_REQUEST object.
+ * @task_tag: This is the task tag to be assigned to the task request or
+ * SCI_CONTROLLER_INVALID_IO_TAG.
+ *
+ * This method is called when the struct scic_sds_controller is in the ready state and
+ * the start task handler is called. - The remote device is requested to start
+ * the task request - if successful - assign the task to the io_request_table -
+ * post the request to the SCU hardware enum sci_status SCI_SUCCESS if the start io
+ * operation succeeds SCI_FAILURE_INSUFFICIENT_RESOURCES if the IO tag could
+ * not be allocated for the io request. SCI_FAILURE_INVALID_STATE if one or
+ * more objects are not in a valid state to accept io requests. How does the io
+ * tag get assigned in this code path?
+ */
+static enum sci_status scic_sds_controller_ready_state_start_task_handler(
+ struct sci_base_controller *controller,
+ struct sci_base_remote_device *remote_device,
+ struct sci_base_request *io_request,
+ u16 task_tag)
+{
+ struct scic_sds_controller *this_controller = (struct scic_sds_controller *)
+ controller;
+ struct scic_sds_request *the_request = (struct scic_sds_request *)
+ io_request;
+ struct scic_sds_remote_device *the_device = (struct scic_sds_remote_device *)
+ remote_device;
+ enum sci_status status;
+
+ status = scic_sds_remote_device_start_task(
+ this_controller, the_device, the_request
+ );
+
+ if (status == SCI_SUCCESS) {
+ this_controller->io_request_table[
+ scic_sds_io_tag_get_index(the_request->io_tag)] = the_request;
+
+ scic_sds_controller_post_request(
+ this_controller,
+ scic_sds_request_get_post_context(the_request)
+ );
+ } else if (status == SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS) {
+ this_controller->io_request_table[
+ scic_sds_io_tag_get_index(the_request->io_tag)] = the_request;
+
+ /*
+ * We will let framework know this task request started successfully,
+ * although core is still woring on starting the request (to post tc when
+ * RNC is resumed.) */
+ status = SCI_SUCCESS;
+ }
+ return status;
+}
+
+/**
+ *
+ * @controller: This is struct sci_base_controller object which is cast into a
+ * struct scic_sds_controller object.
+ * @remote_device: This is struct sci_base_remote_device which is cast to a
+ * struct scic_sds_remote_device object.
+ * @io_request: This is the struct sci_base_request which is cast to a
+ * SCIC_SDS_IO_REQUEST object.
+ *
+ * This method is called when the struct scic_sds_controller is in the ready state and
+ * the terminate request handler is called. - call the io request terminate
+ * function - if successful - post the terminate request to the SCU hardware
+ * enum sci_status SCI_SUCCESS if the start io operation succeeds
+ * SCI_FAILURE_INVALID_STATE if one or more objects are not in a valid state to
+ * accept io requests.
+ */
+static enum sci_status scic_sds_controller_ready_state_terminate_request_handler(
+ struct sci_base_controller *controller,
+ struct sci_base_remote_device *remote_device,
+ struct sci_base_request *io_request)
+{
+ struct scic_sds_controller *this_controller = (struct scic_sds_controller *)
+ controller;
+ struct scic_sds_request *the_request = (struct scic_sds_request *)
+ io_request;
+ enum sci_status status;
+
+ status = scic_sds_io_request_terminate(the_request);
+ if (status == SCI_SUCCESS) {
+ /*
+ * Utilize the original post context command and or in the POST_TC_ABORT
+ * request sub-type. */
+ scic_sds_controller_post_request(
+ this_controller,
+ scic_sds_request_get_post_context(the_request)
+ | SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT
+ );
+ }
+
+ return status;
+}
+
+/**
+ *
+ * @controller: This is struct scic_sds_controller which receives the link up
+ * notification.
+ * @port: This is struct scic_sds_port with which the phy is associated.
+ * @phy: This is the struct scic_sds_phy which has gone link up.
+ *
+ * This method is called when the struct scic_sds_controller is in the starting state
+ * link up handler is called. This method will perform the following: - Stop
+ * the phy timer - Start the next phy - Report the link up condition to the
+ * port object none
+ */
+static void scic_sds_controller_ready_state_link_up_handler(
+ struct scic_sds_controller *this_controller,
+ struct scic_sds_port *port,
+ struct scic_sds_phy *phy)
+{
+ this_controller->port_agent.link_up_handler(
+ this_controller, &this_controller->port_agent, port, phy
+ );
+}
+
+/**
+ *
+ * @controller: This is struct scic_sds_controller which receives the link down
+ * notification.
+ * @port: This is struct scic_sds_port with which the phy is associated.
+ * @phy: This is the struct scic_sds_phy which has gone link down.
+ *
+ * This method is called when the struct scic_sds_controller is in the starting state
+ * link down handler is called. - Report the link down condition to the port
+ * object none
+ */
+static void scic_sds_controller_ready_state_link_down_handler(
+ struct scic_sds_controller *this_controller,
+ struct scic_sds_port *port,
+ struct scic_sds_phy *phy)
+{
+ this_controller->port_agent.link_down_handler(
+ this_controller, &this_controller->port_agent, port, phy
+ );
+}
+
+/*
+ * *****************************************************************************
+ * * STOPPING STATE HANDLERS
+ * ***************************************************************************** */
+
+/**
+ *
+ * @controller: This is struct sci_base_controller object which is cast into a
+ * struct scic_sds_controller object.
+ * @remote_device: This is struct sci_base_remote_device which is cast to a
+ * struct scic_sds_remote_device object.
+ * @io_request: This is the struct sci_base_request which is cast to a
+ * SCIC_SDS_IO_REQUEST object.
+ *
+ * This method is called when the struct scic_sds_controller is in a stopping state
+ * and the complete io handler is called. - This function is not yet
+ * implemented enum sci_status SCI_FAILURE
+ */
+static enum sci_status scic_sds_controller_stopping_state_complete_io_handler(
+ struct sci_base_controller *controller,
+ struct sci_base_remote_device *remote_device,
+ struct sci_base_request *io_request)
+{
+ struct scic_sds_controller *this_controller;
+
+ this_controller = (struct scic_sds_controller *)controller;
+
+ /* / @todo Implement this function */
+ return SCI_FAILURE;
+}
+
+/**
+ *
+ * @controller: This is struct sci_base_controller object which is cast into a
+ * struct scic_sds_controller object.
+ * @remote_device: This is struct sci_base_remote_device which is cast to a
+ * struct scic_sds_remote_device object.
+ * @io_request: This is the struct sci_base_request which is cast to a
+ * SCIC_SDS_IO_REQUEST object.
+ *
+ * This method is called when the struct scic_sds_controller is in a stopping state
+ * and the complete task handler is called. - This function is not yet
+ * implemented enum sci_status SCI_FAILURE
+ */
+
+/*
+ * *****************************************************************************
+ * * STOPPED STATE HANDLERS
+ * ***************************************************************************** */
+
+/*
+ * *****************************************************************************
+ * * FAILED STATE HANDLERS
+ * ***************************************************************************** */
+
+const struct scic_sds_controller_state_handler scic_sds_controller_state_handler_table[] = {
+ [SCI_BASE_CONTROLLER_STATE_INITIAL] = {
+ .base.start_io = scic_sds_controller_default_start_operation_handler,
+ .base.complete_io = scic_sds_controller_default_request_handler,
+ .base.continue_io = scic_sds_controller_default_request_handler,
+ .terminate_request = scic_sds_controller_default_request_handler,
+ },
+ [SCI_BASE_CONTROLLER_STATE_RESET] = {
+ .base.initialize = scic_sds_controller_reset_state_initialize_handler,
+ .base.start_io = scic_sds_controller_default_start_operation_handler,
+ .base.complete_io = scic_sds_controller_default_request_handler,
+ .base.continue_io = scic_sds_controller_default_request_handler,
+ .terminate_request = scic_sds_controller_default_request_handler,
+ },
+ [SCI_BASE_CONTROLLER_STATE_INITIALIZING] = {
+ .base.start_io = scic_sds_controller_default_start_operation_handler,
+ .base.complete_io = scic_sds_controller_default_request_handler,
+ .base.continue_io = scic_sds_controller_default_request_handler,
+ .terminate_request = scic_sds_controller_default_request_handler,
+ },
+ [SCI_BASE_CONTROLLER_STATE_INITIALIZED] = {
+ .base.start = scic_sds_controller_initialized_state_start_handler,
+ .base.start_io = scic_sds_controller_default_start_operation_handler,
+ .base.complete_io = scic_sds_controller_default_request_handler,
+ .base.continue_io = scic_sds_controller_default_request_handler,
+ .terminate_request = scic_sds_controller_default_request_handler,
+ },
+ [SCI_BASE_CONTROLLER_STATE_STARTING] = {
+ .base.start_io = scic_sds_controller_default_start_operation_handler,
+ .base.complete_io = scic_sds_controller_default_request_handler,
+ .base.continue_io = scic_sds_controller_default_request_handler,
+ .terminate_request = scic_sds_controller_default_request_handler,
+ .link_up = scic_sds_controller_starting_state_link_up_handler,
+ .link_down = scic_sds_controller_starting_state_link_down_handler
+ },
+ [SCI_BASE_CONTROLLER_STATE_READY] = {
+ .base.stop = scic_sds_controller_ready_state_stop_handler,
+ .base.reset = scic_sds_controller_general_reset_handler,
+ .base.start_io = scic_sds_controller_ready_state_start_io_handler,
+ .base.complete_io = scic_sds_controller_ready_state_complete_io_handler,
+ .base.continue_io = scic_sds_controller_ready_state_continue_io_handler,
+ .base.start_task = scic_sds_controller_ready_state_start_task_handler,
+ .base.complete_task = scic_sds_controller_ready_state_complete_io_handler,
+ .terminate_request = scic_sds_controller_ready_state_terminate_request_handler,
+ .link_up = scic_sds_controller_ready_state_link_up_handler,
+ .link_down = scic_sds_controller_ready_state_link_down_handler
+ },
+ [SCI_BASE_CONTROLLER_STATE_RESETTING] = {
+ .base.start_io = scic_sds_controller_default_start_operation_handler,
+ .base.complete_io = scic_sds_controller_default_request_handler,
+ .base.continue_io = scic_sds_controller_default_request_handler,
+ .terminate_request = scic_sds_controller_default_request_handler,
+ },
+ [SCI_BASE_CONTROLLER_STATE_STOPPING] = {
+ .base.start_io = scic_sds_controller_default_start_operation_handler,
+ .base.complete_io = scic_sds_controller_stopping_state_complete_io_handler,
+ .base.continue_io = scic_sds_controller_default_request_handler,
+ .terminate_request = scic_sds_controller_default_request_handler,
+ },
+ [SCI_BASE_CONTROLLER_STATE_STOPPED] = {
+ .base.reset = scic_sds_controller_general_reset_handler,
+ .base.start_io = scic_sds_controller_default_start_operation_handler,
+ .base.complete_io = scic_sds_controller_default_request_handler,
+ .base.continue_io = scic_sds_controller_default_request_handler,
+ .terminate_request = scic_sds_controller_default_request_handler,
+ },
+ [SCI_BASE_CONTROLLER_STATE_FAILED] = {
+ .base.reset = scic_sds_controller_general_reset_handler,
+ .base.start_io = scic_sds_controller_default_start_operation_handler,
+ .base.complete_io = scic_sds_controller_default_request_handler,
+ .base.continue_io = scic_sds_controller_default_request_handler,
+ .terminate_request = scic_sds_controller_default_request_handler,
+ },
+};
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_controller
+ * object.
+ *
+ * This method implements the actions taken by the struct scic_sds_controller on entry
+ * to the SCI_BASE_CONTROLLER_STATE_INITIAL. - Set the state handlers to the
+ * controllers initial state. none This function should initialze the
+ * controller object.
+ */
+static void scic_sds_controller_initial_state_enter(
+ struct sci_base_object *object)
+{
+ struct scic_sds_controller *this_controller;
+
+ this_controller = (struct scic_sds_controller *)object;
+
+ sci_base_state_machine_change_state(
+ &this_controller->parent.state_machine, SCI_BASE_CONTROLLER_STATE_RESET);
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_controller
+ * object.
+ *
+ * This method implements the actions taken by the struct scic_sds_controller on exit
+ * from the SCI_BASE_CONTROLLER_STATE_STARTING. - This function stops the
+ * controller starting timeout timer. none
+ */
+static void scic_sds_controller_starting_state_exit(
+ struct sci_base_object *object)
+{
+ struct scic_sds_controller *scic = (struct scic_sds_controller *)object;
+
+ scic_cb_timer_stop(scic, scic->timeout_timer);
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_controller
+ * object.
+ *
+ * This method implements the actions taken by the struct scic_sds_controller on entry
+ * to the SCI_BASE_CONTROLLER_STATE_READY. - Set the state handlers to the
+ * controllers ready state. none
+ */
+static void scic_sds_controller_ready_state_enter(
+ struct sci_base_object *object)
+{
+ struct scic_sds_controller *this_controller;
+
+ this_controller = (struct scic_sds_controller *)object;
+
+ /* set the default interrupt coalescence number and timeout value. */
+ scic_controller_set_interrupt_coalescence(
+ this_controller, 0x10, 250);
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_controller
+ * object.
+ *
+ * This method implements the actions taken by the struct scic_sds_controller on exit
+ * from the SCI_BASE_CONTROLLER_STATE_READY. - This function does nothing. none
+ */
+static void scic_sds_controller_ready_state_exit(
+ struct sci_base_object *object)
+{
+ struct scic_sds_controller *this_controller;
+
+ this_controller = (struct scic_sds_controller *)object;
+
+ /* disable interrupt coalescence. */
+ scic_controller_set_interrupt_coalescence(this_controller, 0, 0);
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_controller
+ * object.
+ *
+ * This method implements the actions taken by the struct scic_sds_controller on entry
+ * to the SCI_BASE_CONTROLLER_STATE_READY. - Set the state handlers to the
+ * controllers ready state. - Stop the phys on this controller - Stop the ports
+ * on this controller - Stop all of the remote devices on this controller none
+ */
+static void scic_sds_controller_stopping_state_enter(
+ struct sci_base_object *object)
+{
+ struct scic_sds_controller *this_controller;
+
+ this_controller = (struct scic_sds_controller *)object;
+
+ /* Stop all of the components for this controller */
+ scic_sds_controller_stop_phys(this_controller);
+ scic_sds_controller_stop_ports(this_controller);
+ scic_sds_controller_stop_devices(this_controller);
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_controller
+ * object.
+ *
+ * This method implements the actions taken by the struct scic_sds_controller on exit
+ * from the SCI_BASE_CONTROLLER_STATE_STOPPING. - This function stops the
+ * controller stopping timeout timer. none
+ */
+static void scic_sds_controller_stopping_state_exit(
+ struct sci_base_object *object)
+{
+ struct scic_sds_controller *this_controller;
+
+ this_controller = (struct scic_sds_controller *)object;
+
+ scic_cb_timer_stop(this_controller, this_controller->timeout_timer);
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_controller
+ * object.
+ *
+ * This method implements the actions taken by the struct scic_sds_controller on entry
+ * to the SCI_BASE_CONTROLLER_STATE_RESETTING. - Set the state handlers to the
+ * controllers resetting state. - Write to the SCU hardware reset register to
+ * force a reset - Transition to the SCI_BASE_CONTROLLER_STATE_RESET none
+ */
+static void scic_sds_controller_resetting_state_enter(
+ struct sci_base_object *object)
+{
+ struct scic_sds_controller *this_controller;
+
+ this_controller = (struct scic_sds_controller *)object;
+
+ scic_sds_controller_reset_hardware(this_controller);
+
+ sci_base_state_machine_change_state(
+ scic_sds_controller_get_base_state_machine(this_controller),
+ SCI_BASE_CONTROLLER_STATE_RESET
+ );
+}
+
+/* --------------------------------------------------------------------------- */
+
+const struct sci_base_state scic_sds_controller_state_table[] = {
+ [SCI_BASE_CONTROLLER_STATE_INITIAL] = {
+ .enter_state = scic_sds_controller_initial_state_enter,
+ },
+ [SCI_BASE_CONTROLLER_STATE_RESET] = {},
+ [SCI_BASE_CONTROLLER_STATE_INITIALIZING] = {},
+ [SCI_BASE_CONTROLLER_STATE_INITIALIZED] = {},
+ [SCI_BASE_CONTROLLER_STATE_STARTING] = {
+ .exit_state = scic_sds_controller_starting_state_exit,
+ },
+ [SCI_BASE_CONTROLLER_STATE_READY] = {
+ .enter_state = scic_sds_controller_ready_state_enter,
+ .exit_state = scic_sds_controller_ready_state_exit,
+ },
+ [SCI_BASE_CONTROLLER_STATE_RESETTING] = {
+ .enter_state = scic_sds_controller_resetting_state_enter,
+ },
+ [SCI_BASE_CONTROLLER_STATE_STOPPING] = {
+ .enter_state = scic_sds_controller_stopping_state_enter,
+ .exit_state = scic_sds_controller_stopping_state_exit,
+ },
+ [SCI_BASE_CONTROLLER_STATE_STOPPED] = {},
+ [SCI_BASE_CONTROLLER_STATE_FAILED] = {}
+};
+
diff --git a/drivers/scsi/isci/core/scic_sds_controller.h b/drivers/scsi/isci/core/scic_sds_controller.h
new file mode 100644
index 000000000000..afa45f9874a4
--- /dev/null
+++ b/drivers/scsi/isci/core/scic_sds_controller.h
@@ -0,0 +1,706 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCIC_SDS_CONTROLLER_H_
+#define _SCIC_SDS_CONTROLLER_H_
+
+/**
+ * This file contains the structures, constants and prototypes used for the
+ * core controller object.
+ *
+ *
+ */
+
+#include "sci_pool.h"
+#include "sci_controller_constants.h"
+#include "sci_memory_descriptor_list.h"
+#include "sci_base_controller.h"
+#include "scic_config_parameters.h"
+#include "scic_sds_port.h"
+#include "scic_sds_phy.h"
+#include "scic_sds_remote_node_table.h"
+#include "scu_registers.h"
+#include "scu_constants.h"
+#include "scu_remote_node_context.h"
+#include "scu_task_context.h"
+#include "scu_unsolicited_frame.h"
+#include "scic_sds_unsolicited_frame_control.h"
+#include "scic_sds_port_configuration_agent.h"
+#include "scic_sds_pci.h"
+
+struct scic_sds_remote_device;
+struct scic_sds_request;
+struct scic_sds_controller;
+
+
+#define SCU_COMPLETION_RAM_ALIGNMENT (64)
+
+/**
+ * enum SCIC_SDS_CONTROLLER_MEMORY_DESCRIPTORS -
+ *
+ * This enumeration depects the types of MDEs that are going to be created for
+ * the controller object.
+ */
+enum SCIC_SDS_CONTROLLER_MEMORY_DESCRIPTORS {
+ /**
+ * Completion queue MDE entry
+ */
+ SCU_MDE_COMPLETION_QUEUE,
+
+ /**
+ * Remote node context MDE entry
+ */
+ SCU_MDE_REMOTE_NODE_CONTEXT,
+
+ /**
+ * Task context MDE entry
+ */
+ SCU_MDE_TASK_CONTEXT,
+
+ /**
+ * Unsolicited frame buffer MDE entrys this is the start of the unsolicited
+ * frame buffer entries.
+ */
+ SCU_MDE_UF_BUFFER,
+
+ SCU_MAX_MDES
+};
+
+/**
+ *
+ *
+ * Allowed PORT configuration modes APC Automatic PORT configuration mode is
+ * defined by the OEM configuration parameters providing no PHY_MASK parameters
+ * for any PORT. i.e. There are no phys assigned to any of the ports at start.
+ * MPC Manual PORT configuration mode is defined by the OEM configuration
+ * parameters providing a PHY_MASK value for any PORT. It is assumed that any
+ * PORT with no PHY_MASK is an invalid port and not all PHYs must be assigned.
+ * A PORT_PHY mask that assigns just a single PHY to a port and no other PHYs
+ * being assigned is sufficient to declare manual PORT configuration.
+ */
+enum SCIC_PORT_CONFIGURATION_MODE {
+ SCIC_PORT_MANUAL_CONFIGURATION_MODE,
+ SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE
+};
+
+/**
+ * struct scic_power_control -
+ *
+ * This structure defines the fields for managing power control for direct
+ * attached disk devices.
+ */
+struct scic_power_control {
+ /**
+ * This field is set when the power control timer is running and cleared when
+ * it is not.
+ */
+ bool timer_started;
+
+ /**
+ * This field is the handle to the driver timer object. This timer is used to
+ * control when the directed attached disks can consume power.
+ */
+ void *timer;
+
+ /**
+ * This field is used to keep track of how many phys are put into the
+ * requesters field.
+ */
+ u8 phys_waiting;
+
+ /**
+ * This field is an array of phys that we are waiting on. The phys are direct
+ * mapped into requesters via struct scic_sds_phy.phy_index
+ */
+ struct scic_sds_phy *requesters[SCI_MAX_PHYS];
+
+};
+
+/**
+ * struct scic_sds_controller -
+ *
+ * This structure represents the SCU contoller object.
+ */
+struct scic_sds_controller {
+ /**
+ * The struct sci_base_controller is the parent object for the struct scic_sds_controller
+ * object.
+ */
+ struct sci_base_controller parent;
+
+ /**
+ * This field is the driver timer object handler used to time the controller
+ * object start and stop requests.
+ */
+ void *timeout_timer;
+
+ /**
+ * This field contains the user parameters to be utilized for this
+ * core controller object.
+ */
+ union scic_user_parameters user_parameters;
+
+ /**
+ * This field contains the OEM parameters to be utilized for this
+ * core controller object.
+ */
+ union scic_oem_parameters oem_parameters;
+
+ /**
+ * This field contains the port configuration agent for this controller.
+ */
+ struct scic_sds_port_configuration_agent port_agent;
+
+ /**
+ * This field is the array of port objects that are controlled by this
+ * controller object. There is one dummy port object also contained within
+ * this controller object.
+ */
+ struct scic_sds_port port_table[SCI_MAX_PORTS + 1];
+
+ /**
+ * This field is the array of phy objects that are controlled by this
+ * controller object.
+ */
+ struct scic_sds_phy phy_table[SCI_MAX_PHYS];
+
+ /**
+ * This field is the array of device objects that are currently constructed
+ * for this controller object. This table is used as a fast lookup of device
+ * objects that need to handle device completion notifications from the
+ * hardware. The table is RNi based.
+ */
+ struct scic_sds_remote_device *device_table[SCI_MAX_REMOTE_DEVICES];
+
+ /**
+ * This field is the array of IO request objects that are currently active for
+ * this controller object. This table is used as a fast lookup of the io
+ * request object that need to handle completion queue notifications. The
+ * table is TCi based.
+ */
+ struct scic_sds_request *io_request_table[SCI_MAX_IO_REQUESTS];
+
+ /**
+ * This field is the free RNi data structure
+ */
+ struct scic_remote_node_table available_remote_nodes;
+
+ /**
+ * This field is the TCi pool used to manage the task context index.
+ */
+ SCI_POOL_CREATE(tci_pool, u16, SCI_MAX_IO_REQUESTS);
+
+ /**
+ * This filed is the struct scic_power_control data used to controll when direct
+ * attached devices can consume power.
+ */
+ struct scic_power_control power_control;
+
+ /**
+ * This field is the array of sequence values for the IO Tag fields. Even
+ * though only 4 bits of the field is used for the sequence the sequence is 16
+ * bits in size so the sequence can be bitwise or'd with the TCi to build the
+ * IO Tag value.
+ */
+ u16 io_request_sequence[SCI_MAX_IO_REQUESTS];
+
+ /**
+ * This field in the array of sequence values for the RNi. These are used
+ * to control io request build to io request start operations. The sequence
+ * value is recorded into an io request when it is built and is checked on
+ * the io request start operation to make sure that there was not a device
+ * hot plug between the build and start operation.
+ */
+ u8 remote_device_sequence[SCI_MAX_REMOTE_DEVICES];
+
+ /**
+ * This field is a pointer to the memory allocated by the driver for the task
+ * context table. This data is shared between the hardware and software.
+ */
+ struct scu_task_context *task_context_table;
+
+ /**
+ * This field is a pointer to the memory allocated by the driver for the
+ * remote node context table. This table is shared between the hardware and
+ * software.
+ */
+ union scu_remote_node_context *remote_node_context_table;
+
+ /**
+ * This field is the array of physical memory requiremets for this controller
+ * object.
+ */
+ struct sci_physical_memory_descriptor memory_descriptors[SCU_MAX_MDES];
+
+ /**
+ * This field is a pointer to the completion queue. This memory is
+ * written to by the hardware and read by the software.
+ */
+ u32 *completion_queue;
+
+ /**
+ * This field is the software copy of the completion queue get pointer. The
+ * controller object writes this value to the hardware after processing the
+ * completion entries.
+ */
+ u32 completion_queue_get;
+
+ /**
+ * This field is the minimum of the number of hardware supported port entries
+ * and the software requested port entries.
+ */
+ u32 logical_port_entries;
+
+ /**
+ * This field is the minimum number of hardware supported completion queue
+ * entries and the software requested completion queue entries.
+ */
+ u32 completion_queue_entries;
+
+ /**
+ * This field is the minimum number of hardware supported event entries and
+ * the software requested event entries.
+ */
+ u32 completion_event_entries;
+
+ /**
+ * This field is the minimum number of devices supported by the hardware and
+ * the number of devices requested by the software.
+ */
+ u32 remote_node_entries;
+
+ /**
+ * This field is the minimum number of IO requests supported by the hardware
+ * and the number of IO requests requested by the software.
+ */
+ u32 task_context_entries;
+
+ /**
+ * This object contains all of the unsolicited frame specific
+ * data utilized by the core controller.
+ */
+ struct scic_sds_unsolicited_frame_control uf_control;
+
+ /**
+ * This field records the fact that the controller has encountered a fatal
+ * error and must be reset.
+ */
+ bool encountered_fatal_error;
+
+ /**
+ * This field specifies that the controller should ignore
+ * completion processing for non-fastpath events. This will
+ * cause the completions to be thrown away.
+ */
+ bool restrict_completions;
+
+ /* Phy Startup Data */
+ /**
+ * This field is the driver timer handle for controller phy request startup.
+ * On controller start the controller will start each PHY individually in
+ * order of phy index.
+ */
+ void *phy_startup_timer;
+
+ /**
+ * This field is set when the phy_startup_timer is running and is cleared when
+ * the phy_startup_timer is stopped.
+ */
+ bool phy_startup_timer_pending;
+
+ /**
+ * This field is the index of the next phy start. It is initialized to 0 and
+ * increments for each phy index that is started.
+ */
+ u32 next_phy_to_start;
+
+ /**
+ * This field controlls the invalid link up notifications to the SCI_USER. If
+ * an invalid_link_up notification is reported a bit for the PHY index is set
+ * so further notifications are not made. Once the PHY object reports link up
+ * and is made part of a port then this bit for the PHY index is cleared.
+ */
+ u8 invalid_phy_mask;
+
+ /*
+ * This field saves the current interrupt coalescing number of the controller.
+ */
+ u16 interrupt_coalesce_number;
+
+ /*
+ * This field saves the current interrupt coalescing timeout value in microseconds.
+ */
+ u32 interrupt_coalesce_timeout;
+
+ /**
+ * This field is a pointer to the memory mapped register space for the
+ * struct smu_registers.
+ */
+ struct smu_registers __iomem *smu_registers;
+
+ /**
+ * This field is a pointer to the memory mapped register space for the
+ * struct scu_registers.
+ */
+ struct scu_registers __iomem *scu_registers;
+
+};
+
+typedef void (*scic_sds_controller_phy_handler_t)(struct scic_sds_controller *,
+ struct scic_sds_port *,
+ struct scic_sds_phy *);
+/**
+ * struct scic_sds_controller_state_handler -
+ *
+ * This structure contains the SDS core specific definition for the state
+ * handlers.
+ */
+struct scic_sds_controller_state_handler {
+ struct sci_base_controller_state_handler base;
+
+ sci_base_controller_request_handler_t terminate_request;
+ scic_sds_controller_phy_handler_t link_up;
+ scic_sds_controller_phy_handler_t link_down;
+};
+
+extern const struct scic_sds_controller_state_handler
+ scic_sds_controller_state_handler_table[];
+extern const struct sci_base_state scic_sds_controller_state_table[];
+
+/**
+ * INCREMENT_QUEUE_GET() -
+ *
+ * This macro will increment the specified index to and if the index wraps to 0
+ * it will toggel the cycle bit.
+ */
+#define INCREMENT_QUEUE_GET(index, cycle, entry_count, bit_toggle) \
+ { \
+ if ((index) + 1 == entry_count) { \
+ (index) = 0; \
+ (cycle) = (cycle) ^ (bit_toggle); \
+ } else { \
+ index = index + 1; \
+ } \
+ }
+
+/**
+ * scic_sds_controller_get_base_state_machine() -
+ *
+ * This is a helper macro that gets the base state machine for the controller
+ * object
+ */
+#define scic_sds_controller_get_base_state_machine(this_controller) \
+ (&(this_controller)->parent.state_machine)
+
+/**
+ * scic_sds_controller_get_port_configuration_agent() -
+ *
+ * This is a helper macro to get the port configuration agent from the
+ * controller object.
+ */
+#define scic_sds_controller_get_port_configuration_agent(controller) \
+ (&(controller)->port_agent)
+
+/**
+ * smu_register_write() -
+ *
+ * This macro writes to the smu_register for this controller
+ */
+#define smu_register_write(controller, reg, value) \
+ scic_sds_pci_write_smu_dword((controller), &(reg), (value))
+
+/**
+ * smu_register_read() -
+ *
+ * This macro reads the smu_register for this controller
+ */
+#define smu_register_read(controller, reg) \
+ scic_sds_pci_read_smu_dword((controller), &(reg))
+
+/**
+ * scu_register_write() -
+ *
+ * This mcaro writes the scu_register for this controller
+ */
+#define scu_register_write(controller, reg, value) \
+ scic_sds_pci_write_scu_dword((controller), &(reg), (value))
+
+/**
+ * scu_register_read() -
+ *
+ * This macro reads the scu_register for this controller
+ */
+#define scu_register_read(controller, reg) \
+ scic_sds_pci_read_scu_dword((controller), &(reg))
+
+/**
+ * scic_sds_controller_get_protocol_engine_group() -
+ *
+ * This macro returns the protocol engine group for this controller object.
+ * Presently we only support protocol engine group 0 so just return that
+ */
+#define scic_sds_controller_get_protocol_engine_group(controller) 0
+
+/**
+ * scic_sds_io_tag_construct() -
+ *
+ * This macro constructs an IO tag from the sequence and index values.
+ */
+#define scic_sds_io_tag_construct(sequence, task_index) \
+ ((sequence) << 12 | (task_index))
+
+/**
+ * scic_sds_io_tag_get_sequence() -
+ *
+ * This macro returns the IO sequence from the IO tag value.
+ */
+#define scic_sds_io_tag_get_sequence(io_tag) \
+ (((io_tag) & 0xF000) >> 12)
+
+/**
+ * scic_sds_io_tag_get_index() -
+ *
+ * This macro returns the TCi from the io tag value
+ */
+#define scic_sds_io_tag_get_index(io_tag) \
+ ((io_tag) & 0x0FFF)
+
+/**
+ * scic_sds_io_sequence_increment() -
+ *
+ * This is a helper macro to increment the io sequence count. We may find in
+ * the future that it will be faster to store the sequence count in such a way
+ * as we dont perform the shift operation to build io tag values so therefore
+ * need a way to incrment them correctly
+ */
+#define scic_sds_io_sequence_increment(value) \
+ ((value) = (((value) + 1) & 0x000F))
+
+#define scic_sds_remote_device_node_count(device) \
+ (\
+ (\
+ (device)->target_protocols.u.bits.attached_stp_target \
+ && ((device)->is_direct_attached != true) \
+ ) \
+ ? SCU_STP_REMOTE_NODE_COUNT : SCU_SSP_REMOTE_NODE_COUNT \
+ )
+
+/**
+ * scic_sds_controller_set_invalid_phy() -
+ *
+ * This macro will set the bit in the invalid phy mask for this controller
+ * object. This is used to control messages reported for invalid link up
+ * notifications.
+ */
+#define scic_sds_controller_set_invalid_phy(controller, phy) \
+ ((controller)->invalid_phy_mask |= (1 << (phy)->phy_index))
+
+/**
+ * scic_sds_controller_clear_invalid_phy() -
+ *
+ * This macro will clear the bit in the invalid phy mask for this controller
+ * object. This is used to control messages reported for invalid link up
+ * notifications.
+ */
+#define scic_sds_controller_clear_invalid_phy(controller, phy) \
+ ((controller)->invalid_phy_mask &= ~(1 << (phy)->phy_index))
+
+/* --------------------------------------------------------------------------- */
+
+u32 scic_sds_controller_get_object_size(void);
+
+/* --------------------------------------------------------------------------- */
+
+
+/* --------------------------------------------------------------------------- */
+
+enum SCIC_PORT_CONFIGURATION_MODE scic_sds_controller_get_port_configuration_mode(
+ struct scic_sds_controller *this_controller);
+
+/* --------------------------------------------------------------------------- */
+
+void scic_sds_controller_post_request(
+ struct scic_sds_controller *this_controller,
+ u32 request);
+
+/* --------------------------------------------------------------------------- */
+
+void scic_sds_controller_release_frame(
+ struct scic_sds_controller *this_controller,
+ u32 frame_index);
+
+void scic_sds_controller_copy_sata_response(
+ void *response_buffer,
+ void *frame_header,
+ void *frame_buffer);
+
+/* --------------------------------------------------------------------------- */
+
+enum sci_status scic_sds_controller_allocate_remote_node_context(
+ struct scic_sds_controller *this_controller,
+ struct scic_sds_remote_device *the_device,
+ u16 *node_id);
+
+void scic_sds_controller_free_remote_node_context(
+ struct scic_sds_controller *this_controller,
+ struct scic_sds_remote_device *the_device,
+ u16 node_id);
+
+union scu_remote_node_context *scic_sds_controller_get_remote_node_context_buffer(
+ struct scic_sds_controller *this_controller,
+ u16 node_id);
+
+/* --------------------------------------------------------------------------- */
+
+struct scic_sds_request *scic_sds_controller_get_io_request_from_tag(
+ struct scic_sds_controller *this_controller,
+ u16 io_tag);
+
+
+struct scu_task_context *scic_sds_controller_get_task_context_buffer(
+ struct scic_sds_controller *this_controller,
+ u16 io_tag);
+
+/*
+ * *****************************************************************************
+ * * CORE CONTROLLER POWER CONTROL METHODS
+ * ***************************************************************************** */
+
+
+void scic_sds_controller_power_control_queue_insert(
+ struct scic_sds_controller *this_controller,
+ struct scic_sds_phy *the_phy);
+
+void scic_sds_controller_power_control_queue_remove(
+ struct scic_sds_controller *this_controller,
+ struct scic_sds_phy *the_phy);
+
+/*
+ * *****************************************************************************
+ * * CORE CONTROLLER PHY MESSAGE PROCESSING
+ * ***************************************************************************** */
+
+void scic_sds_controller_link_up(
+ struct scic_sds_controller *this_controller,
+ struct scic_sds_port *the_port,
+ struct scic_sds_phy *the_phy);
+
+void scic_sds_controller_link_down(
+ struct scic_sds_controller *this_controller,
+ struct scic_sds_port *the_port,
+ struct scic_sds_phy *the_phy);
+
+/*
+ * *****************************************************************************
+ * * CORE CONTROLLER PRIVATE METHODS
+ * ***************************************************************************** */
+
+enum sci_status scic_sds_controller_validate_memory_descriptor_table(
+ struct scic_sds_controller *this_controller);
+
+void scic_sds_controller_ram_initialization(
+ struct scic_sds_controller *this_controller);
+
+void scic_sds_controller_assign_task_entries(
+ struct scic_sds_controller *this_controller);
+
+void scic_sds_controller_afe_initialization(
+ struct scic_sds_controller *this_controller);
+
+void scic_sds_controller_enable_port_task_scheduler(
+ struct scic_sds_controller *this_controller);
+
+void scic_sds_controller_initialize_completion_queue(
+ struct scic_sds_controller *this_controller);
+
+void scic_sds_controller_initialize_unsolicited_frame_queue(
+ struct scic_sds_controller *this_controller);
+
+void scic_sds_controller_phy_timer_stop(
+ struct scic_sds_controller *this_controller);
+
+enum sci_status scic_sds_controller_start_next_phy(
+ struct scic_sds_controller *this_controller);
+
+enum sci_status scic_sds_controller_stop_phys(
+ struct scic_sds_controller *this_controller);
+
+enum sci_status scic_sds_controller_stop_ports(
+ struct scic_sds_controller *this_controller);
+
+enum sci_status scic_sds_controller_stop_devices(
+ struct scic_sds_controller *this_controller);
+
+void scic_sds_controller_copy_task_context(
+ struct scic_sds_controller *this_controller,
+ struct scic_sds_request *this_request);
+
+void scic_sds_controller_timeout_handler(
+ struct scic_sds_controller *controller);
+
+void scic_sds_controller_initialize_power_control(
+ struct scic_sds_controller *this_controller);
+
+void scic_sds_controller_register_setup(
+ struct scic_sds_controller *this_controller);
+
+void scic_sds_controller_reset_hardware(
+ struct scic_sds_controller *this_controller);
+
+
+void scic_sds_controller_initialize_phy_startup(
+ struct scic_sds_controller *this_controller);
+
+#endif /* _SCIC_SDS_CONTROLLER_H_ */
diff --git a/drivers/scsi/isci/core/scic_sds_controller_registers.h b/drivers/scsi/isci/core/scic_sds_controller_registers.h
new file mode 100644
index 000000000000..b7bec92ee59c
--- /dev/null
+++ b/drivers/scsi/isci/core/scic_sds_controller_registers.h
@@ -0,0 +1,463 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCIC_SDS_CONTROLLER_REGISTERS_H_
+#define _SCIC_SDS_CONTROLLER_REGISTERS_H_
+
+/**
+ * This file contains macros used to perform the register reads/writes to the
+ * SCU hardware.
+ *
+ *
+ */
+
+#include "scu_registers.h"
+#include "scic_sds_controller.h"
+
+/**
+ * scic_sds_controller_smu_register_read() -
+ *
+ * SMU_REGISTER_ACCESS_MACROS
+ */
+#define scic_sds_controller_smu_register_read(controller, reg) \
+ smu_register_read(\
+ (controller), \
+ (controller)->smu_registers->reg \
+ )
+
+#define scic_sds_controller_smu_register_write(controller, reg, value) \
+ smu_register_write(\
+ (controller), \
+ (controller)->smu_registers->reg, \
+ (value) \
+ )
+
+/**
+ * scu_afe_register_write() -
+ *
+ * AFE_REGISTER_ACCESS_MACROS
+ */
+#define scu_afe_register_write(controller, reg, value) \
+ scu_register_write(\
+ (controller), \
+ (controller)->scu_registers->afe.reg, \
+ (value) \
+ )
+
+#define scu_afe_txreg_write(controller, phy, reg, value) \
+ scu_register_write(\
+ (controller), \
+ (controller)->scu_registers->afe.scu_afe_xcvr[phy].reg,\
+ (value) \
+ )
+
+#define scu_afe_register_read(controller, reg) \
+ scu_register_read(\
+ (controller), \
+ (controller)->scu_registers->afe.reg \
+ )
+
+/**
+ * scu_controller_viit_register_write() -
+ *
+ * VIIT_REGISTER_ACCESS_MACROS
+ */
+#define scu_controller_viit_register_write(controller, index, reg, value) \
+ scu_register_write(\
+ (controller), \
+ (controller)->scu_registers->peg0.viit[index].reg, \
+ value \
+ )
+
+/*
+ * *****************************************************************************
+ * * SMU REGISTERS
+ * ***************************************************************************** */
+
+/**
+ * SMU_PCP_WRITE() -
+ *
+ * struct smu_registers
+ */
+#define SMU_PCP_WRITE(controller, value) \
+ scic_sds_controller_smu_register_write(\
+ controller, post_context_port, value \
+ )
+
+#define SMU_TCR_READ(controller, value) \
+ scic_sds_controller_smu_register_read(\
+ controller, task_context_range \
+ )
+
+#define SMU_TCR_WRITE(controller, value) \
+ scic_sds_controller_smu_register_write(\
+ controller, task_context_range, value \
+ )
+
+#define SMU_HTTBAR_WRITE(controller, address) \
+ { \
+ scic_sds_controller_smu_register_write(\
+ controller, \
+ host_task_table_lower, \
+ lower_32_bits(address) \
+ ); \
+ scic_sds_controller_smu_register_write(\
+ controller, \
+ host_task_table_upper, \
+ upper_32_bits(address) \
+ ); \
+ }
+
+#define SMU_CQBAR_WRITE(controller, address) \
+ { \
+ scic_sds_controller_smu_register_write(\
+ controller, \
+ completion_queue_lower, \
+ lower_32_bits(address) \
+ ); \
+ scic_sds_controller_smu_register_write(\
+ controller, \
+ completion_queue_upper, \
+ upper_32_bits(address) \
+ ); \
+ }
+
+#define SMU_CQGR_WRITE(controller, value) \
+ scic_sds_controller_smu_register_write(\
+ controller, completion_queue_get, value \
+ )
+
+#define SMU_CQGR_READ(controller, value) \
+ scic_sds_controller_smu_register_read(\
+ controller, completion_queue_get \
+ )
+
+#define SMU_CQPR_WRITE(controller, value) \
+ scic_sds_controller_smu_register_write(\
+ controller, completion_queue_put, value \
+ )
+
+#define SMU_RNCBAR_WRITE(controller, address) \
+ { \
+ scic_sds_controller_smu_register_write(\
+ controller, \
+ remote_node_context_lower, \
+ lower_32_bits(address) \
+ ); \
+ scic_sds_controller_smu_register_write(\
+ controller, \
+ remote_node_context_upper, \
+ upper_32_bits(address) \
+ ); \
+ }
+
+#define SMU_AMR_READ(controller) \
+ scic_sds_controller_smu_register_read(\
+ controller, address_modifier \
+ )
+
+#define SMU_IMR_READ(controller) \
+ scic_sds_controller_smu_register_read(\
+ controller, interrupt_mask \
+ )
+
+#define SMU_IMR_WRITE(controller, mask) \
+ scic_sds_controller_smu_register_write(\
+ controller, interrupt_mask, mask \
+ )
+
+#define SMU_ISR_READ(controller) \
+ scic_sds_controller_smu_register_read(\
+ controller, interrupt_status \
+ )
+
+#define SMU_ISR_WRITE(controller, status) \
+ scic_sds_controller_smu_register_write(\
+ controller, interrupt_status, status \
+ )
+
+#define SMU_ICC_READ(controller) \
+ scic_sds_controller_smu_register_read(\
+ controller, interrupt_coalesce_control \
+ )
+
+#define SMU_ICC_WRITE(controller, value) \
+ scic_sds_controller_smu_register_write(\
+ controller, interrupt_coalesce_control, value \
+ )
+
+#define SMU_CQC_WRITE(controller, value) \
+ scic_sds_controller_smu_register_write(\
+ controller, completion_queue_control, value \
+ )
+
+#define SMU_SMUSRCR_WRITE(controller, value) \
+ scic_sds_controller_smu_register_write(\
+ controller, soft_reset_control, value \
+ )
+
+#define SMU_TCA_WRITE(controller, index, value) \
+ scic_sds_controller_smu_register_write(\
+ controller, task_context_assignment[index], value \
+ )
+
+#define SMU_TCA_READ(controller, index) \
+ scic_sds_controller_smu_register_read(\
+ controller, task_context_assignment[index] \
+ )
+
+#define SMU_DCC_READ(controller) \
+ scic_sds_controller_smu_register_read(\
+ controller, device_context_capacity \
+ )
+
+#define SMU_DFC_READ(controller) \
+ scic_sds_controller_smu_register_read(\
+ controller, device_function_capacity \
+ )
+
+#define SMU_SMUCSR_READ(controller) \
+ scic_sds_controller_smu_register_read(\
+ controller, control_status \
+ )
+
+#define SMU_CQPR_READ(controller) \
+ scic_sds_controller_smu_register_read(\
+ controller, completion_queue_put \
+ )
+
+
+/**
+ * scic_sds_controller_scu_register_read() -
+ *
+ * SCU_REGISTER_ACCESS_MACROS
+ */
+#define scic_sds_controller_scu_register_read(controller, reg) \
+ scu_register_read(\
+ (controller), \
+ (controller)->scu_registers->reg \
+ )
+
+#define scic_sds_controller_scu_register_write(controller, reg, value) \
+ scu_register_write(\
+ (controller), \
+ (controller)->scu_registers->reg, \
+ (value) \
+ )
+
+
+/*
+ * ****************************************************************************
+ * * SCU SDMA REGISTERS
+ * **************************************************************************** */
+
+/**
+ * scu_sdma_register_read() -
+ *
+ * SCU_SDMA_REGISTER_ACCESS_MACROS
+ */
+#define scu_sdma_register_read(controller, reg) \
+ scu_register_read(\
+ (controller), \
+ (controller)->scu_registers->sdma.reg \
+ )
+
+#define scu_sdma_register_write(controller, reg, value) \
+ scu_register_write(\
+ (controller), \
+ (controller)->scu_registers->sdma.reg, \
+ (value) \
+ )
+
+/**
+ * SCU_PUFATHAR_WRITE() -
+ *
+ * struct scu_sdma_registers
+ */
+#define SCU_PUFATHAR_WRITE(controller, address) \
+ { \
+ scu_sdma_register_write(\
+ controller, \
+ uf_address_table_lower, \
+ lower_32_bits(address) \
+ ); \
+ scu_sdma_register_write(\
+ controller, \
+ uf_address_table_upper, \
+ upper_32_bits(address) \
+ ); \
+ }
+
+#define SCU_UFHBAR_WRITE(controller, address) \
+ { \
+ scu_sdma_register_write(\
+ controller, \
+ uf_header_base_address_lower, \
+ lower_32_bits(address) \
+ ); \
+ scu_sdma_register_write(\
+ controller, \
+ uf_header_base_address_upper, \
+ upper_32_bits(address) \
+ ); \
+ }
+
+#define SCU_UFQC_READ(controller) \
+ scu_sdma_register_read(\
+ controller, \
+ unsolicited_frame_queue_control \
+ )
+
+#define SCU_UFQC_WRITE(controller, value) \
+ scu_sdma_register_write(\
+ controller, \
+ unsolicited_frame_queue_control, \
+ value \
+ )
+
+#define SCU_UFQPP_READ(controller) \
+ scu_sdma_register_read(\
+ controller, \
+ unsolicited_frame_put_pointer \
+ )
+
+#define SCU_UFQPP_WRITE(controller, value) \
+ scu_sdma_register_write(\
+ controller, \
+ unsolicited_frame_put_pointer, \
+ value \
+ )
+
+#define SCU_UFQGP_WRITE(controller, value) \
+ scu_sdma_register_write(\
+ controller, \
+ unsolicited_frame_get_pointer, \
+ value \
+ )
+
+#define SCU_PDMACR_READ(controller) \
+ scu_sdma_register_read(\
+ controller, \
+ pdma_configuration \
+ )
+
+#define SCU_PDMACR_WRITE(controller, value) \
+ scu_sdma_register_write(\
+ controller, \
+ pdma_configuration, \
+ value \
+ )
+
+#define SCU_CDMACR_READ(controller) \
+ scu_sdma_register_read(\
+ controller, \
+ cdma_configuration \
+ )
+
+#define SCU_CDMACR_WRITE(controller, value) \
+ scu_sdma_register_write(\
+ controller, \
+ cdma_configuration, \
+ value \
+ )
+
+/*
+ * *****************************************************************************
+ * * SCU Port Task Scheduler Group Registers
+ * ***************************************************************************** */
+
+/**
+ * scu_ptsg_register_read() -
+ *
+ * SCU_PTSG_REGISTER_ACCESS_MACROS
+ */
+#define scu_ptsg_register_read(controller, reg) \
+ scu_register_read(\
+ (controller), \
+ (controller)->scu_registers->peg0.ptsg.reg \
+ )
+
+#define scu_ptsg_register_write(controller, reg, value) \
+ scu_register_write(\
+ (controller), \
+ (controller)->scu_registers->peg0.ptsg.reg, \
+ (value) \
+ )
+
+/**
+ * SCU_PTSGCR_READ() -
+ *
+ * SCU_PTSG_REGISTERS
+ */
+#define SCU_PTSGCR_READ(controller) \
+ scu_ptsg_register_read(\
+ (controller), \
+ control \
+ )
+
+#define SCU_PTSGCR_WRITE(controller, value) \
+ scu_ptsg_register_write(\
+ (controller), \
+ control, \
+ value \
+ )
+
+#define SCU_PTSGRTC_READ(controller) \
+ scu_ptsg_register_read(\
+ contoller, \
+ real_time_clock \
+ )
+
+#endif /* _SCIC_SDS_CONTROLLER_REGISTERS_H_ */
diff --git a/drivers/scsi/isci/core/scic_sds_pci.h b/drivers/scsi/isci/core/scic_sds_pci.h
new file mode 100644
index 000000000000..21326777acc6
--- /dev/null
+++ b/drivers/scsi/isci/core/scic_sds_pci.h
@@ -0,0 +1,95 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCIC_SDS_PCI_H_
+#define _SCIC_SDS_PCI_H_
+
+/**
+ * This file contains the prototypes/macros utilized in writing out PCI data
+ * for the SCI core.
+ *
+ *
+ */
+
+#include <asm/io.h>
+#include "sci_types.h"
+
+struct scic_sds_controller;
+
+void scic_sds_pci_bar_initialization(struct scic_sds_controller *scic);
+
+/* for debug we separate scu and smu accesses and require a controller */
+static inline u32 scic_sds_pci_read_smu_dword(struct scic_sds_controller *scic, void __iomem *addr)
+{
+ return readl(addr);
+}
+
+static inline void scic_sds_pci_write_smu_dword(struct scic_sds_controller *scic, void __iomem *addr, u32 value)
+{
+ writel(value, addr);
+}
+
+static inline u32 scic_sds_pci_read_scu_dword(struct scic_sds_controller *scic, void __iomem *addr)
+{
+ return readl(addr);
+}
+
+static inline void scic_sds_pci_write_scu_dword(struct scic_sds_controller *scic, void __iomem *addr, u32 value)
+{
+ writel(value, addr);
+}
+
+
+#endif /* _SCIC_SDS_PCI_H_ */
diff --git a/drivers/scsi/isci/core/scic_sds_phy.c b/drivers/scsi/isci/core/scic_sds_phy.c
new file mode 100644
index 000000000000..7d012b571b5b
--- /dev/null
+++ b/drivers/scsi/isci/core/scic_sds_phy.c
@@ -0,0 +1,2807 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "intel_ata.h"
+#include "intel_sata.h"
+#include "sci_base_state.h"
+#include "sci_base_state_machine.h"
+#include "scic_phy.h"
+#include "scic_sds_controller.h"
+#include "scic_sds_phy.h"
+#include "scic_sds_phy_registers.h"
+#include "scic_sds_port.h"
+#include "scic_user_callback.h"
+#include "sci_environment.h"
+#include "sci_util.h"
+#include "scu_event_codes.h"
+
+#define SCIC_SDS_PHY_MIN_TIMER_COUNT (SCI_MAX_PHYS)
+#define SCIC_SDS_PHY_MAX_TIMER_COUNT (SCI_MAX_PHYS)
+
+/* Maximum arbitration wait time in micro-seconds */
+#define SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME (700)
+
+/*
+ * *****************************************************************************
+ * * SCIC SDS PHY Internal Methods
+ * ***************************************************************************** */
+
+/**
+ * This method will initialize the phy link layer registers
+ * @this_phy:
+ * @link_layer_registers:
+ *
+ * enum sci_status
+ */
+static enum sci_status scic_sds_phy_link_layer_initialization(
+ struct scic_sds_phy *this_phy,
+ struct scu_link_layer_registers *link_layer_registers)
+{
+ u32 phy_configuration;
+ struct sas_capabilities phy_capabilities;
+ u32 parity_check = 0;
+ u32 parity_count = 0;
+ u32 link_layer_control;
+
+ this_phy->link_layer_registers = link_layer_registers;
+
+ /* Set our IDENTIFY frame data */
+ #define SCI_END_DEVICE 0x01
+
+ SCU_SAS_TIID_WRITE(
+ this_phy,
+ (SCU_SAS_TIID_GEN_BIT(SMP_INITIATOR)
+ | SCU_SAS_TIID_GEN_BIT(SSP_INITIATOR)
+ | SCU_SAS_TIID_GEN_BIT(STP_INITIATOR)
+ | SCU_SAS_TIID_GEN_BIT(DA_SATA_HOST)
+ | SCU_SAS_TIID_GEN_VAL(DEVICE_TYPE, SCI_END_DEVICE))
+ );
+
+ /* Write the device SAS Address */
+ SCU_SAS_TIDNH_WRITE(this_phy, 0xFEDCBA98);
+ SCU_SAS_TIDNL_WRITE(this_phy, this_phy->phy_index);
+
+ /* Write the source SAS Address */
+ SCU_SAS_TISSAH_WRITE(
+ this_phy,
+ this_phy->owning_port->owning_controller->oem_parameters.sds1.phys[
+ this_phy->phy_index].sas_address.high
+ );
+ SCU_SAS_TISSAL_WRITE(
+ this_phy,
+ this_phy->owning_port->owning_controller->oem_parameters.sds1.phys[
+ this_phy->phy_index].sas_address.low
+ );
+
+ /* Clear and Set the PHY Identifier */
+ SCU_SAS_TIPID_WRITE(this_phy, 0x00000000);
+ SCU_SAS_TIPID_WRITE(this_phy, SCU_SAS_TIPID_GEN_VALUE(ID, this_phy->phy_index));
+
+ /* Change the initial state of the phy configuration register */
+ phy_configuration = SCU_SAS_PCFG_READ(this_phy);
+
+ /* Hold OOB state machine in reset */
+ phy_configuration |= SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
+ SCU_SAS_PCFG_WRITE(this_phy, phy_configuration);
+
+ /* Configure the SNW capabilities */
+ phy_capabilities.u.all = 0;
+ phy_capabilities.u.bits.start = 1;
+ phy_capabilities.u.bits.gen3_without_ssc_supported = 1;
+ phy_capabilities.u.bits.gen2_without_ssc_supported = 1;
+ phy_capabilities.u.bits.gen1_without_ssc_supported = 1;
+ if (this_phy->owning_port->owning_controller->oem_parameters.sds1.
+ controller.do_enable_ssc == true) {
+ phy_capabilities.u.bits.gen3_with_ssc_supported = 1;
+ phy_capabilities.u.bits.gen2_with_ssc_supported = 1;
+ phy_capabilities.u.bits.gen1_with_ssc_supported = 1;
+ }
+
+ /*
+ * The SAS specification indicates that the phy_capabilities that
+ * are transmitted shall have an even parity. Calculate the parity. */
+ parity_check = phy_capabilities.u.all;
+ while (parity_check != 0) {
+ if (parity_check & 0x1)
+ parity_count++;
+ parity_check >>= 1;
+ }
+
+ /*
+ * If parity indicates there are an odd number of bits set, then
+ * set the parity bit to 1 in the phy capabilities. */
+ if ((parity_count % 2) != 0)
+ phy_capabilities.u.bits.parity = 1;
+
+ SCU_SAS_PHYCAP_WRITE(this_phy, phy_capabilities.u.all);
+
+ /* Set the enable spinup period but disable the ability to send notify enable spinup */
+ SCU_SAS_ENSPINUP_WRITE(this_phy, SCU_ENSPINUP_GEN_VAL(COUNT, 0x33));
+
+#if defined(CONFIG_PBG_HBA_A0) || defined(CONFIG_PBG_HBA_A2) || defined(CONFIG_PBG_HBA_BETA)
+ /* / @todo Provide a way to write this register correctly */
+ scu_link_layer_register_write(this_phy, afe_lookup_table_control, 0x02108421);
+#else
+ /* / @todo Provide a way to write this register correctly */
+ scu_link_layer_register_write(this_phy, afe_lookup_table_control, 0x0e739ce7);
+#endif
+
+ link_layer_control = SCU_SAS_LLCTL_GEN_VAL(
+ NO_OUTBOUND_TASK_TIMEOUT,
+ (u8)this_phy->owning_port->owning_controller->
+ user_parameters.sds1.no_outbound_task_timeout
+ );
+
+/* #define COMPILED_MAX_LINK_RATE SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1 */
+/* #define COMPILED_MAX_LINK_RATE SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2 */
+#define COMPILED_MAX_LINK_RATE SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3
+
+ if (this_phy->owning_port->owning_controller->user_parameters.sds1.
+ phys[this_phy->phy_index].max_speed_generation == SCIC_SDS_PARM_GEN3_SPEED) {
+ link_layer_control |= SCU_SAS_LLCTL_GEN_VAL(
+ MAX_LINK_RATE, COMPILED_MAX_LINK_RATE
+ );
+ } else if (this_phy->owning_port->owning_controller->user_parameters.sds1.
+ phys[this_phy->phy_index].max_speed_generation == SCIC_SDS_PARM_GEN2_SPEED) {
+ link_layer_control |= SCU_SAS_LLCTL_GEN_VAL(
+ MAX_LINK_RATE,
+ min(
+ SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2,
+ COMPILED_MAX_LINK_RATE)
+ );
+ } else {
+ link_layer_control |= SCU_SAS_LLCTL_GEN_VAL(
+ MAX_LINK_RATE,
+ min(
+ SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1,
+ COMPILED_MAX_LINK_RATE)
+ );
+ }
+
+ scu_link_layer_register_write(
+ this_phy, link_layer_control, link_layer_control
+ );
+
+ /*
+ * Program the max ARB time for the PHY to 700us so we inter-operate with
+ * the PMC expander which shuts down PHYs if the expander PHY generates too
+ * many breaks. This time value will guarantee that the initiator PHY will
+ * generate the break. */
+#if defined(CONFIG_PBG_HBA_A0) || defined(CONFIG_PBG_HBA_A2)
+ scu_link_layer_register_write(
+ this_phy,
+ maximum_arbitration_wait_timer_timeout,
+ SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME
+ );
+#endif /* defined(CONFIG_PBG_HBA_A0) || defined(CONFIG_PBG_HBA_A2) */
+
+ /*
+ * Set the link layer hang detection to 500ms (0x1F4) from its default
+ * value of 128ms. Max value is 511 ms. */
+ scu_link_layer_register_write(
+ this_phy, link_layer_hang_detection_timeout, 0x1F4
+ );
+
+ /* We can exit the initial state to the stopped state */
+ sci_base_state_machine_change_state(
+ scic_sds_phy_get_base_state_machine(this_phy),
+ SCI_BASE_PHY_STATE_STOPPED
+ );
+
+ return SCI_SUCCESS;
+}
+
+/**
+ * This function will handle the sata SIGNATURE FIS timeout condition. It will
+ * restart the starting substate machine since we dont know what has actually
+ * happening.
+ */
+static void scic_sds_phy_sata_timeout(void *phy)
+{
+ struct scic_sds_phy *sci_phy = phy;
+
+ dev_dbg(sciphy_to_dev(sci_phy),
+ "%s: SCIC SDS Phy 0x%p did not receive signature fis before "
+ "timeout.\n",
+ __func__,
+ sci_phy);
+
+ sci_base_state_machine_stop(
+ scic_sds_phy_get_starting_substate_machine(sci_phy));
+
+ sci_base_state_machine_change_state(
+ scic_sds_phy_get_base_state_machine(sci_phy),
+ SCI_BASE_PHY_STATE_STARTING
+ );
+}
+
+/*
+ * *****************************************************************************
+ * * SCIC SDS PHY External Methods
+ * ***************************************************************************** */
+
+/**
+ * This method returns the object size for a phy object.
+ *
+ * u32
+ */
+
+/**
+ * This method returns the minimum number of timers required for a phy object.
+ *
+ * u32
+ */
+
+/**
+ * This method returns the maximum number of timers required for a phy object.
+ *
+ * u32
+ */
+
+#ifdef SCIC_DEBUG_ENABLED
+/**
+ * scic_sds_phy_observe_state_change() -
+ * @our_observer:
+ *
+ * Debug code to record the state transitions in the phy
+ */
+void scic_sds_phy_observe_state_change(
+ struct sci_base_observer *our_observer,
+ struct sci_base_subject *the_subject)
+{
+ struct scic_sds_phy *this_phy;
+ struct sci_base_state_machine *the_state_machine;
+
+ u8 transition_requestor;
+ u32 base_state_id;
+ u32 starting_substate_id;
+
+ the_state_machine = (struct sci_base_state_machine *)the_subject;
+ this_phy = (struct scic_sds_phy *)the_state_machine->state_machine_owner;
+
+ if (the_state_machine == &this_phy->parent.state_machine) {
+ transition_requestor = 0x01;
+ } else if (the_state_machine == &this_phy->starting_substate_machine) {
+ transition_requestor = 0x02;
+ } else {
+ transition_requestor = 0xFF;
+ }
+
+ base_state_id =
+ sci_base_state_machine_get_state(&this_phy->parent.state_machine);
+ starting_substate_id =
+ sci_base_state_machine_get_state(&this_phy->starting_substate_machine);
+
+ this_phy->state_record.state_transition_table[
+ this_phy->state_record.index++] = ((transition_requestor << 24)
+ | ((u8)base_state_id << 8)
+ | ((u8)starting_substate_id));
+
+ this_phy->state_record.index =
+ this_phy->state_record.index & (MAX_STATE_TRANSITION_RECORD - 1);
+
+}
+#endif /* SCIC_DEBUG_ENABLED */
+
+#ifdef SCIC_DEBUG_ENABLED
+/**
+ * scic_sds_phy_initialize_state_recording() -
+ *
+ * This method initializes the state record debug information for the phy
+ * object. The state machines for the phy object must be constructed before
+ * this function is called.
+ */
+void scic_sds_phy_initialize_state_recording(
+ struct scic_sds_phy *this_phy)
+{
+ this_phy->state_record.index = 0;
+
+ sci_base_observer_initialize(
+ &this_phy->state_record.base_state_observer,
+ scic_sds_phy_observe_state_change,
+ &this_phy->parent.state_machine.parent
+ );
+
+ sci_base_observer_initialize(
+ &this_phy->state_record.starting_state_observer,
+ scic_sds_phy_observe_state_change,
+ &this_phy->starting_substate_machine.parent
+ );
+}
+#endif /* SCIC_DEBUG_ENABLED */
+
+/**
+ * This method will construct the struct scic_sds_phy object
+ * @this_phy:
+ * @owning_port:
+ * @phy_index:
+ *
+ */
+void scic_sds_phy_construct(
+ struct scic_sds_phy *this_phy,
+ struct scic_sds_port *owning_port,
+ u8 phy_index)
+{
+ /*
+ * Call the base constructor first
+ */
+ sci_base_phy_construct(
+ &this_phy->parent,
+ scic_sds_phy_state_table
+ );
+
+ /* Copy the rest of the input data to our locals */
+ this_phy->owning_port = owning_port;
+ this_phy->phy_index = phy_index;
+ this_phy->bcn_received_while_port_unassigned = false;
+ this_phy->protocol = SCIC_SDS_PHY_PROTOCOL_UNKNOWN;
+ this_phy->link_layer_registers = NULL;
+ this_phy->max_negotiated_speed = SCI_SAS_NO_LINK_RATE;
+
+ /* Clear out the identification buffer data */
+ memset(&this_phy->phy_type, 0, sizeof(this_phy->phy_type));
+
+ /* Initialize the the substate machines */
+ sci_base_state_machine_construct(
+ &this_phy->starting_substate_machine,
+ &this_phy->parent.parent,
+ scic_sds_phy_starting_substates,
+ SCIC_SDS_PHY_STARTING_SUBSTATE_INITIAL
+ );
+
+ #ifdef SCIC_DEBUG_ENABLED
+ scic_sds_phy_initialize_state_recording(this_phy);
+ #endif /* SCIC_DEBUG_ENABLED */
+}
+
+/**
+ * This method returns the port currently containing this phy. If the phy is
+ * currently contained by the dummy port, then the phy is considered to not
+ * be part of a port.
+ * @this_phy: This parameter specifies the phy for which to retrieve the
+ * containing port.
+ *
+ * This method returns a handle to a port that contains the supplied phy.
+ * SCI_INVALID_HANDLE This value is returned if the phy is not part of a real
+ * port (i.e. it's contained in the dummy port). !SCI_INVALID_HANDLE All other
+ * values indicate a handle/pointer to the port containing the phy.
+ */
+struct scic_sds_port *scic_sds_phy_get_port(
+ struct scic_sds_phy *this_phy)
+{
+ if (scic_sds_port_get_index(this_phy->owning_port) == SCIC_SDS_DUMMY_PORT)
+ return SCI_INVALID_HANDLE;
+
+ return this_phy->owning_port;
+}
+
+/**
+ * This method will assign a port to the phy object.
+ * @out]: this_phy This parameter specifies the phy for which to assign a port
+ * object.
+ *
+ *
+ */
+void scic_sds_phy_set_port(
+ struct scic_sds_phy *this_phy,
+ struct scic_sds_port *the_port)
+{
+ this_phy->owning_port = the_port;
+
+ if (this_phy->bcn_received_while_port_unassigned) {
+ this_phy->bcn_received_while_port_unassigned = false;
+ scic_sds_port_broadcast_change_received(this_phy->owning_port, this_phy);
+ }
+}
+
+/**
+ * This method will initialize the constructed phy
+ * @sci_phy:
+ * @link_layer_registers:
+ *
+ * enum sci_status
+ */
+enum sci_status scic_sds_phy_initialize(
+ struct scic_sds_phy *sci_phy,
+ struct scu_link_layer_registers *link_layer_registers)
+{
+ /* Create the SIGNATURE FIS Timeout timer for this phy */
+ sci_phy->sata_timeout_timer = scic_cb_timer_create(
+ scic_sds_phy_get_controller(sci_phy),
+ scic_sds_phy_sata_timeout,
+ sci_phy
+ );
+
+ /* Perofrm the initialization of the PE hardware */
+ scic_sds_phy_link_layer_initialization(sci_phy, link_layer_registers);
+
+ /*
+ * There is nothing that needs to be done in this state just
+ * transition to the stopped state. */
+ sci_base_state_machine_change_state(
+ scic_sds_phy_get_base_state_machine(sci_phy),
+ SCI_BASE_PHY_STATE_STOPPED
+ );
+
+ return SCI_SUCCESS;
+}
+
+
+/**
+ *
+ * @this_phy: The phy object to be suspended.
+ *
+ * This function will perform the register reads/writes to suspend the SCU
+ * hardware protocol engine. none
+ */
+void scic_sds_phy_suspend(
+ struct scic_sds_phy *this_phy)
+{
+ u32 scu_sas_pcfg_value;
+
+ scu_sas_pcfg_value = SCU_SAS_PCFG_READ(this_phy);
+
+ scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE);
+
+ SCU_SAS_PCFG_WRITE(this_phy, scu_sas_pcfg_value);
+}
+
+/**
+ *
+ * @this_phy: The phy object to resume.
+ *
+ * This function will perform the register reads/writes required to resume the
+ * SCU hardware protocol engine. none
+ */
+void scic_sds_phy_resume(
+ struct scic_sds_phy *this_phy)
+{
+ u32 scu_sas_pcfg_value;
+
+ scu_sas_pcfg_value = SCU_SAS_PCFG_READ(this_phy);
+
+ scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE);
+
+ SCU_SAS_PCFG_WRITE(this_phy, scu_sas_pcfg_value);
+}
+
+/**
+ * This method returns the local sas address assigned to this phy.
+ * @this_phy: This parameter specifies the phy for which to retrieve the local
+ * SAS address.
+ * @sas_address: This parameter specifies the location into which to copy the
+ * local SAS address.
+ *
+ */
+void scic_sds_phy_get_sas_address(
+ struct scic_sds_phy *this_phy,
+ struct sci_sas_address *sas_address)
+{
+ sas_address->high = SCU_SAS_TISSAH_READ(this_phy);
+ sas_address->low = SCU_SAS_TISSAL_READ(this_phy);
+}
+
+/**
+ * This method returns the remote end-point (i.e. attached) sas address
+ * assigned to this phy.
+ * @this_phy: This parameter specifies the phy for which to retrieve the remote
+ * end-point SAS address.
+ * @sas_address: This parameter specifies the location into which to copy the
+ * remote end-point SAS address.
+ *
+ */
+void scic_sds_phy_get_attached_sas_address(
+ struct scic_sds_phy *this_phy,
+ struct sci_sas_address *sas_address)
+{
+ sas_address->high
+ = this_phy->phy_type.sas.identify_address_frame_buffer.sas_address.high;
+ sas_address->low
+ = this_phy->phy_type.sas.identify_address_frame_buffer.sas_address.low;
+}
+
+/**
+ * This method returns the supported protocols assigned to this phy
+ * @this_phy:
+ *
+ *
+ */
+void scic_sds_phy_get_protocols(
+ struct scic_sds_phy *this_phy,
+ struct sci_sas_identify_address_frame_protocols *protocols)
+{
+ protocols->u.all = (u16)(SCU_SAS_TIID_READ(this_phy) & 0x0000FFFF);
+}
+
+/**
+ *
+ * @this_phy: The parameter is the phy object for which the attached phy
+ * protcols are to be returned.
+ *
+ * This method returns the supported protocols for the attached phy. If this
+ * is a SAS phy the protocols are returned from the identify address frame. If
+ * this is a SATA phy then protocols are made up and the target phy is an STP
+ * target phy. The caller will get the entire set of bits for the protocol
+ * value.
+ */
+void scic_sds_phy_get_attached_phy_protocols(
+ struct scic_sds_phy *this_phy,
+ struct sci_sas_identify_address_frame_protocols *protocols)
+{
+ protocols->u.all = 0;
+
+ if (this_phy->protocol == SCIC_SDS_PHY_PROTOCOL_SAS) {
+ protocols->u.all =
+ this_phy->phy_type.sas.identify_address_frame_buffer.protocols.u.all;
+ } else if (this_phy->protocol == SCIC_SDS_PHY_PROTOCOL_SATA) {
+ protocols->u.bits.stp_target = 1;
+ }
+}
+
+/*
+ * *****************************************************************************
+ * * SCIC SDS PHY Handler Redirects
+ * ***************************************************************************** */
+
+/**
+ * This method will attempt to start the phy object. This request is only valid
+ * when the phy is in the stopped state
+ * @this_phy:
+ *
+ * enum sci_status
+ */
+enum sci_status scic_sds_phy_start(
+ struct scic_sds_phy *this_phy)
+{
+ return this_phy->state_handlers->parent.start_handler(&this_phy->parent);
+}
+
+/**
+ * This method will attempt to stop the phy object.
+ * @this_phy:
+ *
+ * enum sci_status SCI_SUCCESS if the phy is going to stop SCI_INVALID_STATE if the
+ * phy is not in a valid state to stop
+ */
+enum sci_status scic_sds_phy_stop(
+ struct scic_sds_phy *this_phy)
+{
+ return this_phy->state_handlers->parent.stop_handler(&this_phy->parent);
+}
+
+/**
+ * This method will attempt to reset the phy. This request is only valid when
+ * the phy is in an ready state
+ * @this_phy:
+ *
+ * enum sci_status
+ */
+enum sci_status scic_sds_phy_reset(
+ struct scic_sds_phy *this_phy)
+{
+ return this_phy->state_handlers->parent.reset_handler(
+ &this_phy->parent
+ );
+}
+
+/**
+ * This method will process the event code received.
+ * @this_phy:
+ * @event_code:
+ *
+ * enum sci_status
+ */
+enum sci_status scic_sds_phy_event_handler(
+ struct scic_sds_phy *this_phy,
+ u32 event_code)
+{
+ return this_phy->state_handlers->event_handler(this_phy, event_code);
+}
+
+/**
+ * This method will process the frame index received.
+ * @this_phy:
+ * @frame_index:
+ *
+ * enum sci_status
+ */
+enum sci_status scic_sds_phy_frame_handler(
+ struct scic_sds_phy *this_phy,
+ u32 frame_index)
+{
+ return this_phy->state_handlers->frame_handler(this_phy, frame_index);
+}
+
+/**
+ * This method will give the phy permission to consume power
+ * @this_phy:
+ *
+ * enum sci_status
+ */
+enum sci_status scic_sds_phy_consume_power_handler(
+ struct scic_sds_phy *this_phy)
+{
+ return this_phy->state_handlers->consume_power_handler(this_phy);
+}
+
+/*
+ * *****************************************************************************
+ * * SCIC PHY Public Methods
+ * ***************************************************************************** */
+
+
+enum sci_status scic_sas_phy_get_properties(
+ struct scic_sds_phy *sci_phy,
+ struct scic_sas_phy_properties *properties)
+{
+ if (sci_phy->protocol == SCIC_SDS_PHY_PROTOCOL_SAS) {
+ memcpy(
+ &properties->received_iaf,
+ &sci_phy->phy_type.sas.identify_address_frame_buffer,
+ sizeof(struct sci_sas_identify_address_frame)
+ );
+
+ properties->received_capabilities.u.all
+ = SCU_SAS_RECPHYCAP_READ(sci_phy);
+
+ return SCI_SUCCESS;
+ }
+
+ return SCI_FAILURE;
+}
+
+
+enum sci_status scic_sata_phy_get_properties(
+ struct scic_sds_phy *sci_phy,
+ struct scic_sata_phy_properties *properties)
+{
+ if (sci_phy->protocol == SCIC_SDS_PHY_PROTOCOL_SATA) {
+ memcpy(
+ &properties->signature_fis,
+ &sci_phy->phy_type.sata.signature_fis_buffer,
+ sizeof(struct sata_fis_reg_d2h)
+ );
+
+ /* / @todo add support for port selectors. */
+ properties->is_port_selector_present = false;
+
+ return SCI_SUCCESS;
+ }
+
+ return SCI_FAILURE;
+}
+
+/*
+ * *****************************************************************************
+ * * SCIC SDS PHY HELPER FUNCTIONS
+ * ***************************************************************************** */
+
+
+/**
+ *
+ * @this_phy: The phy object that received SAS PHY DETECTED.
+ *
+ * This method continues the link training for the phy as if it were a SAS PHY
+ * instead of a SATA PHY. This is done because the completion queue had a SAS
+ * PHY DETECTED event when the state machine was expecting a SATA PHY event.
+ * none
+ */
+static void scic_sds_phy_start_sas_link_training(
+ struct scic_sds_phy *this_phy)
+{
+ u32 phy_control;
+
+ phy_control = SCU_SAS_PCFG_READ(this_phy);
+ phy_control |= SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD);
+ SCU_SAS_PCFG_WRITE(this_phy, phy_control);
+
+ sci_base_state_machine_change_state(
+ &this_phy->starting_substate_machine,
+ SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_SPEED_EN
+ );
+
+ this_phy->protocol = SCIC_SDS_PHY_PROTOCOL_SAS;
+}
+
+/**
+ *
+ * @this_phy: The phy object that received a SATA SPINUP HOLD event
+ *
+ * This method continues the link training for the phy as if it were a SATA PHY
+ * instead of a SAS PHY. This is done because the completion queue had a SATA
+ * SPINUP HOLD event when the state machine was expecting a SAS PHY event. none
+ */
+static void scic_sds_phy_start_sata_link_training(
+ struct scic_sds_phy *this_phy)
+{
+ sci_base_state_machine_change_state(
+ &this_phy->starting_substate_machine,
+ SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_POWER
+ );
+
+ this_phy->protocol = SCIC_SDS_PHY_PROTOCOL_SATA;
+}
+
+/**
+ * This method performs processing common to all protocols upon completion of
+ * link training.
+ * @this_phy: This parameter specifies the phy object for which link training
+ * has completed.
+ * @max_link_rate: This parameter specifies the maximum link rate to be
+ * associated with this phy.
+ * @next_state: This parameter specifies the next state for the phy's starting
+ * sub-state machine.
+ *
+ */
+static void scic_sds_phy_complete_link_training(
+ struct scic_sds_phy *this_phy,
+ enum sci_sas_link_rate max_link_rate,
+ u32 next_state)
+{
+ this_phy->max_negotiated_speed = max_link_rate;
+
+ sci_base_state_machine_change_state(
+ scic_sds_phy_get_starting_substate_machine(this_phy), next_state
+ );
+}
+
+/**
+ *
+ * @this_phy: The struct scic_sds_phy object to restart.
+ *
+ * This method restarts the struct scic_sds_phy objects base state machine in the
+ * starting state from any starting substate. none
+ */
+static void scic_sds_phy_restart_starting_state(
+ struct scic_sds_phy *this_phy)
+{
+ /* Stop the current substate machine */
+ sci_base_state_machine_stop(
+ scic_sds_phy_get_starting_substate_machine(this_phy)
+ );
+
+ /* Re-enter the base state machine starting state */
+ sci_base_state_machine_change_state(
+ scic_sds_phy_get_base_state_machine(this_phy),
+ SCI_BASE_PHY_STATE_STARTING
+ );
+}
+
+/*
+ * *****************************************************************************
+ * * SCIC SDS PHY EVENT_HANDLERS
+ * ***************************************************************************** */
+
+/**
+ *
+ * @phy: This struct scic_sds_phy object which has received an event.
+ * @event_code: This is the event code which the phy object is to decode.
+ *
+ * This method is called when an event notification is received for the phy
+ * object when in the state SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SPEED_EN. -
+ * decode the event - sas phy detected causes a state transition to the wait
+ * for speed event notification. - any other events log a warning message and
+ * set a failure status enum sci_status SCI_SUCCESS on any valid event notification
+ * SCI_FAILURE on any unexpected event notifation
+ */
+static enum sci_status scic_sds_phy_starting_substate_await_ossp_event_handler(
+ struct scic_sds_phy *this_phy,
+ u32 event_code)
+{
+ u32 result = SCI_SUCCESS;
+
+ switch (scu_get_event_code(event_code)) {
+ case SCU_EVENT_SAS_PHY_DETECTED:
+ scic_sds_phy_start_sas_link_training(this_phy);
+ this_phy->is_in_link_training = true;
+ break;
+
+ case SCU_EVENT_SATA_SPINUP_HOLD:
+ scic_sds_phy_start_sata_link_training(this_phy);
+ this_phy->is_in_link_training = true;
+ break;
+
+ default:
+ dev_warn(sciphy_to_dev(this_phy),
+ "%s: PHY starting substate machine received "
+ "unexpected event_code %x\n",
+ __func__,
+ event_code);
+
+ result = SCI_FAILURE;
+ break;
+ }
+
+ return result;
+}
+
+/**
+ *
+ * @phy: This struct scic_sds_phy object which has received an event.
+ * @event_code: This is the event code which the phy object is to decode.
+ *
+ * This method is called when an event notification is received for the phy
+ * object when in the state SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SPEED_EN. -
+ * decode the event - sas phy detected returns us back to this state. - speed
+ * event detected causes a state transition to the wait for iaf. - identify
+ * timeout is an un-expected event and the state machine is restarted. - link
+ * failure events restart the starting state machine - any other events log a
+ * warning message and set a failure status enum sci_status SCI_SUCCESS on any valid
+ * event notification SCI_FAILURE on any unexpected event notifation
+ */
+static enum sci_status scic_sds_phy_starting_substate_await_sas_phy_speed_event_handler(
+ struct scic_sds_phy *this_phy,
+ u32 event_code)
+{
+ u32 result = SCI_SUCCESS;
+
+ switch (scu_get_event_code(event_code)) {
+ case SCU_EVENT_SAS_PHY_DETECTED:
+ /*
+ * Why is this being reported again by the controller?
+ * We would re-enter this state so just stay here */
+ break;
+
+ case SCU_EVENT_SAS_15:
+ case SCU_EVENT_SAS_15_SSC:
+ scic_sds_phy_complete_link_training(
+ this_phy, SCI_SAS_150_GB, SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_IAF_UF
+ );
+ break;
+
+ case SCU_EVENT_SAS_30:
+ case SCU_EVENT_SAS_30_SSC:
+ scic_sds_phy_complete_link_training(
+ this_phy, SCI_SAS_300_GB, SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_IAF_UF
+ );
+ break;
+
+ case SCU_EVENT_SAS_60:
+ case SCU_EVENT_SAS_60_SSC:
+ scic_sds_phy_complete_link_training(
+ this_phy, SCI_SAS_600_GB, SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_IAF_UF
+ );
+ break;
+
+ case SCU_EVENT_SATA_SPINUP_HOLD:
+ /*
+ * We were doing SAS PHY link training and received a SATA PHY event
+ * continue OOB/SN as if this were a SATA PHY */
+ scic_sds_phy_start_sata_link_training(this_phy);
+ break;
+
+ case SCU_EVENT_LINK_FAILURE:
+ /* Link failure change state back to the starting state */
+ scic_sds_phy_restart_starting_state(this_phy);
+ break;
+
+ default:
+ dev_warn(sciphy_to_dev(this_phy),
+ "%s: PHY starting substate machine received "
+ "unexpected event_code %x\n",
+ __func__,
+ event_code);
+
+ result = SCI_FAILURE;
+ break;
+ }
+
+ return result;
+}
+
+/**
+ *
+ * @phy: This struct scic_sds_phy object which has received an event.
+ * @event_code: This is the event code which the phy object is to decode.
+ *
+ * This method is called when an event notification is received for the phy
+ * object when in the state SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_IAF_UF. -
+ * decode the event - sas phy detected event backs up the state machine to the
+ * await speed notification. - identify timeout is an un-expected event and the
+ * state machine is restarted. - link failure events restart the starting state
+ * machine - any other events log a warning message and set a failure status
+ * enum sci_status SCI_SUCCESS on any valid event notification SCI_FAILURE on any
+ * unexpected event notifation
+ */
+static enum sci_status scic_sds_phy_starting_substate_await_iaf_uf_event_handler(
+ struct scic_sds_phy *this_phy,
+ u32 event_code)
+{
+ u32 result = SCI_SUCCESS;
+
+ switch (scu_get_event_code(event_code)) {
+ case SCU_EVENT_SAS_PHY_DETECTED:
+ /* Backup the state machine */
+ scic_sds_phy_start_sas_link_training(this_phy);
+ break;
+
+ case SCU_EVENT_SATA_SPINUP_HOLD:
+ /*
+ * We were doing SAS PHY link training and received a SATA PHY event
+ * continue OOB/SN as if this were a SATA PHY */
+ scic_sds_phy_start_sata_link_training(this_phy);
+ break;
+
+ case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT:
+ case SCU_EVENT_LINK_FAILURE:
+ case SCU_EVENT_HARD_RESET_RECEIVED:
+ /* Start the oob/sn state machine over again */
+ scic_sds_phy_restart_starting_state(this_phy);
+ break;
+
+ default:
+ dev_warn(sciphy_to_dev(this_phy),
+ "%s: PHY starting substate machine received "
+ "unexpected event_code %x\n",
+ __func__,
+ event_code);
+
+ result = SCI_FAILURE;
+ break;
+ }
+
+ return result;
+}
+
+/**
+ *
+ * @phy: This struct scic_sds_phy object which has received an event.
+ * @event_code: This is the event code which the phy object is to decode.
+ *
+ * This method is called when an event notification is received for the phy
+ * object when in the state SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_POWER. -
+ * decode the event - link failure events restart the starting state machine -
+ * any other events log a warning message and set a failure status enum sci_status
+ * SCI_SUCCESS on a link failure event SCI_FAILURE on any unexpected event
+ * notifation
+ */
+static enum sci_status scic_sds_phy_starting_substate_await_sas_power_event_handler(
+ struct scic_sds_phy *this_phy,
+ u32 event_code)
+{
+ u32 result = SCI_SUCCESS;
+
+ switch (scu_get_event_code(event_code)) {
+ case SCU_EVENT_LINK_FAILURE:
+ /* Link failure change state back to the starting state */
+ scic_sds_phy_restart_starting_state(this_phy);
+ break;
+
+ default:
+ dev_warn(sciphy_to_dev(this_phy),
+ "%s: PHY starting substate machine received unexpected "
+ "event_code %x\n",
+ __func__,
+ event_code);
+
+ result = SCI_FAILURE;
+ break;
+ }
+
+ return result;
+}
+
+/**
+ *
+ * @phy: This struct scic_sds_phy object which has received an event.
+ * @event_code: This is the event code which the phy object is to decode.
+ *
+ * This method is called when an event notification is received for the phy
+ * object when in the state SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_POWER. -
+ * decode the event - link failure events restart the starting state machine -
+ * sata spinup hold events are ignored since they are expected - any other
+ * events log a warning message and set a failure status enum sci_status SCI_SUCCESS
+ * on a link failure event SCI_FAILURE on any unexpected event notifation
+ */
+static enum sci_status scic_sds_phy_starting_substate_await_sata_power_event_handler(
+ struct scic_sds_phy *this_phy,
+ u32 event_code)
+{
+ u32 result = SCI_SUCCESS;
+
+ switch (scu_get_event_code(event_code)) {
+ case SCU_EVENT_LINK_FAILURE:
+ /* Link failure change state back to the starting state */
+ scic_sds_phy_restart_starting_state(this_phy);
+ break;
+
+ case SCU_EVENT_SATA_SPINUP_HOLD:
+ /* These events are received every 10ms and are expected while in this state */
+ break;
+
+ case SCU_EVENT_SAS_PHY_DETECTED:
+ /*
+ * There has been a change in the phy type before OOB/SN for the
+ * SATA finished start down the SAS link traning path. */
+ scic_sds_phy_start_sas_link_training(this_phy);
+ break;
+
+ default:
+ dev_warn(sciphy_to_dev(this_phy),
+ "%s: PHY starting substate machine received "
+ "unexpected event_code %x\n",
+ __func__,
+ event_code);
+
+ result = SCI_FAILURE;
+ break;
+ }
+
+ return result;
+}
+
+/**
+ *
+ * @phy: This struct scic_sds_phy object which has received an event.
+ * @event_code: This is the event code which the phy object is to decode.
+ *
+ * This method is called when an event notification is received for the phy
+ * object when in the state SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_PHY_EN. -
+ * decode the event - link failure events restart the starting state machine -
+ * sata spinup hold events are ignored since they are expected - sata phy
+ * detected event change to the wait speed event - any other events log a
+ * warning message and set a failure status enum sci_status SCI_SUCCESS on a link
+ * failure event SCI_FAILURE on any unexpected event notifation
+ */
+static enum sci_status scic_sds_phy_starting_substate_await_sata_phy_event_handler(
+ struct scic_sds_phy *this_phy,
+ u32 event_code)
+{
+ u32 result = SCI_SUCCESS;
+
+ switch (scu_get_event_code(event_code)) {
+ case SCU_EVENT_LINK_FAILURE:
+ /* Link failure change state back to the starting state */
+ scic_sds_phy_restart_starting_state(this_phy);
+ break;
+
+ case SCU_EVENT_SATA_SPINUP_HOLD:
+ /*
+ * These events might be received since we dont know how many may be in
+ * the completion queue while waiting for power */
+ break;
+
+ case SCU_EVENT_SATA_PHY_DETECTED:
+ this_phy->protocol = SCIC_SDS_PHY_PROTOCOL_SATA;
+
+ /* We have received the SATA PHY notification change state */
+ sci_base_state_machine_change_state(
+ scic_sds_phy_get_starting_substate_machine(this_phy),
+ SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_SPEED_EN
+ );
+ break;
+
+ case SCU_EVENT_SAS_PHY_DETECTED:
+ /*
+ * There has been a change in the phy type before OOB/SN for the
+ * SATA finished start down the SAS link traning path. */
+ scic_sds_phy_start_sas_link_training(this_phy);
+ break;
+
+ default:
+ dev_warn(sciphy_to_dev(this_phy),
+ "%s: PHY starting substate machine received "
+ "unexpected event_code %x\n",
+ __func__,
+ event_code);
+
+ result = SCI_FAILURE;
+ break;
+ }
+
+ return result;
+}
+
+/**
+ *
+ * @phy: This struct scic_sds_phy object which has received an event.
+ * @event_code: This is the event code which the phy object is to decode.
+ *
+ * This method is called when an event notification is received for the phy
+ * object when in the state SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_SPEED_EN.
+ * - decode the event - sata phy detected returns us back to this state. -
+ * speed event detected causes a state transition to the wait for signature. -
+ * link failure events restart the starting state machine - any other events
+ * log a warning message and set a failure status enum sci_status SCI_SUCCESS on any
+ * valid event notification SCI_FAILURE on any unexpected event notifation
+ */
+static enum sci_status scic_sds_phy_starting_substate_await_sata_speed_event_handler(
+ struct scic_sds_phy *this_phy,
+ u32 event_code)
+{
+ u32 result = SCI_SUCCESS;
+
+ switch (scu_get_event_code(event_code)) {
+ case SCU_EVENT_SATA_PHY_DETECTED:
+ /*
+ * The hardware reports multiple SATA PHY detected events
+ * ignore the extras */
+ break;
+
+ case SCU_EVENT_SATA_15:
+ case SCU_EVENT_SATA_15_SSC:
+ scic_sds_phy_complete_link_training(
+ this_phy,
+ SCI_SAS_150_GB,
+ SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SIG_FIS_UF
+ );
+ break;
+
+ case SCU_EVENT_SATA_30:
+ case SCU_EVENT_SATA_30_SSC:
+ scic_sds_phy_complete_link_training(
+ this_phy,
+ SCI_SAS_300_GB,
+ SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SIG_FIS_UF
+ );
+ break;
+
+ case SCU_EVENT_SATA_60:
+ case SCU_EVENT_SATA_60_SSC:
+ scic_sds_phy_complete_link_training(
+ this_phy,
+ SCI_SAS_600_GB,
+ SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SIG_FIS_UF
+ );
+ break;
+
+ case SCU_EVENT_LINK_FAILURE:
+ /* Link failure change state back to the starting state */
+ scic_sds_phy_restart_starting_state(this_phy);
+ break;
+
+ case SCU_EVENT_SAS_PHY_DETECTED:
+ /*
+ * There has been a change in the phy type before OOB/SN for the
+ * SATA finished start down the SAS link traning path. */
+ scic_sds_phy_start_sas_link_training(this_phy);
+ break;
+
+ default:
+ dev_warn(sciphy_to_dev(this_phy),
+ "%s: PHY starting substate machine received "
+ "unexpected event_code %x\n",
+ __func__,
+ event_code);
+
+ result = SCI_FAILURE;
+ break;
+ }
+
+ return result;
+}
+
+/**
+ *
+ * @phy: This struct scic_sds_phy object which has received an event.
+ * @event_code: This is the event code which the phy object is to decode.
+ *
+ * This method is called when an event notification is received for the phy
+ * object when in the state SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SIG_FIS_UF. -
+ * decode the event - sas phy detected event backs up the state machine to the
+ * await speed notification. - identify timeout is an un-expected event and the
+ * state machine is restarted. - link failure events restart the starting state
+ * machine - any other events log a warning message and set a failure status
+ * enum sci_status SCI_SUCCESS on any valid event notification SCI_FAILURE on any
+ * unexpected event notifation
+ */
+static enum sci_status scic_sds_phy_starting_substate_await_sig_fis_event_handler(
+ struct scic_sds_phy *this_phy,
+ u32 event_code)
+{
+ u32 result = SCI_SUCCESS;
+
+ switch (scu_get_event_code(event_code)) {
+ case SCU_EVENT_SATA_PHY_DETECTED:
+ /* Backup the state machine */
+ sci_base_state_machine_change_state(
+ scic_sds_phy_get_starting_substate_machine(this_phy),
+ SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_SPEED_EN
+ );
+ break;
+
+ case SCU_EVENT_LINK_FAILURE:
+ /* Link failure change state back to the starting state */
+ scic_sds_phy_restart_starting_state(this_phy);
+ break;
+
+ default:
+ dev_warn(sciphy_to_dev(this_phy),
+ "%s: PHY starting substate machine received "
+ "unexpected event_code %x\n",
+ __func__,
+ event_code);
+
+ result = SCI_FAILURE;
+ break;
+ }
+
+ return result;
+}
+
+
+/*
+ * *****************************************************************************
+ * * SCIC SDS PHY FRAME_HANDLERS
+ * ***************************************************************************** */
+
+/**
+ *
+ * @phy: This is struct scic_sds_phy object which is being requested to decode the
+ * frame data.
+ * @frame_index: This is the index of the unsolicited frame which was received
+ * for this phy.
+ *
+ * This method decodes the unsolicited frame when the struct scic_sds_phy is in the
+ * SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_IAF_UF. - Get the UF Header - If the UF
+ * is an IAF - Copy IAF data to local phy object IAF data buffer. - Change
+ * starting substate to wait power. - else - log warning message of unexpected
+ * unsolicted frame - release frame buffer enum sci_status SCI_SUCCESS
+ */
+static enum sci_status scic_sds_phy_starting_substate_await_iaf_uf_frame_handler(
+ struct scic_sds_phy *this_phy,
+ u32 frame_index)
+{
+ enum sci_status result;
+ u32 *frame_words;
+ struct sci_sas_identify_address_frame *identify_frame;
+
+ result = scic_sds_unsolicited_frame_control_get_header(
+ &(scic_sds_phy_get_controller(this_phy)->uf_control),
+ frame_index,
+ (void **)&frame_words);
+
+ if (result != SCI_SUCCESS) {
+ return result;
+ }
+
+ frame_words[0] = SCIC_SWAP_DWORD(frame_words[0]);
+ identify_frame = (struct sci_sas_identify_address_frame *)frame_words;
+
+ if (identify_frame->address_frame_type == 0) {
+ /*
+ * Byte swap the rest of the frame so we can make
+ * a copy of the buffer */
+ frame_words[1] = SCIC_SWAP_DWORD(frame_words[1]);
+ frame_words[2] = SCIC_SWAP_DWORD(frame_words[2]);
+ frame_words[3] = SCIC_SWAP_DWORD(frame_words[3]);
+ frame_words[4] = SCIC_SWAP_DWORD(frame_words[4]);
+ frame_words[5] = SCIC_SWAP_DWORD(frame_words[5]);
+
+ memcpy(
+ &this_phy->phy_type.sas.identify_address_frame_buffer,
+ identify_frame,
+ sizeof(struct sci_sas_identify_address_frame)
+ );
+
+ if (identify_frame->protocols.u.bits.smp_target) {
+ /*
+ * We got the IAF for an expander PHY go to the final state since
+ * there are no power requirements for expander phys. */
+ sci_base_state_machine_change_state(
+ scic_sds_phy_get_starting_substate_machine(this_phy),
+ SCIC_SDS_PHY_STARTING_SUBSTATE_FINAL
+ );
+ } else {
+ /* We got the IAF we can now go to the await spinup semaphore state */
+ sci_base_state_machine_change_state(
+ scic_sds_phy_get_starting_substate_machine(this_phy),
+ SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_POWER
+ );
+ }
+
+ result = SCI_SUCCESS;
+ } else
+ dev_warn(sciphy_to_dev(this_phy),
+ "%s: PHY starting substate machine received "
+ "unexpected frame id %x\n",
+ __func__,
+ frame_index);
+
+ /* Regardless of the result release this frame since we are done with it */
+ scic_sds_controller_release_frame(
+ scic_sds_phy_get_controller(this_phy), frame_index
+ );
+
+ return result;
+}
+
+/**
+ *
+ * @phy: This is struct scic_sds_phy object which is being requested to decode the
+ * frame data.
+ * @frame_index: This is the index of the unsolicited frame which was received
+ * for this phy.
+ *
+ * This method decodes the unsolicited frame when the struct scic_sds_phy is in the
+ * SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SIG_FIS_UF. - Get the UF Header - If
+ * the UF is an SIGNATURE FIS - Copy IAF data to local phy object SIGNATURE FIS
+ * data buffer. - else - log warning message of unexpected unsolicted frame -
+ * release frame buffer enum sci_status SCI_SUCCESS Must decode the SIGNATURE FIS
+ * data
+ */
+static enum sci_status scic_sds_phy_starting_substate_await_sig_fis_frame_handler(
+ struct scic_sds_phy *this_phy,
+ u32 frame_index)
+{
+ enum sci_status result;
+ u32 *frame_words;
+ struct sata_fis_header *fis_frame_header;
+ u32 *fis_frame_data;
+
+ result = scic_sds_unsolicited_frame_control_get_header(
+ &(scic_sds_phy_get_controller(this_phy)->uf_control),
+ frame_index,
+ (void **)&frame_words);
+
+ if (result != SCI_SUCCESS) {
+ return result;
+ }
+
+ fis_frame_header = (struct sata_fis_header *)frame_words;
+
+ if (
+ (fis_frame_header->fis_type == SATA_FIS_TYPE_REGD2H)
+ && !(fis_frame_header->status & ATA_STATUS_REG_BSY_BIT)
+ ) {
+ scic_sds_unsolicited_frame_control_get_buffer(
+ &(scic_sds_phy_get_controller(this_phy)->uf_control),
+ frame_index,
+ (void **)&fis_frame_data
+ );
+
+ scic_sds_controller_copy_sata_response(
+ &this_phy->phy_type.sata.signature_fis_buffer,
+ frame_words,
+ fis_frame_data
+ );
+
+ /* We got the IAF we can now go to the await spinup semaphore state */
+ sci_base_state_machine_change_state(
+ scic_sds_phy_get_starting_substate_machine(this_phy),
+ SCIC_SDS_PHY_STARTING_SUBSTATE_FINAL
+ );
+
+ result = SCI_SUCCESS;
+ } else
+ dev_warn(sciphy_to_dev(this_phy),
+ "%s: PHY starting substate machine received "
+ "unexpected frame id %x\n",
+ __func__,
+ frame_index);
+
+ /* Regardless of the result release this frame since we are done with it */
+ scic_sds_controller_release_frame(
+ scic_sds_phy_get_controller(this_phy), frame_index
+ );
+
+ return result;
+}
+
+/*
+ * *****************************************************************************
+ * * SCIC SDS PHY POWER_HANDLERS
+ * ***************************************************************************** */
+
+/**
+ *
+ * @phy: This is the struct sci_base_phy object which is cast into a struct scic_sds_phy
+ * object.
+ *
+ * This method is called by the struct scic_sds_controller when the phy object is
+ * granted power. - The notify enable spinups are turned on for this phy object
+ * - The phy state machine is transitioned to the
+ * SCIC_SDS_PHY_STARTING_SUBSTATE_FINAL. enum sci_status SCI_SUCCESS
+ */
+static enum sci_status scic_sds_phy_starting_substate_await_sas_power_consume_power_handler(
+ struct scic_sds_phy *this_phy)
+{
+ u32 enable_spinup;
+
+ enable_spinup = SCU_SAS_ENSPINUP_READ(this_phy);
+ enable_spinup |= SCU_ENSPINUP_GEN_BIT(ENABLE);
+ SCU_SAS_ENSPINUP_WRITE(this_phy, enable_spinup);
+
+ /* Change state to the final state this substate machine has run to completion */
+ sci_base_state_machine_change_state(
+ scic_sds_phy_get_starting_substate_machine(this_phy),
+ SCIC_SDS_PHY_STARTING_SUBSTATE_FINAL
+ );
+
+ return SCI_SUCCESS;
+}
+
+/**
+ *
+ * @phy: This is the struct sci_base_phy object which is cast into a struct scic_sds_phy
+ * object.
+ *
+ * This method is called by the struct scic_sds_controller when the phy object is
+ * granted power. - The phy state machine is transitioned to the
+ * SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_PHY_EN. enum sci_status SCI_SUCCESS
+ */
+static enum sci_status scic_sds_phy_starting_substate_await_sata_power_consume_power_handler(
+ struct scic_sds_phy *this_phy)
+{
+ u32 scu_sas_pcfg_value;
+
+ /* Release the spinup hold state and reset the OOB state machine */
+ scu_sas_pcfg_value = SCU_SAS_PCFG_READ(this_phy);
+ scu_sas_pcfg_value &=
+ ~(SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD) | SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE));
+ scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
+ SCU_SAS_PCFG_WRITE(this_phy, scu_sas_pcfg_value);
+
+ /* Now restart the OOB operation */
+ scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
+ scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
+ SCU_SAS_PCFG_WRITE(this_phy, scu_sas_pcfg_value);
+
+ /* Change state to the final state this substate machine has run to completion */
+ sci_base_state_machine_change_state(
+ scic_sds_phy_get_starting_substate_machine(this_phy),
+ SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_PHY_EN
+ );
+
+ return SCI_SUCCESS;
+}
+
+/* --------------------------------------------------------------------------- */
+
+struct scic_sds_phy_state_handler
+scic_sds_phy_starting_substate_handler_table[SCIC_SDS_PHY_STARTING_MAX_SUBSTATES] =
+{
+ /* SCIC_SDS_PHY_STARTING_SUBSTATE_INITIAL */
+ {
+ {
+ scic_sds_phy_default_start_handler,
+ scic_sds_phy_default_stop_handler,
+ scic_sds_phy_default_reset_handler,
+ scic_sds_phy_default_destroy_handler
+ },
+ scic_sds_phy_default_frame_handler,
+ scic_sds_phy_default_event_handler,
+ scic_sds_phy_default_consume_power_handler
+ },
+ /* SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_OSSP_EN */
+ {
+ {
+ scic_sds_phy_default_start_handler,
+ scic_sds_phy_default_stop_handler,
+ scic_sds_phy_default_reset_handler,
+ scic_sds_phy_default_destroy_handler
+ },
+ scic_sds_phy_default_frame_handler,
+ scic_sds_phy_starting_substate_await_ossp_event_handler,
+ scic_sds_phy_default_consume_power_handler
+ },
+ /* SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_SPEED_EN */
+ {
+ {
+ scic_sds_phy_default_start_handler,
+ scic_sds_phy_default_stop_handler,
+ scic_sds_phy_default_reset_handler,
+ scic_sds_phy_default_destroy_handler
+ },
+ scic_sds_phy_default_frame_handler,
+ scic_sds_phy_starting_substate_await_sas_phy_speed_event_handler,
+ scic_sds_phy_default_consume_power_handler
+ },
+ /* SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_IAF_UF */
+ {
+ {
+ scic_sds_phy_default_start_handler,
+ scic_sds_phy_default_stop_handler,
+ scic_sds_phy_default_reset_handler,
+ scic_sds_phy_default_destroy_handler
+ },
+ scic_sds_phy_starting_substate_await_iaf_uf_frame_handler,
+ scic_sds_phy_starting_substate_await_iaf_uf_event_handler,
+ scic_sds_phy_default_consume_power_handler
+ },
+ /* SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_POWER */
+ {
+ {
+ scic_sds_phy_default_start_handler,
+ scic_sds_phy_default_stop_handler,
+ scic_sds_phy_default_reset_handler,
+ scic_sds_phy_default_destroy_handler
+ },
+ scic_sds_phy_default_frame_handler,
+ scic_sds_phy_starting_substate_await_sas_power_event_handler,
+ scic_sds_phy_starting_substate_await_sas_power_consume_power_handler
+ },
+ /* SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_POWER, */
+ {
+ {
+ scic_sds_phy_default_start_handler,
+ scic_sds_phy_default_stop_handler,
+ scic_sds_phy_default_reset_handler,
+ scic_sds_phy_default_destroy_handler
+ },
+ scic_sds_phy_default_frame_handler,
+ scic_sds_phy_starting_substate_await_sata_power_event_handler,
+ scic_sds_phy_starting_substate_await_sata_power_consume_power_handler
+ },
+ /* SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_PHY_EN, */
+ {
+ {
+ scic_sds_phy_default_start_handler,
+ scic_sds_phy_default_stop_handler,
+ scic_sds_phy_default_reset_handler,
+ scic_sds_phy_default_destroy_handler
+ },
+ scic_sds_phy_default_frame_handler,
+ scic_sds_phy_starting_substate_await_sata_phy_event_handler,
+ scic_sds_phy_default_consume_power_handler
+ },
+ /* SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_SPEED_EN, */
+ {
+ {
+ scic_sds_phy_default_start_handler,
+ scic_sds_phy_default_stop_handler,
+ scic_sds_phy_default_reset_handler,
+ scic_sds_phy_default_destroy_handler
+ },
+ scic_sds_phy_default_frame_handler,
+ scic_sds_phy_starting_substate_await_sata_speed_event_handler,
+ scic_sds_phy_default_consume_power_handler
+ },
+ /* SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SIG_FIS_UF, */
+ {
+ {
+ scic_sds_phy_default_start_handler,
+ scic_sds_phy_default_stop_handler,
+ scic_sds_phy_default_reset_handler,
+ scic_sds_phy_default_destroy_handler
+ },
+ scic_sds_phy_starting_substate_await_sig_fis_frame_handler,
+ scic_sds_phy_starting_substate_await_sig_fis_event_handler,
+ scic_sds_phy_default_consume_power_handler
+ },
+ /* SCIC_SDS_PHY_STARTING_SUBSTATE_FINAL */
+ {
+ {
+ scic_sds_phy_default_start_handler,
+ scic_sds_phy_default_stop_handler,
+ scic_sds_phy_default_reset_handler,
+ scic_sds_phy_default_destroy_handler
+ },
+ scic_sds_phy_default_frame_handler,
+ scic_sds_phy_default_event_handler,
+ scic_sds_phy_default_consume_power_handler
+ }
+};
+
+/**
+ * scic_sds_phy_set_starting_substate_handlers() -
+ *
+ * This macro sets the starting substate handlers by state_id
+ */
+#define scic_sds_phy_set_starting_substate_handlers(phy, state_id) \
+ scic_sds_phy_set_state_handlers(\
+ (phy), \
+ &scic_sds_phy_starting_substate_handler_table[(state_id)] \
+ )
+
+/*
+ * ****************************************************************************
+ * * PHY STARTING SUBSTATE METHODS
+ * **************************************************************************** */
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on
+ * entering the SCIC_SDS_PHY_STARTING_SUBSTATE_INITIAL. - The initial state
+ * handlers are put in place for the struct scic_sds_phy object. - The state is
+ * changed to the wait phy type event notification. none
+ */
+static void scic_sds_phy_starting_initial_substate_enter(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_sds_phy_set_starting_substate_handlers(
+ this_phy, SCIC_SDS_PHY_STARTING_SUBSTATE_INITIAL);
+
+ /* This is just an temporary state go off to the starting state */
+ sci_base_state_machine_change_state(
+ scic_sds_phy_get_starting_substate_machine(this_phy),
+ SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_OSSP_EN
+ );
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on
+ * entering the SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_PHY_TYPE_EN. - Set the
+ * struct scic_sds_phy object state handlers for this state. none
+ */
+static void scic_sds_phy_starting_await_ossp_en_substate_enter(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_sds_phy_set_starting_substate_handlers(
+ this_phy, SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_OSSP_EN
+ );
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on
+ * entering the SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SPEED_EN. - Set the
+ * struct scic_sds_phy object state handlers for this state. none
+ */
+static void scic_sds_phy_starting_await_sas_speed_en_substate_enter(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_sds_phy_set_starting_substate_handlers(
+ this_phy, SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_SPEED_EN
+ );
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on
+ * entering the SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_IAF_UF. - Set the
+ * struct scic_sds_phy object state handlers for this state. none
+ */
+static void scic_sds_phy_starting_await_iaf_uf_substate_enter(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_sds_phy_set_starting_substate_handlers(
+ this_phy, SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_IAF_UF
+ );
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on
+ * entering the SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_POWER. - Set the
+ * struct scic_sds_phy object state handlers for this state. - Add this phy object to
+ * the power control queue none
+ */
+static void scic_sds_phy_starting_await_sas_power_substate_enter(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_sds_phy_set_starting_substate_handlers(
+ this_phy, SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_POWER
+ );
+
+ scic_sds_controller_power_control_queue_insert(
+ scic_sds_phy_get_controller(this_phy),
+ this_phy
+ );
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on exiting
+ * the SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_POWER. - Remove the
+ * struct scic_sds_phy object from the power control queue. none
+ */
+static void scic_sds_phy_starting_await_sas_power_substate_exit(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_sds_controller_power_control_queue_remove(
+ scic_sds_phy_get_controller(this_phy), this_phy
+ );
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on
+ * entering the SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_POWER. - Set the
+ * struct scic_sds_phy object state handlers for this state. - Add this phy object to
+ * the power control queue none
+ */
+static void scic_sds_phy_starting_await_sata_power_substate_enter(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_sds_phy_set_starting_substate_handlers(
+ this_phy, SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_POWER
+ );
+
+ scic_sds_controller_power_control_queue_insert(
+ scic_sds_phy_get_controller(this_phy),
+ this_phy
+ );
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on exiting
+ * the SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_POWER. - Remove the
+ * struct scic_sds_phy object from the power control queue. none
+ */
+static void scic_sds_phy_starting_await_sata_power_substate_exit(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_sds_controller_power_control_queue_remove(
+ scic_sds_phy_get_controller(this_phy),
+ this_phy
+ );
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on
+ * entering the SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_PHY_EN. - Set the
+ * struct scic_sds_phy object state handlers for this state. none
+ */
+static void scic_sds_phy_starting_await_sata_phy_substate_enter(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_sds_phy_set_starting_substate_handlers(
+ this_phy, SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_PHY_EN
+ );
+
+ scic_cb_timer_start(
+ scic_sds_phy_get_controller(this_phy),
+ this_phy->sata_timeout_timer,
+ SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT
+ );
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on exiting
+ * the SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_SPEED_EN. - stop the timer
+ * that was started on entry to await sata phy event notification none
+ */
+static void scic_sds_phy_starting_await_sata_phy_substate_exit(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_cb_timer_stop(
+ scic_sds_phy_get_controller(this_phy),
+ this_phy->sata_timeout_timer
+ );
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on
+ * entering the SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_SPEED_EN. - Set the
+ * struct scic_sds_phy object state handlers for this state. none
+ */
+static void scic_sds_phy_starting_await_sata_speed_substate_enter(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_sds_phy_set_starting_substate_handlers(
+ this_phy, SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_SPEED_EN
+ );
+
+ scic_cb_timer_start(
+ scic_sds_phy_get_controller(this_phy),
+ this_phy->sata_timeout_timer,
+ SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT
+ );
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on exiting
+ * the SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_SPEED_EN. - stop the timer
+ * that was started on entry to await sata phy event notification none
+ */
+static void scic_sds_phy_starting_await_sata_speed_substate_exit(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_cb_timer_stop(
+ scic_sds_phy_get_controller(this_phy),
+ this_phy->sata_timeout_timer
+ );
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on
+ * entering the SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SIG_FIS_UF. - Set the
+ * struct scic_sds_phy object state handlers for this state. - Start the SIGNATURE FIS
+ * timeout timer none
+ */
+static void scic_sds_phy_starting_await_sig_fis_uf_substate_enter(
+ struct sci_base_object *object)
+{
+ bool continue_to_ready_state;
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_sds_phy_set_starting_substate_handlers(
+ this_phy, SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SIG_FIS_UF
+ );
+
+ continue_to_ready_state = scic_sds_port_link_detected(
+ this_phy->owning_port,
+ this_phy
+ );
+
+ if (continue_to_ready_state) {
+ /*
+ * Clear the PE suspend condition so we can actually receive SIG FIS
+ * The hardware will not respond to the XRDY until the PE suspend
+ * condition is cleared. */
+ scic_sds_phy_resume(this_phy);
+
+ scic_cb_timer_start(
+ scic_sds_phy_get_controller(this_phy),
+ this_phy->sata_timeout_timer,
+ SCIC_SDS_SIGNATURE_FIS_TIMEOUT
+ );
+ } else {
+ this_phy->is_in_link_training = false;
+ }
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on exiting
+ * the SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SIG_FIS_UF. - Stop the SIGNATURE
+ * FIS timeout timer. none
+ */
+static void scic_sds_phy_starting_await_sig_fis_uf_substate_exit(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_cb_timer_stop(
+ scic_sds_phy_get_controller(this_phy),
+ this_phy->sata_timeout_timer
+ );
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on
+ * entering the SCIC_SDS_PHY_STARTING_SUBSTATE_FINAL. - Set the struct scic_sds_phy
+ * object state handlers for this state. - Change base state machine to the
+ * ready state. none
+ */
+static void scic_sds_phy_starting_final_substate_enter(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_sds_phy_set_starting_substate_handlers(
+ this_phy, SCIC_SDS_PHY_STARTING_SUBSTATE_FINAL
+ );
+
+ /*
+ * State machine has run to completion so exit out and change
+ * the base state machine to the ready state */
+ sci_base_state_machine_change_state(
+ scic_sds_phy_get_base_state_machine(this_phy),
+ SCI_BASE_PHY_STATE_READY);
+}
+
+/* --------------------------------------------------------------------------- */
+
+const struct sci_base_state scic_sds_phy_starting_substates[] = {
+ [SCIC_SDS_PHY_STARTING_SUBSTATE_INITIAL] = {
+ .enter_state = scic_sds_phy_starting_initial_substate_enter,
+ },
+ [SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_OSSP_EN] = {
+ .enter_state = scic_sds_phy_starting_await_ossp_en_substate_enter,
+ },
+ [SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_SPEED_EN] = {
+ .enter_state = scic_sds_phy_starting_await_sas_speed_en_substate_enter,
+ },
+ [SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_IAF_UF] = {
+ .enter_state = scic_sds_phy_starting_await_iaf_uf_substate_enter,
+ },
+ [SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_POWER] = {
+ .enter_state = scic_sds_phy_starting_await_sas_power_substate_enter,
+ .exit_state = scic_sds_phy_starting_await_sas_power_substate_exit,
+ },
+ [SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_POWER] = {
+ .enter_state = scic_sds_phy_starting_await_sata_power_substate_enter,
+ .exit_state = scic_sds_phy_starting_await_sata_power_substate_exit
+ },
+ [SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_PHY_EN] = {
+ .enter_state = scic_sds_phy_starting_await_sata_phy_substate_enter,
+ .exit_state = scic_sds_phy_starting_await_sata_phy_substate_exit
+ },
+ [SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_SPEED_EN] = {
+ .enter_state = scic_sds_phy_starting_await_sata_speed_substate_enter,
+ .exit_state = scic_sds_phy_starting_await_sata_speed_substate_exit
+ },
+ [SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SIG_FIS_UF] = {
+ .enter_state = scic_sds_phy_starting_await_sig_fis_uf_substate_enter,
+ .exit_state = scic_sds_phy_starting_await_sig_fis_uf_substate_exit
+ },
+ [SCIC_SDS_PHY_STARTING_SUBSTATE_FINAL] = {
+ .enter_state = scic_sds_phy_starting_final_substate_enter,
+ }
+};
+
+/*
+ * ***************************************************************************
+ * * DEFAULT HANDLERS
+ * *************************************************************************** */
+
+/**
+ *
+ * @phy: This is the struct sci_base_phy object which is cast into a struct scic_sds_phy
+ * object.
+ *
+ * This is the default method for phy a start request. It will report a
+ * warning and exit. enum sci_status SCI_FAILURE_INVALID_STATE
+ */
+enum sci_status scic_sds_phy_default_start_handler(
+ struct sci_base_phy *phy)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)phy;
+
+ dev_warn(sciphy_to_dev(this_phy),
+ "%s: SCIC Phy 0x%p requested to start from invalid "
+ "state %d\n",
+ __func__,
+ this_phy,
+ sci_base_state_machine_get_state(
+ &this_phy->parent.state_machine));
+
+ return SCI_FAILURE_INVALID_STATE;
+
+}
+
+/**
+ *
+ * @phy: This is the struct sci_base_phy object which is cast into a struct scic_sds_phy
+ * object.
+ *
+ * This is the default method for phy a stop request. It will report a warning
+ * and exit. enum sci_status SCI_FAILURE_INVALID_STATE
+ */
+enum sci_status scic_sds_phy_default_stop_handler(
+ struct sci_base_phy *phy)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)phy;
+
+ dev_warn(sciphy_to_dev(this_phy),
+ "%s: SCIC Phy 0x%p requested to stop from invalid "
+ "state %d\n",
+ __func__,
+ this_phy,
+ sci_base_state_machine_get_state(
+ &this_phy->parent.state_machine));
+
+ return SCI_FAILURE_INVALID_STATE;
+}
+
+/**
+ *
+ * @phy: This is the struct sci_base_phy object which is cast into a struct scic_sds_phy
+ * object.
+ *
+ * This is the default method for phy a reset request. It will report a
+ * warning and exit. enum sci_status SCI_FAILURE_INVALID_STATE
+ */
+enum sci_status scic_sds_phy_default_reset_handler(
+ struct sci_base_phy *phy)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)phy;
+
+ dev_warn(sciphy_to_dev(this_phy),
+ "%s: SCIC Phy 0x%p requested to reset from invalid state "
+ "%d\n",
+ __func__,
+ this_phy,
+ sci_base_state_machine_get_state(
+ &this_phy->parent.state_machine));
+
+ return SCI_FAILURE_INVALID_STATE;
+}
+
+/**
+ *
+ * @phy: This is the struct sci_base_phy object which is cast into a struct scic_sds_phy
+ * object.
+ *
+ * This is the default method for phy a destruct request. It will report a
+ * warning and exit. enum sci_status SCI_FAILURE_INVALID_STATE
+ */
+enum sci_status scic_sds_phy_default_destroy_handler(
+ struct sci_base_phy *phy)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)phy;
+
+ /* / @todo Implement something for the default */
+ dev_warn(sciphy_to_dev(this_phy),
+ "%s: SCIC Phy 0x%p requested to destroy from invalid "
+ "state %d\n",
+ __func__,
+ this_phy,
+ sci_base_state_machine_get_state(
+ &this_phy->parent.state_machine));
+
+ return SCI_FAILURE_INVALID_STATE;
+}
+
+/**
+ *
+ * @phy: This is the struct sci_base_phy object which is cast into a struct scic_sds_phy
+ * object.
+ * @frame_index: This is the frame index that was received from the SCU
+ * hardware.
+ *
+ * This is the default method for a phy frame handling request. It will report
+ * a warning, release the frame and exit. enum sci_status SCI_FAILURE_INVALID_STATE
+ */
+enum sci_status scic_sds_phy_default_frame_handler(
+ struct scic_sds_phy *this_phy,
+ u32 frame_index)
+{
+ dev_warn(sciphy_to_dev(this_phy),
+ "%s: SCIC Phy 0x%p received unexpected frame data %d "
+ "while in state %d\n",
+ __func__,
+ this_phy,
+ frame_index,
+ sci_base_state_machine_get_state(
+ &this_phy->parent.state_machine));
+
+ scic_sds_controller_release_frame(
+ scic_sds_phy_get_controller(this_phy), frame_index);
+
+ return SCI_FAILURE_INVALID_STATE;
+}
+
+/**
+ *
+ * @phy: This is the struct sci_base_phy object which is cast into a struct scic_sds_phy
+ * object.
+ * @event_code: This is the event code that was received from the SCU hardware.
+ *
+ * This is the default method for a phy event handler. It will report a
+ * warning and exit. enum sci_status SCI_FAILURE_INVALID_STATE
+ */
+enum sci_status scic_sds_phy_default_event_handler(
+ struct scic_sds_phy *this_phy,
+ u32 event_code)
+{
+ dev_warn(sciphy_to_dev(this_phy),
+ "%s: SCIC Phy 0x%p received unexpected event status %x "
+ "while in state %d\n",
+ __func__,
+ this_phy,
+ event_code,
+ sci_base_state_machine_get_state(
+ &this_phy->parent.state_machine));
+
+ return SCI_FAILURE_INVALID_STATE;
+}
+
+/**
+ *
+ * @phy: This is the struct sci_base_phy object which is cast into a struct scic_sds_phy
+ * object.
+ *
+ * This is the default method for a phy consume power handler. It will report
+ * a warning and exit. enum sci_status SCI_FAILURE_INVALID_STATE
+ */
+enum sci_status scic_sds_phy_default_consume_power_handler(
+ struct scic_sds_phy *this_phy)
+{
+ dev_warn(sciphy_to_dev(this_phy),
+ "%s: SCIC Phy 0x%p given unexpected permission to consume "
+ "power while in state %d\n",
+ __func__,
+ this_phy,
+ sci_base_state_machine_get_state(
+ &this_phy->parent.state_machine));
+
+ return SCI_FAILURE_INVALID_STATE;
+}
+
+/*
+ * ******************************************************************************
+ * * PHY STOPPED STATE HANDLERS
+ * ****************************************************************************** */
+
+/**
+ *
+ * @phy: This is the struct sci_base_phy object which is cast into a struct scic_sds_phy
+ * object.
+ *
+ * This method takes the struct scic_sds_phy from a stopped state and attempts to
+ * start it. - The phy state machine is transitioned to the
+ * SCI_BASE_PHY_STATE_STARTING. enum sci_status SCI_SUCCESS
+ */
+static enum sci_status scic_sds_phy_stopped_state_start_handler(
+ struct sci_base_phy *phy)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)phy;
+
+ sci_base_state_machine_change_state(
+ scic_sds_phy_get_base_state_machine(this_phy),
+ SCI_BASE_PHY_STATE_STARTING
+ );
+
+ return SCI_SUCCESS;
+}
+
+/**
+ *
+ * @phy: This is the struct sci_base_phy object which is cast into a struct scic_sds_phy
+ * object.
+ *
+ * This method takes the struct scic_sds_phy from a stopped state and destroys it. -
+ * This function takes no action. Shouldnt this function transition the
+ * struct sci_base_phy::state_machine to the SCI_BASE_PHY_STATE_FINAL? enum sci_status
+ * SCI_SUCCESS
+ */
+static enum sci_status scic_sds_phy_stopped_state_destroy_handler(
+ struct sci_base_phy *phy)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)phy;
+
+ /* / @todo what do we actually need to do here? */
+ return SCI_SUCCESS;
+}
+
+/*
+ * ******************************************************************************
+ * * PHY STARTING STATE HANDLERS
+ * ****************************************************************************** */
+
+/* All of these state handlers are mapped to the starting sub-state machine */
+
+/*
+ * ******************************************************************************
+ * * PHY READY STATE HANDLERS
+ * ****************************************************************************** */
+
+/**
+ *
+ * @phy: This is the struct sci_base_phy object which is cast into a struct scic_sds_phy
+ * object.
+ *
+ * This method takes the struct scic_sds_phy from a ready state and attempts to stop
+ * it. - The phy state machine is transitioned to the
+ * SCI_BASE_PHY_STATE_STOPPED. enum sci_status SCI_SUCCESS
+ */
+static enum sci_status scic_sds_phy_ready_state_stop_handler(
+ struct sci_base_phy *phy)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)phy;
+
+ sci_base_state_machine_change_state(
+ scic_sds_phy_get_base_state_machine(this_phy),
+ SCI_BASE_PHY_STATE_STOPPED
+ );
+
+ return SCI_SUCCESS;
+}
+
+/**
+ *
+ * @phy: This is the struct sci_base_phy object which is cast into a struct scic_sds_phy
+ * object.
+ *
+ * This method takes the struct scic_sds_phy from a ready state and attempts to reset
+ * it. - The phy state machine is transitioned to the
+ * SCI_BASE_PHY_STATE_STARTING. enum sci_status SCI_SUCCESS
+ */
+static enum sci_status scic_sds_phy_ready_state_reset_handler(
+ struct sci_base_phy *phy)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)phy;
+
+ sci_base_state_machine_change_state(
+ scic_sds_phy_get_base_state_machine(this_phy),
+ SCI_BASE_PHY_STATE_RESETTING
+ );
+
+ return SCI_SUCCESS;
+}
+
+/**
+ *
+ * @phy: This is the struct scic_sds_phy object which has received the event.
+ *
+ * This method request the struct scic_sds_phy handle the received event. The only
+ * event that we are interested in while in the ready state is the link failure
+ * event. - decoded event is a link failure - transition the struct scic_sds_phy back
+ * to the SCI_BASE_PHY_STATE_STARTING state. - any other event recived will
+ * report a warning message enum sci_status SCI_SUCCESS if the event received is a
+ * link failure SCI_FAILURE_INVALID_STATE for any other event received.
+ */
+static enum sci_status scic_sds_phy_ready_state_event_handler(
+ struct scic_sds_phy *this_phy,
+ u32 event_code)
+{
+ enum sci_status result = SCI_FAILURE;
+
+ switch (scu_get_event_code(event_code)) {
+ case SCU_EVENT_LINK_FAILURE:
+ /* Link failure change state back to the starting state */
+ sci_base_state_machine_change_state(
+ scic_sds_phy_get_base_state_machine(this_phy),
+ SCI_BASE_PHY_STATE_STARTING
+ );
+
+ result = SCI_SUCCESS;
+ break;
+
+ case SCU_EVENT_BROADCAST_CHANGE:
+ /* Broadcast change received. Notify the port. */
+ if (scic_sds_phy_get_port(this_phy) != SCI_INVALID_HANDLE)
+ scic_sds_port_broadcast_change_received(this_phy->owning_port, this_phy);
+ else
+ this_phy->bcn_received_while_port_unassigned = true;
+ break;
+
+ default:
+ dev_warn(sciphy_to_dev(this_phy),
+ "%sP SCIC PHY 0x%p ready state machine received "
+ "unexpected event_code %x\n",
+ __func__,
+ this_phy,
+ event_code);
+
+ result = SCI_FAILURE_INVALID_STATE;
+ break;
+ }
+
+ return result;
+}
+
+/* --------------------------------------------------------------------------- */
+
+/**
+ *
+ * @this_phy: This is the struct scic_sds_phy object which is receiving the event.
+ * @event_code: This is the event code to be processed.
+ *
+ * This is the resetting state event handler. enum sci_status
+ * SCI_FAILURE_INVALID_STATE
+ */
+static enum sci_status scic_sds_phy_resetting_state_event_handler(
+ struct scic_sds_phy *this_phy,
+ u32 event_code)
+{
+ enum sci_status result = SCI_FAILURE;
+
+ switch (scu_get_event_code(event_code)) {
+ case SCU_EVENT_HARD_RESET_TRANSMITTED:
+ /* Link failure change state back to the starting state */
+ sci_base_state_machine_change_state(
+ scic_sds_phy_get_base_state_machine(this_phy),
+ SCI_BASE_PHY_STATE_STARTING
+ );
+
+ result = SCI_SUCCESS;
+ break;
+
+ default:
+ dev_warn(sciphy_to_dev(this_phy),
+ "%s: SCIC PHY 0x%p resetting state machine received "
+ "unexpected event_code %x\n",
+ __func__,
+ this_phy,
+ event_code);
+
+ result = SCI_FAILURE_INVALID_STATE;
+ break;
+ }
+
+ return result;
+}
+
+/* --------------------------------------------------------------------------- */
+
+struct scic_sds_phy_state_handler
+scic_sds_phy_state_handler_table[SCI_BASE_PHY_MAX_STATES] =
+{
+ /* SCI_BASE_PHY_STATE_INITIAL */
+ {
+ {
+ scic_sds_phy_default_start_handler,
+ scic_sds_phy_default_stop_handler,
+ scic_sds_phy_default_reset_handler,
+ scic_sds_phy_default_destroy_handler
+ },
+ scic_sds_phy_default_frame_handler,
+ scic_sds_phy_default_event_handler,
+ scic_sds_phy_default_consume_power_handler
+ },
+ /* SCI_BASE_PHY_STATE_STOPPED */
+ {
+ {
+ scic_sds_phy_stopped_state_start_handler,
+ scic_sds_phy_default_stop_handler,
+ scic_sds_phy_default_reset_handler,
+ scic_sds_phy_stopped_state_destroy_handler
+ },
+ scic_sds_phy_default_frame_handler,
+ scic_sds_phy_default_event_handler,
+ scic_sds_phy_default_consume_power_handler
+ },
+ /* SCI_BASE_PHY_STATE_STARTING */
+ {
+ {
+ scic_sds_phy_default_start_handler,
+ scic_sds_phy_default_stop_handler,
+ scic_sds_phy_default_reset_handler,
+ scic_sds_phy_default_destroy_handler
+ },
+ scic_sds_phy_default_frame_handler,
+ scic_sds_phy_default_event_handler,
+ scic_sds_phy_default_consume_power_handler
+ },
+ /* SCI_BASE_PHY_STATE_READY */
+ {
+ {
+ scic_sds_phy_default_start_handler,
+ scic_sds_phy_ready_state_stop_handler,
+ scic_sds_phy_ready_state_reset_handler,
+ scic_sds_phy_default_destroy_handler
+ },
+ scic_sds_phy_default_frame_handler,
+ scic_sds_phy_ready_state_event_handler,
+ scic_sds_phy_default_consume_power_handler
+ },
+ /* SCI_BASE_PHY_STATE_RESETTING */
+ {
+ {
+ scic_sds_phy_default_start_handler,
+ scic_sds_phy_default_stop_handler,
+ scic_sds_phy_default_reset_handler,
+ scic_sds_phy_default_destroy_handler
+ },
+ scic_sds_phy_default_frame_handler,
+ scic_sds_phy_resetting_state_event_handler,
+ scic_sds_phy_default_consume_power_handler
+ },
+ /* SCI_BASE_PHY_STATE_FINAL */
+ {
+ {
+ scic_sds_phy_default_start_handler,
+ scic_sds_phy_default_stop_handler,
+ scic_sds_phy_default_reset_handler,
+ scic_sds_phy_default_destroy_handler
+ },
+ scic_sds_phy_default_frame_handler,
+ scic_sds_phy_default_event_handler,
+ scic_sds_phy_default_consume_power_handler
+ }
+};
+
+/*
+ * ****************************************************************************
+ * * PHY STATE PRIVATE METHODS
+ * **************************************************************************** */
+
+/**
+ *
+ * @this_phy: This is the struct scic_sds_phy object to stop.
+ *
+ * This method will stop the struct scic_sds_phy object. This does not reset the
+ * protocol engine it just suspends it and places it in a state where it will
+ * not cause the end device to power up. none
+ */
+static void scu_link_layer_stop_protocol_engine(
+ struct scic_sds_phy *this_phy)
+{
+ u32 scu_sas_pcfg_value;
+ u32 enable_spinup_value;
+
+ /* Suspend the protocol engine and place it in a sata spinup hold state */
+ scu_sas_pcfg_value = SCU_SAS_PCFG_READ(this_phy);
+ scu_sas_pcfg_value |= (
+ SCU_SAS_PCFG_GEN_BIT(OOB_RESET)
+ | SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE)
+ | SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD)
+ );
+ SCU_SAS_PCFG_WRITE(this_phy, scu_sas_pcfg_value);
+
+ /* Disable the notify enable spinup primitives */
+ enable_spinup_value = SCU_SAS_ENSPINUP_READ(this_phy);
+ enable_spinup_value &= ~SCU_ENSPINUP_GEN_BIT(ENABLE);
+ SCU_SAS_ENSPINUP_WRITE(this_phy, enable_spinup_value);
+}
+
+/**
+ *
+ *
+ * This method will start the OOB/SN state machine for this struct scic_sds_phy object.
+ */
+static void scu_link_layer_start_oob(
+ struct scic_sds_phy *this_phy)
+{
+ u32 scu_sas_pcfg_value;
+
+ scu_sas_pcfg_value = SCU_SAS_PCFG_READ(this_phy);
+ scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
+ scu_sas_pcfg_value &=
+ ~(SCU_SAS_PCFG_GEN_BIT(OOB_RESET) | SCU_SAS_PCFG_GEN_BIT(HARD_RESET));
+
+ SCU_SAS_PCFG_WRITE(this_phy, scu_sas_pcfg_value);
+}
+
+/**
+ *
+ *
+ * This method will transmit a hard reset request on the specified phy. The SCU
+ * hardware requires that we reset the OOB state machine and set the hard reset
+ * bit in the phy configuration register. We then must start OOB over with the
+ * hard reset bit set.
+ */
+static void scu_link_layer_tx_hard_reset(
+ struct scic_sds_phy *this_phy)
+{
+ u32 phy_configuration_value;
+
+ /*
+ * SAS Phys must wait for the HARD_RESET_TX event notification to transition
+ * to the starting state. */
+ phy_configuration_value = SCU_SAS_PCFG_READ(this_phy);
+ phy_configuration_value |=
+ (SCU_SAS_PCFG_GEN_BIT(HARD_RESET) | SCU_SAS_PCFG_GEN_BIT(OOB_RESET));
+ SCU_SAS_PCFG_WRITE(this_phy, phy_configuration_value);
+
+ /* Now take the OOB state machine out of reset */
+ phy_configuration_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
+ phy_configuration_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
+ SCU_SAS_PCFG_WRITE(this_phy, phy_configuration_value);
+}
+
+/*
+ * ****************************************************************************
+ * * PHY BASE STATE METHODS
+ * **************************************************************************** */
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on
+ * entering the SCI_BASE_PHY_STATE_INITIAL. - This function sets the state
+ * handlers for the phy object base state machine initial state. none
+ */
+static void scic_sds_phy_initial_state_enter(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_sds_phy_set_base_state_handlers(this_phy, SCI_BASE_PHY_STATE_STOPPED);
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on
+ * entering the SCI_BASE_PHY_STATE_INITIAL. - This function sets the state
+ * handlers for the phy object base state machine initial state. - The SCU
+ * hardware is requested to stop the protocol engine. none
+ */
+static void scic_sds_phy_stopped_state_enter(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ /* / @todo We need to get to the controller to place this PE in a reset state */
+
+ scic_sds_phy_set_base_state_handlers(this_phy, SCI_BASE_PHY_STATE_STOPPED);
+
+ scu_link_layer_stop_protocol_engine(this_phy);
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on
+ * entering the SCI_BASE_PHY_STATE_STARTING. - This function sets the state
+ * handlers for the phy object base state machine starting state. - The SCU
+ * hardware is requested to start OOB/SN on this protocl engine. - The phy
+ * starting substate machine is started. - If the previous state was the ready
+ * state then the struct scic_sds_controller is informed that the phy has gone link
+ * down. none
+ */
+static void scic_sds_phy_starting_state_enter(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_sds_phy_set_base_state_handlers(this_phy, SCI_BASE_PHY_STATE_STARTING);
+
+ scu_link_layer_stop_protocol_engine(this_phy);
+ scu_link_layer_start_oob(this_phy);
+
+ /* We don't know what kind of phy we are going to be just yet */
+ this_phy->protocol = SCIC_SDS_PHY_PROTOCOL_UNKNOWN;
+ this_phy->bcn_received_while_port_unassigned = false;
+
+ /* Change over to the starting substate machine to continue */
+ sci_base_state_machine_start(&this_phy->starting_substate_machine);
+
+ if (this_phy->parent.state_machine.previous_state_id
+ == SCI_BASE_PHY_STATE_READY) {
+ scic_sds_controller_link_down(
+ scic_sds_phy_get_controller(this_phy),
+ scic_sds_phy_get_port(this_phy),
+ this_phy
+ );
+ }
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on
+ * entering the SCI_BASE_PHY_STATE_READY. - This function sets the state
+ * handlers for the phy object base state machine ready state. - The SCU
+ * hardware protocol engine is resumed. - The struct scic_sds_controller is informed
+ * that the phy object has gone link up. none
+ */
+static void scic_sds_phy_ready_state_enter(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_sds_phy_set_base_state_handlers(this_phy, SCI_BASE_PHY_STATE_READY);
+
+ scic_sds_controller_link_up(
+ scic_sds_phy_get_controller(this_phy),
+ scic_sds_phy_get_port(this_phy),
+ this_phy
+ );
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on exiting
+ * the SCI_BASE_PHY_STATE_INITIAL. This function suspends the SCU hardware
+ * protocol engine represented by this struct scic_sds_phy object. none
+ */
+static void scic_sds_phy_ready_state_exit(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_sds_phy_suspend(this_phy);
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on
+ * entering the SCI_BASE_PHY_STATE_RESETTING. - This function sets the state
+ * handlers for the phy object base state machine resetting state. none
+ */
+static void scic_sds_phy_resetting_state_enter(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_sds_phy_set_base_state_handlers(this_phy, SCI_BASE_PHY_STATE_RESETTING);
+
+ /*
+ * The phy is being reset, therefore deactivate it from the port.
+ * In the resetting state we don't notify the user regarding
+ * link up and link down notifications. */
+ scic_sds_port_deactivate_phy(this_phy->owning_port, this_phy, false);
+
+ if (this_phy->protocol == SCIC_SDS_PHY_PROTOCOL_SAS) {
+ scu_link_layer_tx_hard_reset(this_phy);
+ } else {
+ /*
+ * The SCU does not need to have a descrete reset state so just go back to
+ * the starting state. */
+ sci_base_state_machine_change_state(
+ &this_phy->parent.state_machine,
+ SCI_BASE_PHY_STATE_STARTING
+ );
+ }
+}
+
+/**
+ *
+ * @object: This is the struct sci_base_object which is cast to a struct scic_sds_phy object.
+ *
+ * This method will perform the actions required by the struct scic_sds_phy on
+ * entering the SCI_BASE_PHY_STATE_FINAL. - This function sets the state
+ * handlers for the phy object base state machine final state. none
+ */
+static void scic_sds_phy_final_state_enter(
+ struct sci_base_object *object)
+{
+ struct scic_sds_phy *this_phy;
+
+ this_phy = (struct scic_sds_phy *)object;
+
+ scic_sds_phy_set_base_state_handlers(this_phy, SCI_BASE_PHY_STATE_FINAL);
+
+ /* Nothing to do here */
+}
+
+/* --------------------------------------------------------------------------- */
+
+const struct sci_base_state scic_sds_phy_state_table[] = {
+ [SCI_BASE_PHY_STATE_INITIAL] = {
+ .enter_state = scic_sds_phy_initial_state_enter,
+ },
+ [SCI_BASE_PHY_STATE_STOPPED] = {
+ .enter_state = scic_sds_phy_stopped_state_enter,
+ },
+ [SCI_BASE_PHY_STATE_STARTING] = {
+ .enter_state = scic_sds_phy_starting_state_enter,
+ },
+ [SCI_BASE_PHY_STATE_READY] = {
+ .enter_state = scic_sds_phy_ready_state_enter,
+ .exit_state = scic_sds_phy_ready_state_exit,
+ },
+ [SCI_BASE_PHY_STATE_RESETTING] = {
+ .enter_state = scic_sds_phy_resetting_state_enter,
+ },
+ [SCI_BASE_PHY_STATE_FINAL] = {
+ .enter_state = scic_sds_phy_final_state_enter,
+ },
+};
+
diff --git a/drivers/scsi/isci/core/scic_sds_phy.h b/drivers/scsi/isci/core/scic_sds_phy.h
new file mode 100644
index 000000000000..d9691b30e457
--- /dev/null
+++ b/drivers/scsi/isci/core/scic_sds_phy.h
@@ -0,0 +1,491 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCIC_SDS_PHY_H_
+#define _SCIC_SDS_PHY_H_
+
+/**
+ * This file contains the structures, constants and prototypes for the
+ * struct scic_sds_phy object.
+ *
+ *
+ */
+
+#include "intel_sata.h"
+#include "intel_sas.h"
+#include "sci_base_phy.h"
+#include "scu_registers.h"
+
+struct scic_sds_port;
+/**
+ *
+ *
+ * This is the timeout value for the SATA phy to wait for a SIGNATURE FIS
+ * before restarting the starting state machine. Technically, the old parallel
+ * ATA specification required up to 30 seconds for a device to issue its
+ * signature FIS as a result of a soft reset. Now we see that devices respond
+ * generally within 15 seconds, but we'll use 25 for now.
+ */
+#define SCIC_SDS_SIGNATURE_FIS_TIMEOUT 25000
+
+/**
+ *
+ *
+ * This is the timeout for the SATA OOB/SN because the hardware does not
+ * recognize a hot plug after OOB signal but before the SN signals. We need to
+ * make sure after a hotplug timeout if we have not received the speed event
+ * notification from the hardware that we restart the hardware OOB state
+ * machine.
+ */
+#define SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT 250
+
+/**
+ * enum SCIC_SDS_PHY_STARTING_SUBSTATES -
+ *
+ *
+ */
+enum SCIC_SDS_PHY_STARTING_SUBSTATES {
+ /**
+ * Initial state
+ */
+ SCIC_SDS_PHY_STARTING_SUBSTATE_INITIAL,
+
+ /**
+ * Wait state for the hardware OSSP event type notification
+ */
+ SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_OSSP_EN,
+
+ /**
+ * Wait state for the PHY speed notification
+ */
+ SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_SPEED_EN,
+
+ /**
+ * Wait state for the IAF Unsolicited frame notification
+ */
+ SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_IAF_UF,
+
+ /**
+ * Wait state for the request to consume power
+ */
+ SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_POWER,
+
+ /**
+ * Wait state for request to consume power
+ */
+ SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_POWER,
+
+ /**
+ * Wait state for the SATA PHY notification
+ */
+ SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_PHY_EN,
+
+ /**
+ * Wait for the SATA PHY speed notification
+ */
+ SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_SPEED_EN,
+
+ /**
+ * Wait state for the SIGNATURE FIS unsolicited frame notification
+ */
+ SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SIG_FIS_UF,
+
+ /**
+ * Exit state for this state machine
+ */
+ SCIC_SDS_PHY_STARTING_SUBSTATE_FINAL,
+
+ /**
+ * Maximum number of substates for the STARTING state machine
+ */
+ SCIC_SDS_PHY_STARTING_MAX_SUBSTATES
+};
+
+struct scic_sds_port;
+struct scic_sds_controller;
+
+#ifdef SCIC_DEBUG_ENABLED
+#define MAX_STATE_TRANSITION_RECORD (256)
+
+/**
+ *
+ *
+ * Debug code to record the state transitions for the phy object
+ */
+struct scic_sds_phy_state_record {
+ struct sci_base_observer base_state_observer;
+ struct sci_base_observer starting_state_observer;
+
+ u16 index;
+
+ u32 state_transition_table[MAX_STATE_TRANSITION_RECORD];
+
+};
+#endif /* SCIC_DEBUG_ENABLED */
+
+/**
+ * This enumeration provides a named phy type for the state machine
+ *
+ *
+ */
+enum SCIC_SDS_PHY_PROTOCOL {
+ /**
+ * This is an unknown phy type since there is either nothing on the other
+ * end or we have not detected the phy type as yet.
+ */
+ SCIC_SDS_PHY_PROTOCOL_UNKNOWN,
+
+ /**
+ * This is a SAS PHY
+ */
+ SCIC_SDS_PHY_PROTOCOL_SAS,
+
+ /**
+ * This is a SATA PHY
+ */
+ SCIC_SDS_PHY_PROTOCOL_SATA,
+
+ SCIC_SDS_MAX_PHY_PROTOCOLS
+};
+
+/**
+ * struct scic_sds_phy - This structure contains or references all of the data
+ * necessary to represent the core phy object and SCU harware protocol
+ * engine.
+ *
+ *
+ */
+struct scic_sds_phy {
+ struct sci_base_phy parent;
+
+ /**
+ * This field specifies the port object that owns/contains this phy.
+ */
+ struct scic_sds_port *owning_port;
+
+ /**
+ * This field indicates whether the phy supports 1.5 Gb/s, 3.0 Gb/s,
+ * or 6.0 Gb/s operation.
+ */
+ enum sci_sas_link_rate max_negotiated_speed;
+
+ /**
+ * This member specifies the protocol being utilized on this phy. This
+ * field contains a legitamite value once the PHY has link trained with
+ * a remote phy.
+ */
+ enum SCIC_SDS_PHY_PROTOCOL protocol;
+
+ /**
+ * This field specifies the index with which this phy is associated (0-3).
+ */
+ u8 phy_index;
+
+ /**
+ * This member indicates if this particular PHY has received a BCN while
+ * it had no port assignement. This BCN will be reported once the phy is
+ * assigned to a port.
+ */
+ bool bcn_received_while_port_unassigned;
+
+ /**
+ * This field indicates if this PHY is currently in the process of
+ * link training (i.e. it has started OOB, but has yet to perform
+ * IAF exchange/Signature FIS reception).
+ */
+ bool is_in_link_training;
+
+ union {
+ struct {
+ struct sci_sas_identify_address_frame identify_address_frame_buffer;
+
+ } sas;
+
+ struct {
+ struct sata_fis_reg_d2h signature_fis_buffer;
+
+ } sata;
+
+ } phy_type;
+
+ /**
+ * This field contains a reference to the timer utilized in detecting
+ * when a signature FIS timeout has occurred. The signature FIS is the
+ * first FIS sent by an attached SATA device after OOB/SN.
+ */
+ void *sata_timeout_timer;
+
+ struct scic_sds_phy_state_handler *state_handlers;
+
+ struct sci_base_state_machine starting_substate_machine;
+
+ #ifdef SCIC_DEBUG_ENABLED
+ struct scic_sds_phy_state_record state_record;
+ #endif /* SCIC_DEBUG_ENABLED */
+
+ /**
+ * This field points to the link layer register set within the SCU.
+ */
+ struct scu_link_layer_registers *link_layer_registers;
+
+};
+
+
+typedef enum sci_status (*SCIC_SDS_PHY_EVENT_HANDLER_T)(struct scic_sds_phy *, u32);
+typedef enum sci_status (*SCIC_SDS_PHY_FRAME_HANDLER_T)(struct scic_sds_phy *, u32);
+typedef enum sci_status (*SCIC_SDS_PHY_POWER_HANDLER_T)(struct scic_sds_phy *);
+
+/**
+ * struct scic_sds_phy_state_handler -
+ *
+ *
+ */
+struct scic_sds_phy_state_handler {
+ /**
+ * This is the struct sci_base_phy object state handlers.
+ */
+ struct sci_base_phy_state_handler parent;
+
+ /**
+ * The state handler for unsolicited frames received from the SCU hardware.
+ */
+ SCIC_SDS_PHY_FRAME_HANDLER_T frame_handler;
+
+ /**
+ * The state handler for events received from the SCU hardware.
+ */
+ SCIC_SDS_PHY_EVENT_HANDLER_T event_handler;
+
+ /**
+ * The state handler for staggered spinup.
+ */
+ SCIC_SDS_PHY_POWER_HANDLER_T consume_power_handler;
+
+};
+
+extern struct scic_sds_phy_state_handler scic_sds_phy_state_handler_table[];
+extern const struct sci_base_state scic_sds_phy_state_table[];
+extern const struct sci_base_state scic_sds_phy_starting_substates[];
+extern struct scic_sds_phy_state_handler
+ scic_sds_phy_starting_substate_handler_table[];
+
+
+/**
+ * scic_sds_phy_get_index() -
+ *
+ * This macro returns the phy index for the specified phy
+ */
+#define scic_sds_phy_get_index(phy) \
+ ((phy)->phy_index)
+
+/**
+ * scic_sds_phy_get_controller() - This macro returns the controller for this
+ * phy
+ *
+ *
+ */
+#define scic_sds_phy_get_controller(phy) \
+ (scic_sds_port_get_controller((phy)->owning_port))
+
+/**
+ * scic_sds_phy_get_base_state_machine() - This macro returns the state machine
+ * for the base phy
+ *
+ *
+ */
+#define scic_sds_phy_get_base_state_machine(phy) \
+ (&(phy)->parent.state_machine)
+
+/**
+ * scic_sds_phy_get_starting_substate_machine() - This macro returns the
+ * starting substate machine for this phy
+ *
+ *
+ */
+#define scic_sds_phy_get_starting_substate_machine(phy) \
+ (&(phy)->starting_substate_machine)
+
+/**
+ * scic_sds_phy_set_state_handlers() - This macro sets the state handlers for
+ * this phy object
+ *
+ *
+ */
+#define scic_sds_phy_set_state_handlers(phy, handlers) \
+ ((phy)->state_handlers = (handlers))
+
+/**
+ * scic_sds_phy_set_base_state_handlers() -
+ *
+ * This macro set the base state handlers for the phy object.
+ */
+#define scic_sds_phy_set_base_state_handlers(phy, state_id) \
+ scic_sds_phy_set_state_handlers(\
+ (phy), \
+ &scic_sds_phy_state_handler_table[(state_id)] \
+ )
+
+/**
+ * scic_sds_phy_is_ready() -
+ *
+ * This macro returns true if the current base state for this phy is
+ * SCI_BASE_PHY_STATE_READY
+ */
+#define scic_sds_phy_is_ready(phy) \
+ (\
+ SCI_BASE_PHY_STATE_READY \
+ == sci_base_state_machine_get_state(\
+ scic_sds_phy_get_base_state_machine(phy) \
+ ) \
+ )
+
+/* --------------------------------------------------------------------------- */
+
+
+
+
+/* --------------------------------------------------------------------------- */
+
+void scic_sds_phy_construct(
+ struct scic_sds_phy *this_phy,
+ struct scic_sds_port *owning_port,
+ u8 phy_index);
+
+struct scic_sds_port *scic_sds_phy_get_port(
+ struct scic_sds_phy *this_phy);
+
+void scic_sds_phy_set_port(
+ struct scic_sds_phy *this_phy,
+ struct scic_sds_port *owning_port);
+
+enum sci_status scic_sds_phy_initialize(
+ struct scic_sds_phy *this_phy,
+ struct scu_link_layer_registers *link_layer_registers);
+
+enum sci_status scic_sds_phy_start(
+ struct scic_sds_phy *this_phy);
+
+enum sci_status scic_sds_phy_stop(
+ struct scic_sds_phy *this_phy);
+
+enum sci_status scic_sds_phy_reset(
+ struct scic_sds_phy *this_phy);
+
+/* --------------------------------------------------------------------------- */
+
+void scic_sds_phy_suspend(