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authorTom Cherry <tcherry@nvidia.com>2012-05-30 18:18:17 -0700
committerTom Cherry <tcherry@nvidia.com>2012-05-30 18:18:17 -0700
commit7af2c7ce772882f6e85e2a357711bf822f066bfa (patch)
tree2a1307a8096a62d4252a7c382f43204da3325401
parentd92da78335899834f8f667eb7c865aaf47bdff48 (diff)
parentc9d3eda2af45736e73f0dfd2261257e083f3758a (diff)
Merge commit 'main-ics-2012.05.30-A1' into dev-jb-staging
-rw-r--r--arch/arm/configs/tegra3_android_defconfig1
-rw-r--r--arch/arm/mach-tegra/Kconfig9
-rw-r--r--arch/arm/mach-tegra/Makefile2
-rw-r--r--arch/arm/mach-tegra/baseband-xmm-power.c1
-rw-r--r--arch/arm/mach-tegra/board-cardhu-kbc.c8
-rw-r--r--arch/arm/mach-tegra/board-cardhu-panel.c45
-rw-r--r--arch/arm/mach-tegra/board-cardhu-pinmux.c5
-rw-r--r--arch/arm/mach-tegra/board-cardhu-pm298-power-rails.c7
-rw-r--r--arch/arm/mach-tegra/board-cardhu-pm299-power-rails.c7
-rw-r--r--arch/arm/mach-tegra/board-cardhu-power.c11
-rw-r--r--arch/arm/mach-tegra/board-cardhu-sdhci.c4
-rw-r--r--arch/arm/mach-tegra/board-cardhu-sensors.c74
-rw-r--r--arch/arm/mach-tegra/board-cardhu.c400
-rw-r--r--arch/arm/mach-tegra/board-enterprise-baseband.c62
-rw-r--r--arch/arm/mach-tegra/board-enterprise.c260
-rw-r--r--arch/arm/mach-tegra/board-harmony-pcie.c3
-rw-r--r--arch/arm/mach-tegra/board-harmony.c94
-rw-r--r--arch/arm/mach-tegra/board-kai.c147
-rw-r--r--arch/arm/mach-tegra/board-p1852.c174
-rw-r--r--arch/arm/mach-tegra/board-trimslice.c3
-rw-r--r--arch/arm/mach-tegra/board-ventana.c207
-rw-r--r--arch/arm/mach-tegra/board-whistler-baseband.c62
-rw-r--r--arch/arm/mach-tegra/board-whistler-sdhci.c4
-rw-r--r--arch/arm/mach-tegra/board-whistler.c118
-rw-r--r--arch/arm/mach-tegra/common-t2.c6
-rw-r--r--arch/arm/mach-tegra/common.c6
-rw-r--r--arch/arm/mach-tegra/devices.c31
-rw-r--r--arch/arm/mach-tegra/include/mach/dc.h1
-rw-r--r--arch/arm/mach-tegra/include/mach/latency_allowance.h4
-rw-r--r--arch/arm/mach-tegra/include/mach/usb_phy.h238
-rw-r--r--arch/arm/mach-tegra/iovmm-gart.c6
-rw-r--r--arch/arm/mach-tegra/p852/board-p852.c140
-rw-r--r--arch/arm/mach-tegra/pcie.c191
-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c39
-rw-r--r--arch/arm/mach-tegra/tegra2_mc.c6
-rw-r--r--arch/arm/mach-tegra/tegra2_usb_phy.c1598
-rw-r--r--arch/arm/mach-tegra/tegra3_clocks.c8
-rw-r--r--arch/arm/mach-tegra/tegra3_usb_phy.c2409
-rw-r--r--arch/arm/mach-tegra/tegra_usb_phy.h104
-rw-r--r--arch/arm/mach-tegra/usb_phy.c3391
-rw-r--r--chromeos/config/armel/config.common.armel528
-rw-r--r--chromeos/config/armel/config.flavour.chromeos-tegra3125
-rw-r--r--chromeos/config/armel/config.flavour.chromiumos-arm86
-rw-r--r--chromeos/config/config.common.chromeos2039
-rw-r--r--chromeos/config/i386/config.common.i386749
l---------chromeos/config/i386/config.flavour.chromeos-intel-menlow1
-rw-r--r--chromeos/config/i386/config.flavour.chromeos-pinetrail-i38641
-rw-r--r--chromeos/config/i386/config.flavour.chromiumos-i38685
-rw-r--r--chromeos/config/x86_64/config.common.x86_64740
-rw-r--r--chromeos/config/x86_64/config.flavour.chromeos-intel-pineview3
-rwxr-xr-xchromeos/scripts/allconfigs28
-rwxr-xr-xchromeos/scripts/kernelconfig123
-rwxr-xr-xchromeos/scripts/prepareconfig18
-rwxr-xr-xchromeos/scripts/splitconfig49
-rw-r--r--drivers/ata/Kconfig17
-rw-r--r--drivers/ata/Makefile1
-rw-r--r--drivers/ata/ahci-tegra.c2154
-rw-r--r--drivers/i2c/busses/i2c-tegra.c18
-rw-r--r--drivers/media/video/tegra/Kconfig7
-rw-r--r--drivers/media/video/tegra/Makefile1
-rw-r--r--drivers/media/video/tegra/ad5816.c1204
-rw-r--r--drivers/mfd/tps80031.c20
-rw-r--r--drivers/misc/tegra-baseband/bb-m7400.c15
-rw-r--r--drivers/mmc/host/sdhci-tegra.c16
-rw-r--r--drivers/net/wireless/bcm4329/wl_iw.c27
-rw-r--r--drivers/spi/spi-tegra.c405
-rw-r--r--drivers/usb/gadget/Makefile1
-rw-r--r--drivers/usb/gadget/android.c8
-rw-r--r--drivers/usb/gadget/fsl_tegra_udc.c170
-rw-r--r--drivers/usb/gadget/tegra_udc.c141
-rw-r--r--drivers/usb/host/ehci-hub.c12
-rw-r--r--drivers/usb/host/ehci-tegra.c1366
-rw-r--r--drivers/usb/host/ehci.h1
-rw-r--r--drivers/usb/otg/tegra-otg.c153
-rw-r--r--drivers/video/tegra/dc/dc.c17
-rw-r--r--drivers/video/tegra/dc/dc_reg.h2
-rw-r--r--drivers/video/tegra/dc/dsi.c17
-rw-r--r--drivers/video/tegra/fb.c12
-rw-r--r--drivers/video/tegra/host/bus_client.c56
-rw-r--r--drivers/video/tegra/host/chip_support.h12
-rw-r--r--drivers/video/tegra/host/debug.c67
-rw-r--r--drivers/video/tegra/host/gr3d/gr3d_t20.c2
-rw-r--r--drivers/video/tegra/host/gr3d/gr3d_t30.c2
-rw-r--r--drivers/video/tegra/host/host1x/host1x_cdma.c2
-rw-r--r--drivers/video/tegra/host/host1x/host1x_channel.c20
-rw-r--r--drivers/video/tegra/host/host1x/host1x_debug.c132
-rw-r--r--drivers/video/tegra/host/host1x/host1x_syncpt.c64
-rw-r--r--drivers/video/tegra/host/mpe/mpe.c2
-rw-r--r--drivers/video/tegra/host/nvhost_cdma.c45
-rw-r--r--drivers/video/tegra/host/nvhost_cdma.h7
-rw-r--r--drivers/video/tegra/host/nvhost_channel.c24
-rw-r--r--drivers/video/tegra/host/nvhost_channel.h8
-rw-r--r--drivers/video/tegra/host/nvhost_intr.c10
-rw-r--r--drivers/video/tegra/host/nvhost_job.c347
-rw-r--r--drivers/video/tegra/host/nvhost_job.h37
-rw-r--r--drivers/video/tegra/host/nvhost_syncpt.c30
-rw-r--r--drivers/video/tegra/host/nvhost_syncpt.h18
-rw-r--r--drivers/video/tegra/host/t30/t30.c2
-rw-r--r--drivers/video/tegra/nvmap/nvmap.c268
-rw-r--r--drivers/video/tegra/nvmap/nvmap.h86
-rw-r--r--drivers/video/tegra/nvmap/nvmap_dev.c19
-rw-r--r--drivers/video/tegra/nvmap/nvmap_handle.c73
-rw-r--r--include/linux/nvmap.h56
-rw-r--r--include/linux/platform_data/tegra_usb.h139
-rw-r--r--include/media/ad5816.h81
-rw-r--r--include/trace/events/nvhost.h95
-rw-r--r--security/tf_driver/Makefile2
-rw-r--r--security/tf_driver/s_version.h4
-rw-r--r--security/tf_driver/tf_comm_tz.c18
-rw-r--r--security/tf_driver/tf_protocol.h4
-rw-r--r--sound/soc/tegra/Makefile2
-rw-r--r--sound/soc/tegra/tegra20_das.c6
-rw-r--r--sound/soc/tegra/tegra20_das.h4
-rw-r--r--sound/soc/tegra/tegra_aic326x.c4
-rw-r--r--sound/soc/tegra/tegra_asoc_utils.c138
-rw-r--r--sound/soc/tegra/tegra_asoc_utils.h4
-rw-r--r--sound/soc/tegra/tegra_max98088.c4
-rw-r--r--sound/soc/tegra/tegra_max98095.c4
-rw-r--r--sound/soc/tegra/tegra_p1852.c42
-rw-r--r--sound/soc/tegra/tegra_pcm.c18
-rw-r--r--sound/soc/tegra/tegra_pcm.h1
-rw-r--r--sound/soc/tegra/tegra_rt5640.c5
-rw-r--r--sound/soc/tegra/tegra_wm8753.c5
-rw-r--r--sound/soc/tegra/tegra_wm8903.c4
124 files changed, 15562 insertions, 6697 deletions
diff --git a/arch/arm/configs/tegra3_android_defconfig b/arch/arm/configs/tegra3_android_defconfig
index ba20b0e..2b4aee1 100644
--- a/arch/arm/configs/tegra3_android_defconfig
+++ b/arch/arm/configs/tegra3_android_defconfig
@@ -340,6 +340,7 @@ CONFIG_VIDEO_AR0832=y
CONFIG_TORCH_SSL3250A=y
CONFIG_TORCH_TPS61050=y
CONFIG_VIDEO_SH532U=y
+CONFIG_VIDEO_AD5816=y
CONFIG_USB_VIDEO_CLASS=y
# CONFIG_USB_GSPCA is not set
# CONFIG_RADIO_ADAPTERS is not set
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 1aa448c..82306bc 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -22,6 +22,7 @@ config ARCH_TEGRA_2x_SOC
select PCI_MSI if TEGRA_PCI
select CPA
select ARM_ERRATA_716044
+ select ARM_ERRATA_764369 if SMP
select ARCH_HAS_SUSPEND_PAGETABLE
help
Support for NVIDIA Tegra AP20 and T20 processors, based on the
@@ -46,6 +47,7 @@ config ARCH_TEGRA_3x_SOC
select ARCH_SUPPORTS_MSI if TEGRA_PCI
select PCI_MSI if TEGRA_PCI
select ARM_ERRATA_754322
+ select ARM_ERRATA_764369 if SMP
select TEGRA_LP2_ARM_TWD if HAVE_ARM_TWD && !TEGRA_RAIL_OFF_MULTIPLE_CPUS
select CPA
select ARCH_HAS_SUSPEND_PAGETABLE
@@ -259,6 +261,13 @@ config TEGRA_CARDHU_DSI
help
Support for DSI Panel on Nvidia Cardhu
+config TEGRA_CARDHU_DUAL_DSI_PANEL
+ bool "Support Dual DSI panel on Cardhu"
+ default n
+ depends on TEGRA_CARDHU_DSI
+ help
+ Support for Dual DSI Panel on Nvidia Cardhu
+
config TEGRA_EMC_SCALING_ENABLE
bool "Enable scaling the memory frequency"
depends on TEGRA_SILICON_PLATFORM
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 6b1c4c5..3153203 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -44,6 +44,8 @@ obj-y += i2c_error_recovery.o
obj-y += mc.o
obj-$(CONFIG_TEGRA_STAT_MON) += tegra2_statmon.o
obj-$(CONFIG_USB_SUPPORT) += usb_phy.o
+obj-$(CONFIG_USB_SUPPORT) += tegra3_usb_phy.o
+obj-$(CONFIG_USB_SUPPORT) += tegra2_usb_phy.o
obj-$(CONFIG_FIQ) += fiq.o
obj-$(CONFIG_TEGRA_FIQ_DEBUGGER) += tegra_fiq_debugger.o
obj-$(CONFIG_TEGRA_PWM) += pwm.o
diff --git a/arch/arm/mach-tegra/baseband-xmm-power.c b/arch/arm/mach-tegra/baseband-xmm-power.c
index 20f8d30..4da5d41 100644
--- a/arch/arm/mach-tegra/baseband-xmm-power.c
+++ b/arch/arm/mach-tegra/baseband-xmm-power.c
@@ -33,6 +33,7 @@
#include <linux/suspend.h>
#include <linux/pm_qos_params.h>
#include <mach/usb_phy.h>
+#include <linux/regulator/consumer.h>
#include "board.h"
#include "board-enterprise.h"
#include "devices.h"
diff --git a/arch/arm/mach-tegra/board-cardhu-kbc.c b/arch/arm/mach-tegra/board-cardhu-kbc.c
index 16e83bb..c397140 100644
--- a/arch/arm/mach-tegra/board-cardhu-kbc.c
+++ b/arch/arm/mach-tegra/board-cardhu-kbc.c
@@ -196,8 +196,8 @@ static struct gpio_keys_button cardhu_int_keys[] = {
};
static struct gpio_keys_button cardhu_pm298_int_keys[] = {
- [0] = GPIO_IKEY(KEY_POWER, MAX77663_IRQ_BASE + MAX77663_IRQ_ONOFF_EN0_FALLING, 1, 100),
- [1] = GPIO_IKEY(KEY_POWER, MAX77663_IRQ_BASE + MAX77663_IRQ_ONOFF_EN0_1SEC, 1, 3000),
+ [0] = GPIO_IKEY(KEY_POWER, MAX77663_IRQ_BASE + MAX77663_IRQ_ONOFF_EN0_FALLING, 0, 100),
+ [1] = GPIO_IKEY(KEY_POWER, MAX77663_IRQ_BASE + MAX77663_IRQ_ONOFF_EN0_1SEC, 0, 3000),
};
static struct gpio_keys_button cardhu_pm299_int_keys[] = {
@@ -252,8 +252,6 @@ int __init cardhu_keys_init(void)
if (get_tegra_image_type() == rck_image)
cardhu_keys_e1291_pdata.buttons[i].code
= KEY_ENTER;
- } else {
- tegra_gpio_enable(gpio_nr);
}
}
@@ -265,8 +263,6 @@ int __init cardhu_keys_init(void)
if (gpio_nr < 0) {
if (get_tegra_image_type() == rck_image)
cardhu_keys_e1198[i].code = KEY_ENTER;
- } else {
- tegra_gpio_enable(gpio_nr);
}
}
diff --git a/arch/arm/mach-tegra/board-cardhu-panel.c b/arch/arm/mach-tegra/board-cardhu-panel.c
index 4899dee..a621710 100644
--- a/arch/arm/mach-tegra/board-cardhu-panel.c
+++ b/arch/arm/mach-tegra/board-cardhu-panel.c
@@ -144,8 +144,6 @@ static int cardhu_backlight_init(struct device *dev)
pr_err("bl_output array does not have 256 elements\n");
#ifndef CONFIG_TEGRA_CARDHU_DSI
- tegra_gpio_disable(cardhu_bl_pwm);
-
ret = gpio_request(cardhu_bl_enb, "backlight_enb");
if (ret < 0)
return ret;
@@ -153,8 +151,6 @@ static int cardhu_backlight_init(struct device *dev)
ret = gpio_direction_output(cardhu_bl_enb, 1);
if (ret < 0)
gpio_free(cardhu_bl_enb);
- else
- tegra_gpio_enable(cardhu_bl_enb);
return ret;
#endif
@@ -168,8 +164,6 @@ static int cardhu_backlight_init(struct device *dev)
ret = gpio_direction_output(cardhu_dsia_bl_enb, 1);
if (ret < 0)
gpio_free(cardhu_dsia_bl_enb);
- else
- tegra_gpio_enable(cardhu_dsia_bl_enb);
/* Enable back light for DSIb panel */
ret = gpio_request(cardhu_dsib_bl_enb, "dsib_bl_enable");
@@ -179,8 +173,6 @@ static int cardhu_backlight_init(struct device *dev)
ret = gpio_direction_output(cardhu_dsib_bl_enb, 1);
if (ret < 0)
gpio_free(cardhu_dsib_bl_enb);
- else
- tegra_gpio_enable(cardhu_dsib_bl_enb);
#endif
#if DSI_PANEL_219
@@ -192,8 +184,6 @@ static int cardhu_backlight_init(struct device *dev)
ret = gpio_direction_output(cardhu_dsia_bl_enb, 1);
if (ret < 0)
gpio_free(cardhu_dsia_bl_enb);
- else
- tegra_gpio_enable(cardhu_dsia_bl_enb);
#endif
return ret;
@@ -206,7 +196,6 @@ static void cardhu_backlight_exit(struct device *dev)
/*ret = gpio_request(cardhu_bl_enb, "backlight_enb");*/
gpio_set_value(cardhu_bl_enb, 0);
gpio_free(cardhu_bl_enb);
- tegra_gpio_disable(cardhu_bl_enb);
return;
#endif
@@ -214,12 +203,11 @@ static void cardhu_backlight_exit(struct device *dev)
/* Disable back light for DSIa panel */
gpio_set_value(cardhu_dsia_bl_enb, 0);
gpio_free(cardhu_dsia_bl_enb);
- tegra_gpio_disable(cardhu_dsia_bl_enb);
+
/* Disable back light for DSIb panel */
gpio_set_value(cardhu_dsib_bl_enb, 0);
gpio_free(cardhu_dsib_bl_enb);
- tegra_gpio_disable(cardhu_dsib_bl_enb);
gpio_set_value(cardhu_lvds_shutdown, 1);
mdelay(20);
@@ -229,7 +217,7 @@ static void cardhu_backlight_exit(struct device *dev)
/* Disable back light for DSIa panel */
gpio_set_value(cardhu_dsia_bl_enb, 0);
gpio_free(cardhu_dsia_bl_enb);
- tegra_gpio_disable(cardhu_dsia_bl_enb);
+
gpio_set_value(cardhu_lvds_shutdown, 1);
mdelay(20);
@@ -762,8 +750,6 @@ static int cardhu_dsi_panel_enable(void)
ret = gpio_direction_output(AVDD_LCD, 1);
if (ret < 0)
gpio_free(AVDD_LCD);
- else
- tegra_gpio_enable(AVDD_LCD);
#if DSI_PANEL_219
@@ -774,8 +760,7 @@ static int cardhu_dsi_panel_enable(void)
if (ret < 0) {
gpio_free(cardhu_bl_pwm);
return ret;
- } else
- tegra_gpio_enable(cardhu_bl_pwm);
+ }
ret = gpio_request(cardhu_bl_enb, "bl_enb");
if (ret < 0)
@@ -784,8 +769,7 @@ static int cardhu_dsi_panel_enable(void)
if (ret < 0) {
gpio_free(cardhu_bl_enb);
return ret;
- } else
- tegra_gpio_enable(cardhu_bl_enb);
+ }
gpio_set_value(cardhu_lvds_shutdown, 1);
mdelay(20);
@@ -805,8 +789,7 @@ static int cardhu_dsi_panel_enable(void)
if (ret < 0) {
gpio_free(cardhu_dsi_218_panel_reset);
return ret;
- } else
- tegra_gpio_enable(cardhu_dsi_218_panel_reset);
+ }
gpio_set_value(cardhu_dsi_218_panel_reset, 1);
gpio_set_value(cardhu_dsi_218_panel_reset, 0);
@@ -823,8 +806,7 @@ static int cardhu_dsi_panel_enable(void)
if (ret < 0) {
gpio_free(cardhu_dsi_219_panel_reset);
return ret;
- } else
- tegra_gpio_enable(cardhu_dsi_219_panel_reset);
+ }
gpio_set_value(cardhu_dsi_219_panel_reset, 0);
gpio_set_value(cardhu_dsi_219_panel_reset, 1);
@@ -847,18 +829,13 @@ static int cardhu_dsi_panel_disable(void)
printk(KERN_INFO "DSI panel disable\n");
#if DSI_PANEL_219
- tegra_gpio_disable(cardhu_dsi_219_panel_reset);
gpio_free(cardhu_dsi_219_panel_reset);
- tegra_gpio_disable(cardhu_bl_enb);
gpio_free(cardhu_bl_enb);
- tegra_gpio_disable(cardhu_bl_pwm);
gpio_free(cardhu_bl_pwm);
- tegra_gpio_disable(cardhu_lvds_shutdown);
gpio_free(cardhu_lvds_shutdown);
#endif
#if DSI_PANEL_218
- tegra_gpio_disable(cardhu_dsi_218_panel_reset);
gpio_free(cardhu_dsi_218_panel_reset);
#endif
@@ -882,7 +859,6 @@ static int cardhu_dsi_panel_postsuspend(void)
}
#if DSI_PANEL_218
- tegra_gpio_disable(AVDD_LCD);
gpio_free(AVDD_LCD);
#endif
@@ -1222,28 +1198,22 @@ int __init cardhu_panel_init(void)
/* lvds configuration */
err = gpio_request(pm313_R_FDE, "R_FDE");
err |= gpio_direction_output(pm313_R_FDE, 1);
- tegra_gpio_enable(pm313_R_FDE);
err |= gpio_request(pm313_R_FB, "R_FB");
err |= gpio_direction_output(pm313_R_FB, 1);
- tegra_gpio_enable(pm313_R_FB);
err |= gpio_request(pm313_MODE0, "MODE0");
err |= gpio_direction_output(pm313_MODE0, 1);
- tegra_gpio_enable(pm313_MODE0);
err |= gpio_request(pm313_MODE1, "MODE1");
err |= gpio_direction_output(pm313_MODE1, 0);
- tegra_gpio_enable(pm313_MODE1);
err |= gpio_request(pm313_BPP, "BPP");
err |= gpio_direction_output(pm313_BPP, PM313_LVDS_PANEL_BPP);
- tegra_gpio_enable(pm313_BPP);
err = gpio_request(pm313_lvds_shutdown, "lvds_shutdown");
/* free ride provided by bootloader */
err |= gpio_direction_output(pm313_lvds_shutdown, 1);
- tegra_gpio_enable(pm313_lvds_shutdown);
if (err)
printk(KERN_ERR "ERROR(s) in LVDS configuration\n");
@@ -1254,15 +1224,12 @@ int __init cardhu_panel_init(void)
(board_info.board_id == BOARD_PM311)) {
gpio_request(e1247_pm269_lvds_shutdown, "lvds_shutdown");
gpio_direction_output(e1247_pm269_lvds_shutdown, 1);
- tegra_gpio_enable(e1247_pm269_lvds_shutdown);
} else {
gpio_request(cardhu_lvds_shutdown, "lvds_shutdown");
gpio_direction_output(cardhu_lvds_shutdown, 1);
- tegra_gpio_enable(cardhu_lvds_shutdown);
}
#endif
- tegra_gpio_enable(cardhu_hdmi_hpd);
gpio_request(cardhu_hdmi_hpd, "hdmi_hpd");
gpio_direction_input(cardhu_hdmi_hpd);
diff --git a/arch/arm/mach-tegra/board-cardhu-pinmux.c b/arch/arm/mach-tegra/board-cardhu-pinmux.c
index fd0a6ae..05e2179 100644
--- a/arch/arm/mach-tegra/board-cardhu-pinmux.c
+++ b/arch/arm/mach-tegra/board-cardhu-pinmux.c
@@ -472,7 +472,6 @@ static __initdata struct tegra_pingroup_config cardhu_pinmux_cardhu_a03[] = {
static __initdata struct tegra_pingroup_config cardhu_pinmux_e1291_a04[] = {
DEFAULT_PINMUX(GMI_AD15, NAND, PULL_DOWN, NORMAL, OUTPUT),
- DEFAULT_PINMUX(ULPI_DATA5, UARTA, PULL_UP, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(SPI2_MOSI, SPI6, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(DAP3_SCLK, RSVD1, NORMAL, NORMAL, OUTPUT),
@@ -544,11 +543,8 @@ static __initdata struct tegra_pingroup_config gmi_pins_269[] = {
static void __init cardhu_pinmux_audio_init(void)
{
- tegra_gpio_enable(TEGRA_GPIO_CDC_IRQ);
gpio_request(TEGRA_GPIO_CDC_IRQ, "wm8903");
gpio_direction_input(TEGRA_GPIO_CDC_IRQ);
-
- tegra_gpio_enable(TEGRA_GPIO_HP_DET);
}
#define GPIO_INIT_PIN_MODE(_gpio, _is_input, _value) \
@@ -755,7 +751,6 @@ static void set_unused_pin_gpio(struct gpio_init_pin_info *lpm_pin_info,
gpio_free(pin_info->gpio_nr);
continue;
}
- tegra_gpio_enable(pin_info->gpio_nr);
}
}
diff --git a/arch/arm/mach-tegra/board-cardhu-pm298-power-rails.c b/arch/arm/mach-tegra/board-cardhu-pm298-power-rails.c
index 0305ee7..f0dc8af 100644
--- a/arch/arm/mach-tegra/board-cardhu-pm298-power-rails.c
+++ b/arch/arm/mach-tegra/board-cardhu-pm298-power-rails.c
@@ -698,12 +698,5 @@ int __init cardhu_pm298_gpio_switch_regulator_init(void)
break;
}
- for (i = 0; i < nfixreg_devs; ++i) {
- struct fixed_voltage_config *fixed_reg_pdata =
- fixed_reg_devs[i]->dev.platform_data;
- int gpio_nr = fixed_reg_pdata->gpio;
- if (gpio_nr < TEGRA_NR_GPIOS)
- tegra_gpio_enable(gpio_nr);
- }
return platform_add_devices(fixed_reg_devs, nfixreg_devs);
}
diff --git a/arch/arm/mach-tegra/board-cardhu-pm299-power-rails.c b/arch/arm/mach-tegra/board-cardhu-pm299-power-rails.c
index 0c55aa4..6d4db73 100644
--- a/arch/arm/mach-tegra/board-cardhu-pm299-power-rails.c
+++ b/arch/arm/mach-tegra/board-cardhu-pm299-power-rails.c
@@ -688,12 +688,5 @@ int __init cardhu_pm299_gpio_switch_regulator_init(void)
break;
}
- for (i = 0; i < nfixreg_devs; ++i) {
- struct fixed_voltage_config *fixed_reg_pdata =
- fixed_reg_devs[i]->dev.platform_data;
- int gpio_nr = fixed_reg_pdata->gpio;
- if (gpio_nr < TEGRA_NR_GPIOS)
- tegra_gpio_enable(gpio_nr);
- }
return platform_add_devices(fixed_reg_devs, nfixreg_devs);
}
diff --git a/arch/arm/mach-tegra/board-cardhu-power.c b/arch/arm/mach-tegra/board-cardhu-power.c
index 79d8d61..61b5a15 100644
--- a/arch/arm/mach-tegra/board-cardhu-power.c
+++ b/arch/arm/mach-tegra/board-cardhu-power.c
@@ -1,7 +1,7 @@
/*
* arch/arm/mach-tegra/board-cardhu-power.c
*
- * Copyright (C) 2011 NVIDIA, Inc.
+ * Copyright (C) 2011-2012 NVIDIA, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -604,6 +604,7 @@ static struct regulator_consumer_supply fixed_reg_en_vdd_pnl1_supply[] = {
static struct regulator_consumer_supply fixed_reg_cam1_ldo_en_supply[] = {
REGULATOR_SUPPLY("vdd_2v8_cam1", NULL),
REGULATOR_SUPPLY("avdd", "6-0072"),
+ REGULATOR_SUPPLY("vdd", "6-000e"),
};
/* CAM2_LDO_EN from AP GPIO KB_ROW7 R07*/
@@ -649,6 +650,7 @@ static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = {
REGULATOR_SUPPLY("vdd_1v8_cam3", NULL),
REGULATOR_SUPPLY("dvdd", "6-0072"),
REGULATOR_SUPPLY("dvdd", "7-0072"),
+ REGULATOR_SUPPLY("vdd_i2c", "6-000e"),
REGULATOR_SUPPLY("vdd_i2c", "2-0033"),
};
@@ -1072,13 +1074,6 @@ int __init cardhu_fixed_regulator_init(void)
break;
}
- for (i = 0; i < nfixreg_devs; ++i) {
- struct fixed_voltage_config *fixed_reg_pdata =
- fixed_reg_devs[i]->dev.platform_data;
- int gpio_nr = fixed_reg_pdata->gpio;
- if (gpio_nr < TEGRA_NR_GPIOS)
- tegra_gpio_enable(gpio_nr);
- }
return platform_add_devices(fixed_reg_devs, nfixreg_devs);
}
subsys_initcall_sync(cardhu_fixed_regulator_init);
diff --git a/arch/arm/mach-tegra/board-cardhu-sdhci.c b/arch/arm/mach-tegra/board-cardhu-sdhci.c
index c4e631dd..cb0684bc 100644
--- a/arch/arm/mach-tegra/board-cardhu-sdhci.c
+++ b/arch/arm/mach-tegra/board-cardhu-sdhci.c
@@ -280,10 +280,6 @@ static int __init cardhu_wifi_init(void)
if (rc)
pr_err("WLAN_WOW gpio request failed:%d\n", rc);
- tegra_gpio_enable(CARDHU_WLAN_PWR);
- tegra_gpio_enable(CARDHU_WLAN_RST);
- tegra_gpio_enable(CARDHU_WLAN_WOW);
-
rc = gpio_direction_output(CARDHU_WLAN_PWR, 0);
if (rc)
pr_err("WLAN_PWR gpio direction configuration failed:%d\n", rc);
diff --git a/arch/arm/mach-tegra/board-cardhu-sensors.c b/arch/arm/mach-tegra/board-cardhu-sensors.c
index 66b3c9d..042f740 100644
--- a/arch/arm/mach-tegra/board-cardhu-sensors.c
+++ b/arch/arm/mach-tegra/board-cardhu-sensors.c
@@ -49,6 +49,7 @@
#include "board.h"
#include <linux/mpu.h>
#include <media/sh532u.h>
+#include <media/ad5816.h>
#include <linux/bq27x00.h>
#include <mach/gpio.h>
#include <mach/edp.h>
@@ -87,24 +88,20 @@ static int cardhu_camera_init(void)
* and donot have TCA6416 exp for camera */
if ((board_info.board_id == BOARD_E1198) ||
(board_info.board_id == BOARD_E1291)) {
- tegra_gpio_enable(CAM1_POWER_DWN_GPIO);
ret = gpio_request(CAM1_POWER_DWN_GPIO, "camera_power_en");
if (ret < 0)
pr_err("%s: gpio_request failed for gpio %s\n",
__func__, "CAM1_POWER_DWN_GPIO");
- tegra_gpio_enable(CAM3_POWER_DWN_GPIO);
ret = gpio_request(CAM3_POWER_DWN_GPIO, "cam3_power_en");
if (ret < 0)
pr_err("%s: gpio_request failed for gpio %s\n",
__func__, "CAM3_POWER_DWN_GPIO");
- tegra_gpio_enable(CAM2_POWER_DWN_GPIO);
ret = gpio_request(CAM2_POWER_DWN_GPIO, "camera2_power_en");
if (ret < 0)
pr_err("%s: gpio_request failed for gpio %s\n",
__func__, "CAM2_POWER_DWN_GPIO");
- tegra_gpio_enable(OV5650_RESETN_GPIO);
ret = gpio_request(OV5650_RESETN_GPIO, "camera_reset");
if (ret < 0)
pr_err("%s: gpio_request failed for gpio %s\n",
@@ -124,7 +121,6 @@ static int cardhu_camera_init(void)
}
/* To select the CSIB MUX either for cam2 or cam3 */
- tegra_gpio_enable(CAMERA_CSI_MUX_SEL_GPIO);
ret = gpio_request(CAMERA_CSI_MUX_SEL_GPIO, "camera_csi_sel");
if (ret < 0)
pr_err("%s: gpio_request failed for gpio %s\n",
@@ -601,6 +597,54 @@ static struct sh532u_platform_data pm269_sh532u_right_pdata = {
.gpio = pm269_sh532u_right_gpio_pdata,
};
+static struct nvc_gpio_pdata ad5816_gpio_pdata[] = {
+ { AD5816_GPIO_RESET, TEGRA_GPIO_PBB0, false, 0, },
+};
+
+static struct ad5816_platform_data ad5816_left_pdata = {
+ .cfg = NVC_CFG_NODEV,
+ .num = 1,
+ .sync = 2,
+ .dev_name = "focuser",
+ .gpio_count = ARRAY_SIZE(ad5816_gpio_pdata),
+ .gpio = ad5816_gpio_pdata,
+};
+
+static struct ad5816_platform_data ad5816_right_pdata = {
+ .cfg = NVC_CFG_NODEV,
+ .num = 2,
+ .sync = 1,
+ .dev_name = "focuser",
+ .gpio_count = ARRAY_SIZE(ad5816_gpio_pdata),
+ .gpio = ad5816_gpio_pdata,
+};
+
+static struct nvc_gpio_pdata pm269_ad5816_left_gpio_pdata[] = {
+ { AD5816_GPIO_RESET, CAM1_RST_L_GPIO, false, 0, },
+};
+
+static struct ad5816_platform_data pm269_ad5816_left_pdata = {
+ .cfg = 0,
+ .num = 1,
+ .sync = 2,
+ .dev_name = "focuser",
+ .gpio_count = ARRAY_SIZE(pm269_ad5816_left_gpio_pdata),
+ .gpio = pm269_ad5816_left_gpio_pdata,
+};
+
+static struct nvc_gpio_pdata pm269_ad5816_right_gpio_pdata[] = {
+ { AD5816_GPIO_RESET, CAM2_RST_L_GPIO, false, 0, },
+};
+
+static struct ad5816_platform_data pm269_ad5816_right_pdata = {
+ .cfg = 0,
+ .num = 2,
+ .sync = 1,
+ .dev_name = "focuser",
+ .gpio_count = ARRAY_SIZE(pm269_ad5816_right_gpio_pdata),
+ .gpio = pm269_ad5816_right_gpio_pdata,
+};
+
static struct nvc_torch_pin_state cardhu_tps61050_pinstate = {
.mask = 0x0008, /*VGP3*/
@@ -628,6 +672,10 @@ static struct i2c_board_info cardhu_i2c6_board_info[] = {
I2C_BOARD_INFO("sh532u", 0x72),
.platform_data = &sh532u_left_pdata,
},
+ {
+ I2C_BOARD_INFO("ad5816", 0x0E),
+ .platform_data = &ad5816_left_pdata,
+ },
};
static struct i2c_board_info cardhu_i2c7_board_info[] = {
@@ -639,6 +687,10 @@ static struct i2c_board_info cardhu_i2c7_board_info[] = {
I2C_BOARD_INFO("sh532u", 0x72),
.platform_data = &sh532u_right_pdata,
},
+ {
+ I2C_BOARD_INFO("ad5816", 0x0E),
+ .platform_data = &ad5816_right_pdata,
+ },
};
static struct i2c_board_info pm269_i2c6_board_info[] = {
@@ -650,6 +702,10 @@ static struct i2c_board_info pm269_i2c6_board_info[] = {
I2C_BOARD_INFO("sh532u", 0x72),
.platform_data = &pm269_sh532u_left_pdata,
},
+ {
+ I2C_BOARD_INFO("ad5816", 0x0E),
+ .platform_data = &pm269_ad5816_left_pdata,
+ },
};
static struct i2c_board_info pm269_i2c7_board_info[] = {
@@ -661,6 +717,10 @@ static struct i2c_board_info pm269_i2c7_board_info[] = {
I2C_BOARD_INFO("sh532u", 0x72),
.platform_data = &pm269_sh532u_right_pdata,
},
+ {
+ I2C_BOARD_INFO("ad5816", 0x0E),
+ .platform_data = &pm269_ad5816_right_pdata,
+ },
};
static struct i2c_board_info cardhu_i2c8_board_info[] = {
@@ -785,8 +845,6 @@ static int cardhu_nct1008_init(void)
ret = gpio_direction_input(nct1008_port);
if (ret < 0)
gpio_free(nct1008_port);
- else
- tegra_gpio_enable(nct1008_port);
}
return ret;
@@ -916,7 +974,6 @@ static void mpuirq_init(void)
#if (MPU_GYRO_TYPE == MPU_TYPE_MPU3050)
#if MPU_ACCEL_IRQ_GPIO
/* ACCEL-IRQ assignment */
- tegra_gpio_enable(MPU_ACCEL_IRQ_GPIO);
ret = gpio_request(MPU_ACCEL_IRQ_GPIO, MPU_ACCEL_NAME);
if (ret < 0) {
pr_err("%s: gpio_request failed %d\n", __func__, ret);
@@ -933,7 +990,6 @@ static void mpuirq_init(void)
#endif
/* MPU-IRQ assignment */
- tegra_gpio_enable(MPU_GYRO_IRQ_GPIO);
ret = gpio_request(MPU_GYRO_IRQ_GPIO, MPU_GYRO_NAME);
if (ret < 0) {
pr_err("%s: gpio_request failed %d\n", __func__, ret);
diff --git a/arch/arm/mach-tegra/board-cardhu.c b/arch/arm/mach-tegra/board-cardhu.c
index 9083828..4480ab3e 100644
--- a/arch/arm/mach-tegra/board-cardhu.c
+++ b/arch/arm/mach-tegra/board-cardhu.c
@@ -86,43 +86,6 @@ static struct tegra_thermal_data thermal_data = {
#endif
};
-/* !!!TODO: Change for cardhu (Taken from Ventana) */
-static struct tegra_utmip_config utmi_phy_config[] = {
- [0] = {
- .hssync_start_delay = 0,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 15,
- .xcvr_setup_offset = 0,
- .xcvr_use_fuses = 1,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
- [1] = {
- .hssync_start_delay = 0,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 15,
- .xcvr_setup_offset = 0,
- .xcvr_use_fuses = 1,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
- [2] = {
- .hssync_start_delay = 0,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 8,
- .xcvr_setup_offset = 0,
- .xcvr_use_fuses = 1,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
-};
-
static struct resource cardhu_bcm4329_rfkill_resources[] = {
{
.name = "bcm4329_nshutdown_gpio",
@@ -170,8 +133,6 @@ static struct platform_device cardhu_bluesleep_device = {
static noinline void __init cardhu_setup_bluesleep(void)
{
platform_device_register(&cardhu_bluesleep_device);
- tegra_gpio_enable(TEGRA_GPIO_PU6);
- tegra_gpio_enable(TEGRA_GPIO_PU1);
return;
}
@@ -845,9 +806,6 @@ static int __init cardhu_touch_init(void)
touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
} else {
- tegra_gpio_enable(TEGRA_GPIO_PH4);
- tegra_gpio_enable(TEGRA_GPIO_PH6);
-
gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
gpio_direction_input(TEGRA_GPIO_PH4);
@@ -869,135 +827,287 @@ static int __init cardhu_touch_init(void)
return 0;
}
-static struct tegra_uhsic_config uhsic_phy_config = {
- .enable_gpio = EN_HSIC_GPIO,
- .reset_gpio = -1,
- .sync_start_delay = 9,
- .idle_wait_delay = 17,
- .term_range_adj = 0,
- .elastic_underrun_limit = 16,
- .elastic_overrun_limit = 16,
-};
-
-static struct tegra_ehci_platform_data tegra_ehci_uhsic_pdata = {
- .phy_type = TEGRA_USB_PHY_TYPE_HSIC,
- .phy_config = &uhsic_phy_config,
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
- .default_enable = true,
-};
-
-static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
- [0] = {
- .phy_config = &utmi_phy_config[0],
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
- .default_enable = true,
- },
- [1] = {
- .phy_config = &utmi_phy_config[1],
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
- .default_enable = true,
- },
- [2] = {
- .phy_config = &utmi_phy_config[2],
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
- .hotplug = 1,
- .default_enable = true,
- },
-};
-
-static struct tegra_otg_platform_data tegra_otg_pdata = {
- .ehci_device = &tegra_ehci1_device,
- .ehci_pdata = &tegra_ehci_pdata[0],
-};
-
-#ifdef CONFIG_USB_SUPPORT
-static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
- [0] = {
- .instance = 0,
- .vbus_gpio = -1,
- .vbus_reg_supply = "vdd_vbus_micro_usb",
- },
- [1] = {
- .instance = 1,
- .vbus_gpio = -1,
- },
- [2] = {
- .instance = 2,
- .vbus_gpio = -1,
- .vbus_reg_supply = "vdd_vbus_typea_usb",
- },
-};
-
-static int cardhu_usb_hsic_postsupend(void)
+static void cardu_usb_hsic_postsupend(void)
{
#ifdef CONFIG_TEGRA_BB_XMM_POWER
baseband_xmm_set_power_status(BBXMM_PS_L2);
#endif
- return 0;
}
-static int cardhu_usb_hsic_preresume(void)
+static void cardu_usb_hsic_preresume(void)
{
#ifdef CONFIG_TEGRA_BB_XMM_POWER
baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
#endif
- return 0;
}
-static int cardhu_usb_hsic_phy_ready(void)
+static void cardu_usb_hsic_phy_ready(void)
{
#ifdef CONFIG_TEGRA_BB_XMM_POWER
baseband_xmm_set_power_status(BBXMM_PS_L0);
#endif
- return 0;
}
-static int cardhu_usb_hsic_phy_off(void)
+static void cardu_usb_hsic_phy_off(void)
{
#ifdef CONFIG_TEGRA_BB_XMM_POWER
baseband_xmm_set_power_status(BBXMM_PS_L3);
#endif
- return 0;
}
+static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
+ .post_suspend = cardu_usb_hsic_postsupend,
+ .pre_resume = cardu_usb_hsic_preresume,
+ .port_power = cardu_usb_hsic_phy_ready,
+ .post_phy_off = cardu_usb_hsic_phy_off,
+};
+
+static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
+ .port_otg = false,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .hot_plug = false,
+ .remote_wakeup_supported = false,
+ .power_off_on_suspend = false,
+ },
+ .u_cfg.hsic = {
+ .sync_start_delay = 9,
+ .idle_wait_delay = 17,
+ .term_range_adj = 0,
+ .elastic_underrun_limit = 16,
+ .elastic_overrun_limit = 16,
+ },
+ .ops = &hsic_xmm_plat_ops,
+};
+
+
+static int hsic_enable_gpio = -1;
+static int hsic_reset_gpio = -1;
+
+void hsic_platform_open(void)
+{
+ int reset_gpio = 0, enable_gpio = 0;
+
+ if (hsic_enable_gpio != -1)
+ enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
+ if (hsic_reset_gpio != -1)
+ reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
+ /* hsic enable signal deasserted, hsic reset asserted */
+ if (!enable_gpio)
+ gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
+ if (!reset_gpio)
+ gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
+ if (!enable_gpio)
+ tegra_gpio_enable(hsic_enable_gpio);
+ if (!reset_gpio)
+ tegra_gpio_enable(hsic_reset_gpio);
+ /* keep hsic reset asserted for 1 ms */
+ udelay(1000);
+ /* enable (power on) hsic */
+ if (!enable_gpio)
+ gpio_set_value_cansleep(hsic_enable_gpio, 1);
+ udelay(1000);
+ /* deassert reset */
+ if (!reset_gpio)
+ gpio_set_value_cansleep(hsic_reset_gpio, 1);
+
+}
+
+void hsic_platform_close(void)
+{
+ if (hsic_enable_gpio != -1) {
+ gpio_set_value(hsic_enable_gpio, 0);
+ gpio_free(hsic_enable_gpio);
+ }
+ if (hsic_reset_gpio != -1) {
+ gpio_set_value(hsic_reset_gpio, 0);
+ gpio_free(hsic_reset_gpio);
+ }
+}
+
+void hsic_power_on(void)
+{
+ if (hsic_enable_gpio != -1) {
+ gpio_set_value_cansleep(hsic_enable_gpio, 1);
+ udelay(1000);
+ }
+}
+
+void hsic_power_off(void)
+{
+ if (hsic_enable_gpio != -1) {
+ gpio_set_value_cansleep(hsic_enable_gpio, 0);
+ udelay(1000);
+ }
+}
+
+static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
+ .open = hsic_platform_open,
+ .close = hsic_platform_close,
+ .pre_phy_on = hsic_power_on,
+ .post_phy_off = hsic_power_off,
+};
+
+static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
+ .port_otg = false,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .hot_plug = false,
+ .remote_wakeup_supported = false,
+ .power_off_on_suspend = false,
+ },
+ .u_cfg.hsic = {
+ .sync_start_delay = 9,
+ .idle_wait_delay = 17,
+ .term_range_adj = 0,
+ .elastic_underrun_limit = 16,
+ .elastic_overrun_limit = 16,
+ },
+ .ops = &hsic_plat_ops,
+};
+
+static struct tegra_usb_platform_data tegra_udc_pdata = {
+ .port_otg = true,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_DEVICE,
+ .u_data.dev = {
+ .vbus_pmu_irq = 0,
+ .vbus_gpio = -1,
+ .charging_supported = false,
+ .remote_wakeup_supported = false,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 8,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
+ },
+};
+
+static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
+ .port_otg = true,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .vbus_reg = "vdd_vbus_micro_usb",
+ .hot_plug = true,
+ .remote_wakeup_supported = true,
+ .power_off_on_suspend = true,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 15,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
+ },
+};
+
+static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
+ .port_otg = false,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .hot_plug = false,
+ .remote_wakeup_supported = true,
+ .power_off_on_suspend = true,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 15,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
+ },
+};
+
+static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
+ .port_otg = false,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .vbus_reg = "vdd_vbus_typea_usb",
+ .hot_plug = true,
+ .remote_wakeup_supported = true,
+ .power_off_on_suspend = true,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 8,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
+ },
+};
+
+static struct tegra_usb_otg_data tegra_otg_pdata = {
+ .ehci_device = &tegra_ehci1_device,
+ .ehci_pdata = &tegra_ehci1_utmi_pdata,
+};
+
+#if CONFIG_USB_SUPPORT
static void cardhu_usb_init(void)
{
struct board_info bi;
tegra_get_board_info(&bi);
- tegra_usb_phy_init(tegra_usb_phy_pdata,
- ARRAY_SIZE(tegra_usb_phy_pdata));
-
+ /* OTG should be the first to be registered */
tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
platform_device_register(&tegra_otg_device);
+
+ /* setup the udc platform data */
+ tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
+
if (bi.board_id == BOARD_PM267) {
- uhsic_phy_config.reset_gpio =
- PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
- tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
+ hsic_enable_gpio = EN_HSIC_GPIO;
+ hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
+ tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
platform_device_register(&tegra_ehci2_device);
} else if (bi.board_id == BOARD_E1256) {
- tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
+ hsic_enable_gpio = EN_HSIC_GPIO;
+ tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
platform_device_register(&tegra_ehci2_device);
} else if (bi.board_id == BOARD_E1186) {
- /* for baseband devices do not switch off phy during suspend */
- tegra_ehci_uhsic_pdata.power_down_on_bus_suspend = 0;
- uhsic_phy_config.postsuspend = cardhu_usb_hsic_postsupend;
- uhsic_phy_config.preresume = cardhu_usb_hsic_preresume;
- uhsic_phy_config.usb_phy_ready = cardhu_usb_hsic_phy_ready;
- uhsic_phy_config.post_phy_off = cardhu_usb_hsic_phy_off;
- tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
- /* baseband registration happens in baseband-xmm-power */
+ tegra_ehci2_device.dev.platform_data =
+ &tegra_ehci2_hsic_xmm_pdata;
+ /* ehci2 registration happens in baseband-xmm-power */
} else {
- tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
+ tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
platform_device_register(&tegra_ehci2_device);
}
- tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
+ tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
platform_device_register(&tegra_ehci3_device);
}
@@ -1005,19 +1115,6 @@ static void cardhu_usb_init(void)
static void cardhu_usb_init(void) { }
#endif
-static void cardhu_gps_init(void)
-{
- tegra_gpio_enable(TEGRA_GPIO_PU2);
- tegra_gpio_enable(TEGRA_GPIO_PU3);
-}
-
-static void cardhu_nfc_init(void)
-{
- tegra_gpio_enable(TEGRA_GPIO_PX0);
- tegra_gpio_enable(TEGRA_GPIO_PP3);
- tegra_gpio_enable(TEGRA_GPIO_PO7);
-}
-
static struct baseband_power_platform_data tegra_baseband_power_data = {
.baseband_type = BASEBAND_XMM,
.modem = {
@@ -1095,7 +1192,7 @@ static void cardhu_modem_init(void)
} else {
w_disable_gpio = TEGRA_GPIO_PDD5;
}
- tegra_gpio_enable(w_disable_gpio);
+
ret = gpio_request(w_disable_gpio, "w_disable_gpio");
if (ret < 0)
pr_err("%s: gpio_request failed for gpio %d\n",
@@ -1115,22 +1212,9 @@ static void cardhu_modem_init(void)
break;
}
gpio_direction_output(TEGRA_GPIO_PH7, 1);
- tegra_gpio_enable(TEGRA_GPIO_PH7);
}
break;
case BOARD_E1186:
- tegra_gpio_enable(
- tegra_baseband_power_data.modem.xmm.bb_rst);
- tegra_gpio_enable(
- tegra_baseband_power_data.modem.xmm.bb_on);
- tegra_gpio_enable(
- tegra_baseband_power_data.modem.xmm.ipc_bb_wake);
- tegra_gpio_enable(
- tegra_baseband_power_data.modem.xmm.ipc_ap_wake);
- tegra_gpio_enable(
- tegra_baseband_power_data.modem.xmm.ipc_hsic_active);
- tegra_gpio_enable(
- tegra_baseband_power_data.modem.xmm.ipc_hsic_sus_req);
platform_device_register(&tegra_baseband_power_device);
platform_device_register(&tegra_baseband_power2_device);
break;
@@ -1168,7 +1252,6 @@ static void __init tegra_cardhu_init(void)
cardhu_dtv_init();
cardhu_suspend_init();
cardhu_touch_init();
- cardhu_gps_init();
cardhu_modem_init();
cardhu_kbc_init();
cardhu_scroll_init();
@@ -1182,7 +1265,6 @@ static void __init tegra_cardhu_init(void)
cardhu_pins_state_init();
cardhu_emc_init();
tegra_release_bootloader_fb();
- cardhu_nfc_init();
cardhu_pci_init();
#ifdef CONFIG_TEGRA_WDT_RECOVERY
tegra_wdt_recovery_init();
diff --git a/arch/arm/mach-tegra/board-enterprise-baseband.c b/arch/arm/mach-tegra/board-enterprise-baseband.c
index 7552e28..9143103 100644
--- a/arch/arm/mach-tegra/board-enterprise-baseband.c
+++ b/arch/arm/mach-tegra/board-enterprise-baseband.c
@@ -67,35 +67,42 @@ static struct gpio modem_gpios[] = {
{ULPI_D1, GPIOF_OUT_INIT_LOW, "ULPI_D1"},
};
-static int baseband_phy_on(void);
-static int baseband_phy_off(void);
-static void baseband_phy_restore_start(void);
-static void baseband_phy_restore_end(void);
+static void baseband_phy_init(void);
+static void baseband_phy_on(void);
+static void baseband_phy_off(void);
-static struct tegra_ulpi_trimmer e1219_trimmer = { 10, 1, 1, 1 };
-
-static struct tegra_ulpi_config ehci2_null_ulpi_phy_config = {
- .trimmer = &e1219_trimmer,
- .post_phy_on = baseband_phy_on,
+static struct tegra_usb_phy_platform_ops ulpi_null_plat_ops = {
+ .init = baseband_phy_init,
.pre_phy_off = baseband_phy_off,
- .phy_restore_start = baseband_phy_restore_start,
- .phy_restore_end = baseband_phy_restore_end,
- .phy_restore_gpio = MDM2AP_ACK,
- .ulpi_dir_gpio = ULPI_DIR,
- .ulpi_d0_gpio = ULPI_D0,
- .ulpi_d1_gpio = ULPI_D1,
+ .post_phy_on = baseband_phy_on,
};
-static struct tegra_ehci_platform_data ehci2_null_ulpi_platform_data = {
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 0,
- .phy_config = &ehci2_null_ulpi_phy_config,
- .phy_type = TEGRA_USB_PHY_TYPE_NULL_ULPI,
+static struct tegra_usb_platform_data tegra_ehci2_ulpi_null_pdata = {
+ .port_otg = false,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_ULPI_NULL,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .vbus_reg = NULL,
+ .hot_plug = false,
+ .remote_wakeup_supported = false,
+ .power_off_on_suspend = true,
+ },
+ .u_cfg.ulpi = {
+ .shadow_clk_delay = 10,
+ .clock_out_delay = 1,
+ .data_trimmer = 1,
+ .stpdirnxt_trimmer = 1,
+ .dir_trimmer = 1,
+ .clk = NULL,
+ },
+ .ops = &ulpi_null_plat_ops,
};
static int __init tegra_null_ulpi_init(void)
{
- tegra_ehci2_device.dev.platform_data = &ehci2_null_ulpi_platform_data;
+ tegra_ehci2_device.dev.platform_data = &tegra_ehci2_ulpi_null_pdata;
platform_device_register(&tegra_ehci2_device);
return 0;
}
@@ -114,7 +121,7 @@ static irqreturn_t mdm_start_thread(int irq, void *data)
return IRQ_HANDLED;
}
-static int baseband_phy_on(void)
+static void baseband_phy_init(void)
{
static bool phy_init = false;
@@ -124,22 +131,15 @@ static int baseband_phy_on(void)
phy_init = true;
}
pr_info("%s\n", __func__);
- return 0;
-}
-
-static int baseband_phy_off(void)
-{
- pr_info("%s\n", __func__);
- return 0;
}
-static void baseband_phy_restore_start(void)
+static void baseband_phy_off(void)
{
/* set AP2MDM_ACK2 high */
gpio_set_value(AP2MDM_ACK2, 1);
}
-static void baseband_phy_restore_end(void)
+static void baseband_phy_on(void)
{
/* set AP2MDM_ACK2 low */
gpio_set_value(AP2MDM_ACK2, 0);
diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c
index a95ee61..d92ac57 100644
--- a/arch/arm/mach-tegra/board-enterprise.c
+++ b/arch/arm/mach-tegra/board-enterprise.c
@@ -79,43 +79,6 @@ static struct tegra_thermal_data thermal_data = {
#endif
};
-/* !!!TODO: Change for enterprise (Taken from Cardhu) */
-static struct tegra_utmip_config utmi_phy_config[] = {
- [0] = {
- .hssync_start_delay = 0,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 15,
- .xcvr_setup_offset = 0,
- .xcvr_use_fuses = 1,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
- [1] = {
- .hssync_start_delay = 0,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 15,
- .xcvr_setup_offset = 0,
- .xcvr_use_fuses = 1,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
- [2] = {
- .hssync_start_delay = 0,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 8,
- .xcvr_setup_offset = 0,
- .xcvr_use_fuses = 1,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
-};
-
static struct resource enterprise_bcm4329_rfkill_resources[] = {
{
.name = "bcm4329_nshutdown_gpio",
@@ -653,66 +616,120 @@ static int __init enterprise_touch_init(void)
return 0;
}
-static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
- [0] = {
- .instance = 0,
- .vbus_gpio = -1,
- .vbus_reg_supply = "usb_vbus",
- .vbus_irq = ENT_TPS80031_IRQ_BASE +
- TPS80031_INT_VBUS_DET,
- },
- [1] = {
- .instance = 1,
- .vbus_gpio = -1,
- },
- [2] = {
- .instance = 2,
- .vbus_gpio = -1,
- },
-};
+static void enterprise_usb_hsic_postsupend(void)
+{
+ pr_debug("%s\n", __func__);
+#ifdef CONFIG_TEGRA_BB_XMM_POWER
+ baseband_xmm_set_power_status(BBXMM_PS_L2);
+#endif
+}
-static struct tegra_uhsic_config uhsic_phy_config = {
- .enable_gpio = -1,
- .reset_gpio = -1,
- .sync_start_delay = 9,
- .idle_wait_delay = 17,
- .term_range_adj = 0,
- .elastic_underrun_limit = 16,
- .elastic_overrun_limit = 16,
-};
+static void enterprise_usb_hsic_preresume(void)
+{
+ pr_debug("%s\n", __func__);
+#ifdef CONFIG_TEGRA_BB_XMM_POWER
+ baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
+#endif
+}
-static struct tegra_ehci_platform_data tegra_ehci_uhsic_pdata = {
- .phy_type = TEGRA_USB_PHY_TYPE_HSIC,
- .phy_config = &uhsic_phy_config,
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
- .default_enable = true,
-};
+static void enterprise_usb_hsic_phy_power(void)
+{
+ pr_debug("%s\n", __func__);
+#ifdef CONFIG_TEGRA_BB_XMM_POWER
+ baseband_xmm_set_power_status(BBXMM_PS_L0);
+#endif
+}
-static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
- [0] = {
- .phy_config = &utmi_phy_config[0],
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
- .default_enable = false,
- },
- [1] = {
- .phy_config = &utmi_phy_config[1],
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
- .default_enable = false,
- },
- [2] = {
- .phy_config = &utmi_phy_config[2],
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
- .default_enable = false,
- },
-};
+static void enterprise_usb_hsic_post_phy_off(void)
+{
+ pr_debug("%s\n", __func__);
+#ifdef CONFIG_TEGRA_BB_XMM_POWER
+ baseband_xmm_set_power_status(BBXMM_PS_L3);
+#endif
+}
-static struct tegra_otg_platform_data tegra_otg_pdata = {
+static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
+ .post_suspend = enterprise_usb_hsic_postsupend,
+ .pre_resume = enterprise_usb_hsic_preresume,
+ .port_power = enterprise_usb_hsic_phy_power,
+ .post_phy_off = enterprise_usb_hsic_post_phy_off,
+};
+
+static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
+ .port_otg = false,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .hot_plug = false,
+ .remote_wakeup_supported = false,
+ .power_off_on_suspend = false,
+ },
+ .u_cfg.hsic = {
+ .sync_start_delay = 9,
+ .idle_wait_delay = 17,
+ .term_range_adj = 0,
+ .elastic_underrun_limit = 16,
+ .elastic_overrun_limit = 16,
+ },
+ .ops = &hsic_xmm_plat_ops,
+};
+
+
+
+static struct tegra_usb_platform_data tegra_udc_pdata = {
+ .port_otg = true,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_DEVICE,
+ .u_data.dev = {
+ .vbus_pmu_irq = 0,
+ .vbus_gpio = -1,
+ .charging_supported = false,
+ .remote_wakeup_supported = false,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 8,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
+ },
+};
+
+static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
+ .port_otg = true,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .vbus_reg = "usb_vbus",
+ .hot_plug = true,
+ .remote_wakeup_supported = true,
+ .power_off_on_suspend = true,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 15,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
+ },
+};
+
+static struct tegra_usb_otg_data tegra_otg_pdata = {
.ehci_device = &tegra_ehci1_device,
- .ehci_pdata = &tegra_ehci_pdata[0],
+ .ehci_pdata = &tegra_ehci1_utmi_pdata,
};
struct platform_device *tegra_usb_hsic_host_register(void)
@@ -733,8 +750,8 @@ struct platform_device *tegra_usb_hsic_host_register(void)
pdev->dev.dma_mask = tegra_ehci2_device.dev.dma_mask;
pdev->dev.coherent_dma_mask = tegra_ehci2_device.dev.coherent_dma_mask;
- val = platform_device_add_data(pdev, &tegra_ehci_uhsic_pdata,
- sizeof(struct tegra_ehci_platform_data));
+ val = platform_device_add_data(pdev, &tegra_ehci2_hsic_xmm_pdata,
+ sizeof(struct tegra_usb_platform_data));
if (val)
goto error;
@@ -755,52 +772,12 @@ void tegra_usb_hsic_host_unregister(struct platform_device *pdev)
platform_device_unregister(pdev);
}
-static int enterprise_usb_hsic_postsupend(void)
-{
- pr_debug("%s\n", __func__);
-#ifdef CONFIG_TEGRA_BB_XMM_POWER
- baseband_xmm_set_power_status(BBXMM_PS_L2);
-#endif
- return 0;
-}
-
-static int enterprise_usb_hsic_preresume(void)
-{
- pr_debug("%s\n", __func__);
-#ifdef CONFIG_TEGRA_BB_XMM_POWER
- baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
-#endif
- return 0;
-}
-
-static int enterprise_usb_hsic_phy_ready(void)
-{
- pr_debug("%s\n", __func__);
-#ifdef CONFIG_TEGRA_BB_XMM_POWER
- baseband_xmm_set_power_status(BBXMM_PS_L0);
-#endif
- return 0;
-}
-
-static int enterprise_usb_hsic_phy_off(void)
-{
- pr_debug("%s\n", __func__);
-#ifdef CONFIG_TEGRA_BB_XMM_POWER
- baseband_xmm_set_power_status(BBXMM_PS_L3);
-#endif
- return 0;
-}
-
static void enterprise_usb_init(void)
{
- struct fsl_usb2_platform_data *udc_pdata;
-
- tegra_usb_phy_init(tegra_usb_phy_pdata, ARRAY_SIZE(tegra_usb_phy_pdata));
+ tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
platform_device_register(&tegra_otg_device);
-
- udc_pdata = tegra_udc_device.dev.platform_data;
}
static struct platform_device *enterprise_audio_devices[] __initdata = {
@@ -910,12 +887,9 @@ static void enterprise_baseband_init(void)
enterprise_modem_init();
break;
case TEGRA_BB_XMM6260: /* XMM6260 HSIC */
- /* xmm baseband - do not switch off phy during suspend */
- tegra_ehci_uhsic_pdata.power_down_on_bus_suspend = 0;
- uhsic_phy_config.postsuspend = enterprise_usb_hsic_postsupend;
- uhsic_phy_config.preresume = enterprise_usb_hsic_preresume;
- uhsic_phy_config.usb_phy_ready = enterprise_usb_hsic_phy_ready;
- uhsic_phy_config.post_phy_off = enterprise_usb_hsic_phy_off;
+ /* baseband-power.ko will register ehci2 device */
+ tegra_ehci2_device.dev.platform_data =
+ &tegra_ehci2_hsic_xmm_pdata;
/* enable XMM6260 baseband gpio(s) */
tegra_gpio_enable(tegra_baseband_power_data.modem.generic
.mdm_reset);
@@ -938,9 +912,9 @@ static void enterprise_baseband_init(void)
break;
#ifdef CONFIG_TEGRA_BB_M7400
case TEGRA_BB_M7400: /* M7400 HSIC */
- tegra_ehci_uhsic_pdata.power_down_on_bus_suspend = 0;
+ tegra_ehci2_hsic_xmm_pdata.u_data.host.power_off_on_suspend = 0;
tegra_ehci2_device.dev.platform_data
- = &tegra_ehci_uhsic_pdata;
+ = &tegra_ehci2_hsic_xmm_pdata;
platform_device_register(&tegra_baseband_m7400_device);
break;
#endif
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
index f3db0ee..f73cde4 100644
--- a/arch/arm/mach-tegra/board-harmony-pcie.c
+++ b/arch/arm/mach-tegra/board-harmony-pcie.c
@@ -4,6 +4,8 @@
* Copyright (C) 2010 CompuLab, Ltd.
* Mike Rapoport <mike@compulab.co.il>
*
+ * Copyright (C) 2011-2012 NVIDIA Corporation.
+ *
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
@@ -68,7 +70,6 @@ int __init harmony_pcie_init(void)
return 0;
-err_pcie:
tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_TRISTATE);
tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_TRISTATE);
tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_TRISTATE);
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index 9bf8cde..638c851 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -32,6 +32,8 @@
#include <linux/i2c-tegra.h>
#include <linux/memblock.h>
#include <linux/delay.h>
+#include <linux/mfd/tps6586x.h>
+#include <linux/platform_data/tegra_usb.h>
#include <sound/wm8903.h>
@@ -81,20 +83,52 @@ static int __init parse_tag_nvidia(const struct tag *tag)
}
__tagtable(ATAG_NVIDIA, parse_tag_nvidia);
-static struct tegra_utmip_config utmi_phy_config = {
- .hssync_start_delay = 0,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 9,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
+
+static struct tegra_usb_platform_data tegra_udc_pdata = {
+ .port_otg = false,
+ .has_hostpc = false,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_DEVICE,
+ .u_data.dev = {
+ .vbus_pmu_irq = 0,
+ .vbus_gpio = -1,
+ .charging_supported = false,
+ .remote_wakeup_supported = false,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 8,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
+ },
};
-static struct tegra_ehci_platform_data tegra_ehci_pdata = {
- .phy_config = &utmi_phy_config,
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
+static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
+ .port_otg = false,
+ .has_hostpc = false,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = TEGRA_GPIO_PD3,
+ .vbus_reg = NULL,
+ .hot_plug = true,
+ .remote_wakeup_supported = false,
+ .power_off_on_suspend = true,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 9,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 8,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ },
};
static struct tegra_nand_chip_parms nand_chip_parms[] = {
@@ -283,39 +317,6 @@ static void __init harmony_i2c_init(void)
i2c_register_board_info(0, &wm8903_board_info, 1);
}
-/* OTG gadget device */
-/*static u64 tegra_otg_dmamask = DMA_BIT_MASK(32);
-
-
-static struct resource tegra_otg_resources[] = {
- [0] = {
- .start = TEGRA_USB_BASE,
- .end = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = INT_USB,
- .end = INT_USB,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct fsl_usb2_platform_data tegra_otg_pdata = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_UTMI,
-};
-
-static struct platform_device tegra_otg = {
- .name = "fsl-tegra-udc",
- .id = -1,
- .dev = {
- .dma_mask = &tegra_otg_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &tegra_otg_pdata,
- },
- .resource = tegra_otg_resources,
- .num_resources = ARRAY_SIZE(tegra_otg_resources),
-};*/
/* PDA power */
static struct pda_power_pdata pda_power_pdata = {
@@ -476,7 +477,8 @@ static void __init tegra_harmony_init(void)
tegra_sdhci_device2.dev.platform_data = &sdhci_pdata2;
tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
- tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata;
+ tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
+ tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
platform_add_devices(harmony_devices, ARRAY_SIZE(harmony_devices));
harmony_i2c_init();
diff --git a/arch/arm/mach-tegra/board-kai.c b/arch/arm/mach-tegra/board-kai.c
index c455fba..193d686 100644
--- a/arch/arm/mach-tegra/board-kai.c
+++ b/arch/arm/mach-tegra/board-kai.c
@@ -82,42 +82,6 @@ static struct tegra_thermal_data thermal_data = {
#endif
};
-/* !!!TODO: Change for kai (Taken from Ventana) */
-static struct tegra_utmip_config utmi_phy_config[] = {
- [0] = {
- .hssync_start_delay = 0,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 15,
- .xcvr_setup_offset = 0,
- .xcvr_use_fuses = 1,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
- [1] = {
- .hssync_start_delay = 0,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 15,
- .xcvr_setup_offset = 0,
- .xcvr_use_fuses = 1,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
- [2] = {
- .hssync_start_delay = 0,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 8,
- .xcvr_setup_offset = 0,
- .xcvr_use_fuses = 1,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
-};
/* wl128x BT, FM, GPS connectivity chip */
struct ti_st_plat_data kai_wilink_pdata = {
@@ -165,8 +129,15 @@ static struct platform_device kai_bluesleep_device = {
static noinline void __init kai_tegra_setup_tibluesleep(void)
{
+ int ret;
+
+ ret = gpio_request(TEGRA_GPIO_PU6, "host_wake");
+ if (ret)
+ pr_err("gpio_request failed for gpio: %d\n", TEGRA_GPIO_PU6);
+ else
+ gpio_direction_input(TEGRA_GPIO_PU6);
+
platform_device_register(&kai_bluesleep_device);
- tegra_gpio_enable(TEGRA_GPIO_PU6);
}
static __initdata struct tegra_clk_init_table kai_clk_init_table[] = {
@@ -695,47 +666,97 @@ static int __init kai_touch_init(void)
return 0;
}
-static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
- [0] = {
- .phy_config = &utmi_phy_config[0],
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
- .default_enable = true,
+static struct tegra_usb_platform_data tegra_udc_pdata = {
+ .port_otg = true,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_DEVICE,
+ .u_data.dev = {
+ .vbus_pmu_irq = 0,
+ .vbus_gpio = -1,
+ .charging_supported = false,
+ .remote_wakeup_supported = false,
},
- [1] = {
- .phy_config = &utmi_phy_config[1],
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
- .default_enable = false,
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 8,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
},
};
-static struct tegra_otg_platform_data tegra_otg_pdata = {
- .ehci_device = &tegra_ehci1_device,
- .ehci_pdata = &tegra_ehci_pdata[0],
+static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
+ .port_otg = true,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .vbus_reg = NULL,
+ .hot_plug = true,
+ .remote_wakeup_supported = true,
+ .power_off_on_suspend = true,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 15,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
+ },
};
-#ifdef CONFIG_USB_SUPPORT
-static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
- [0] = {
- .instance = 0,
- .vbus_gpio = -1,
+
+static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
+ .port_otg = false,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .vbus_reg = NULL,
+ .hot_plug = false,
+ .remote_wakeup_supported = true,
+ .power_off_on_suspend = true,
+
},
- [1] = {
- .instance = 1,
- .vbus_gpio = -1,
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 8,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
},
};
+static struct tegra_usb_otg_data tegra_otg_pdata = {
+ .ehci_device = &tegra_ehci1_device,
+ .ehci_pdata = &tegra_ehci1_utmi_pdata,
+};
+
+#if CONFIG_USB_SUPPORT
static void kai_usb_init(void)
{
- tegra_usb_phy_init(tegra_usb_phy_pdata,
- ARRAY_SIZE(tegra_usb_phy_pdata));
-
tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
platform_device_register(&tegra_otg_device);
- tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
+ /* Setup the udc platform data */
+ tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
+
+ tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
platform_device_register(&tegra_ehci2_device);
}
diff --git a/arch/arm/mach-tegra/board-p1852.c b/arch/arm/mach-tegra/board-p1852.c
index 43bef99..71c1275 100644
--- a/arch/arm/mach-tegra/board-p1852.c
+++ b/arch/arm/mach-tegra/board-p1852.c
@@ -57,42 +57,6 @@
#include "gpio-names.h"
#include "fuse.h"
-static struct tegra_utmip_config utmi_phy_config[] = {
- [0] = {
- .hssync_start_delay = 0,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 15,
- .xcvr_setup_offset = 0,
- .xcvr_use_fuses = 1,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
- [1] = {
- .hssync_start_delay = 0,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 15,
- .xcvr_setup_offset = 0,
- .xcvr_use_fuses = 1,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
- [2] = {
- .hssync_start_delay = 0,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 8,
- .xcvr_setup_offset = 0,
- .xcvr_use_fuses = 1,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
-};
-
static __initdata struct tegra_clk_init_table p1852_clk_init_table[] = {
/* name parent rate enabled */
{ "pll_m", NULL, 0, true},
@@ -101,9 +65,10 @@ static __initdata struct tegra_clk_init_table p1852_clk_init_table[] = {
{ "pwm", "clk_32k", 32768, false},
{ "blink", "clk_32k", 32768, true},
{ "pll_a", NULL, 552960000, false},
- { "pll_a_out0", NULL, 12288000, false},
- { "d_audio", "pll_a_out0", 12288000, false},
- { "nor", "pll_p", 102000000, true},
+ /* audio cif clock should be faster than i2s */
+ { "pll_a_out0", NULL, 24576000, false},
+ { "d_audio", "pll_a_out0", 24576000, false},
+ { "nor", "pll_p", 86500000, true},
{ "uarta", "pll_p", 480000000, true},
{ "uartd", "pll_p", 480000000, true},
{ "uarte", "pll_p", 480000000, true},
@@ -115,11 +80,11 @@ static __initdata struct tegra_clk_init_table p1852_clk_init_table[] = {
{ "sbc5", "pll_m", 100000000, true},
{ "sbc6", "pll_m", 100000000, true},
{ "cpu_g", "cclk_g", 900000000, true},
- { "i2s0", "pll_a_out0", 12288000, false},
- { "i2s1", "pll_a_out0", 12288000, false},
- { "i2s2", "pll_a_out0", 12288000, false},
- { "i2s3", "pll_a_out0", 12288000, false},
- { "i2s4", "pll_a_out0", 12288000, false},
+ { "i2s0", "pll_a_out0", 24576000, false},
+ { "i2s1", "pll_a_out0", 24576000, false},
+ { "i2s2", "pll_a_out0", 24576000, false},
+ { "i2s3", "pll_a_out0", 24576000, false},
+ { "i2s4", "pll_a_out0", 24576000, false},
{ "audio0", "i2s0_sync", 12288000, false},
{ "audio1", "i2s1_sync", 12288000, false},
{ "audio2", "i2s2_sync", 12288000, false},
@@ -241,16 +206,24 @@ static struct tegra_p1852_platform_data p1852_audio_pdata = {
.cpu_dai_name = "tegra30-i2s.0",
.codec_name = "spdif-dit.0",
.name = "tegra-i2s-1",
- .i2s_format = format_i2s,
+ .i2s_format = format_tdm,
.master = 1,
+ .num_slots = 4,
+ .slot_width = 32,
+ .tx_mask = 0x0f,
+ .rx_mask = 0x0f,
},
.codec_info[1] = {
.codec_dai_name = "dit-hifi",
- .cpu_dai_name = "tegra30-i2s.1",
+ .cpu_dai_name = "tegra30-i2s.4",
.codec_name = "spdif-dit.1",
.name = "tegra-i2s-2",
- .i2s_format = format_i2s,
- .master = 0,
+ .i2s_format = format_tdm,
+ .master = 1,
+ .num_slots = 8,
+ .slot_width = 32,
+ .tx_mask = 0xff,
+ .rx_mask = 0xff,
},
};
@@ -278,7 +251,7 @@ static void p1852_i2s_audio_init(void)
platform_device_register(&generic_codec_1);
platform_device_register(&generic_codec_2);
platform_device_register(&tegra_i2s_device0);
- platform_device_register(&tegra_i2s_device1);
+ platform_device_register(&tegra_i2s_device4);
platform_device_register(&tegra_ahub_device);
platform_device_register(&tegra_snd_p1852);
}
@@ -349,56 +322,91 @@ static struct platform_device *p1852_devices[] __initdata = {
&tegra_wdt_device
};
-static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
- [0] = {
- .instance = 0,
- .vbus_gpio = -1,
- .vbus_reg_supply = NULL,
+static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
+ .port_otg = false,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .vbus_reg = NULL,
+ .hot_plug = false,
+ .remote_wakeup_supported = true,
+ .power_off_on_suspend = true,
},
- [1] = {
- .instance = 1,
- .vbus_gpio = -1,
- },
- [2] = {
- .instance = 2,
- .vbus_gpio = -1,
- .vbus_reg_supply = NULL,
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .idle_wait_delay = 17,
+ .elastic_limit = 16,
+ .term_range_adj = 6,
+ .xcvr_setup = 15,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
},
};
-static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
- [0] = {
- .phy_config = &utmi_phy_config[0],
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
+static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
+ .port_otg = false,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .vbus_reg = NULL,
+ .hot_plug = false,
+ .remote_wakeup_supported = true,
+ .power_off_on_suspend = true,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .idle_wait_delay = 17,
+ .elastic_limit = 16,
+ .term_range_adj = 6,
+ .xcvr_setup = 15,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
},
- [1] = {
- .phy_config = &utmi_phy_config[1],
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
+};
+
+static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
+ .port_otg = false,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .vbus_reg = NULL,
+ .hot_plug = false,
+ .remote_wakeup_supported = true,
+ .power_off_on_suspend = true,
},
- [2] = {
- .phy_config = &utmi_phy_config[2],
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .idle_wait_delay = 17,
+ .elastic_limit = 16,
+ .term_range_adj = 6,
+ .xcvr_setup = 8,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
},
};
static void p1852_usb_init(void)
{
- /* Need to parse sku info to decide host/device mode */
- tegra_usb_phy_init(tegra_usb_phy_pdata,
- ARRAY_SIZE(tegra_usb_phy_pdata));
-
- tegra_ehci1_device.dev.platform_data = &tegra_ehci_pdata[0];
+ tegra_ehci1_device.dev.platform_data = &tegra_ehci1_utmi_pdata;
platform_device_register(&tegra_ehci1_device);
- tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
+ tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
platform_device_register(&tegra_ehci2_device);
- tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
+ tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
platform_device_register(&tegra_ehci3_device);
-
}
static struct tegra_nor_platform_data p1852_nor_data = {
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index 823060e..626cd1b 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -6,6 +6,7 @@
*
* Based on board-harmony.c
* Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011-2012 NVIDIA Corporation.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -95,7 +96,7 @@ static struct platform_device *trimslice_devices[] __initdata = {
&tegra_das_device,
&tegra_pcm_device,
&trimslice_audio_device,
- &trimslice_pci_platform_data,
+ &tegra_pci_device,
};
static struct i2c_board_info trimslice_i2c3_board_info[] = {
diff --git a/arch/arm/mach-tegra/board-ventana.c b/arch/arm/mach-tegra/board-ventana.c
index d371e72..779ffdb 100644
--- a/arch/arm/mach-tegra/board-ventana.c
+++ b/arch/arm/mach-tegra/board-ventana.c
@@ -63,35 +63,6 @@
#include "wakeups-t2.h"
#include "pm.h"
-static struct tegra_utmip_config utmi_phy_config[] = {
- [0] = {
- .hssync_start_delay = 9,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 15,
- .xcvr_setup_offset = 0,
- .xcvr_use_fuses = 1,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
- [1] = {
- .hssync_start_delay = 9,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 8,
- .xcvr_setup_offset = 0,
- .xcvr_use_fuses = 1,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
-};
-
-static struct tegra_ulpi_config ulpi_phy_config = {
- .reset_gpio = TEGRA_GPIO_PG2,
- .clk = "cdev2",
-};
static struct resource ventana_bcm4329_rfkill_resources[] = {
{
@@ -164,19 +135,6 @@ static __initdata struct tegra_clk_init_table ventana_clk_init_table[] = {
{ NULL, NULL, 0, 0},
};
-static struct tegra_ulpi_config ventana_ehci2_ulpi_phy_config = {
- .reset_gpio = TEGRA_GPIO_PV1,
- .clk = "cdev2",
-};
-
-static struct tegra_ehci_platform_data ventana_ehci2_ulpi_platform_data = {
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
- .phy_config = &ventana_ehci2_ulpi_phy_config,
- .phy_type = TEGRA_USB_PHY_TYPE_LINK_ULPI,
- .default_enable = true,
-};
-
static struct tegra_i2c_platform_data ventana_i2c1_platform_data = {
.adapter_nr = 0,
.bus_count = 1,
@@ -498,73 +456,146 @@ static int __init ventana_touch_init_panjit(void)
return 0;
}
-static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
- [0] = {
- .instance = 0,
- .vbus_irq = TPS6586X_INT_BASE + TPS6586X_INT_USB_DET,
- .vbus_gpio = TEGRA_GPIO_PD0,
+static int __init ventana_gps_init(void)
+{
+ struct clk *clk32 = clk_get_sys(NULL, "blink");
+ if (!IS_ERR(clk32)) {
+ clk_set_rate(clk32,clk32->parent->rate);
+ clk_enable(clk32);
+ }
+
+ tegra_gpio_enable(TEGRA_GPIO_PZ3);
+ return 0;
+}
+
+static struct tegra_usb_platform_data tegra_udc_pdata = {
+ .port_otg = true,
+ .has_hostpc = false,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_DEVICE,
+ .u_data.dev = {
+ .vbus_pmu_irq = 0,
+ .vbus_gpio = -1,
+ .charging_supported = false,
+ .remote_wakeup_supported = false,
},
- [1] = {
- .instance = 1,
- .vbus_gpio = -1,
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 8,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
},
- [2] = {
- .instance = 2,
- .vbus_gpio = TEGRA_GPIO_PD3,
+};
+
+static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
+ .port_otg = true,
+ .has_hostpc = false,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = TEGRA_GPIO_PD0,
+ .vbus_reg = NULL,
+ .hot_plug = true,
+ .remote_wakeup_supported = false,
+ .power_off_on_suspend = true,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 9,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 8,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
},
};
-static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
- [0] = {
- .phy_config = &utmi_phy_config[0],
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
- .default_enable = true,
+static void ulpi_link_platform_open(void)
+{
+ int reset_gpio = TEGRA_GPIO_PV1;
+
+ gpio_request(reset_gpio, "ulpi_phy_reset");
+ gpio_direction_output(reset_gpio, 0);
+ tegra_gpio_enable(reset_gpio);
+
+ gpio_direction_output(reset_gpio, 0);
+ msleep(5);
+ gpio_direction_output(reset_gpio, 1);
+}
+
+static struct tegra_usb_phy_platform_ops ulpi_link_plat_ops = {
+ .open = ulpi_link_platform_open,
+};
+
+static struct tegra_usb_platform_data tegra_ehci2_ulpi_link_pdata = {
+ .port_otg = false,
+ .has_hostpc = false,
+ .phy_intf = TEGRA_USB_PHY_INTF_ULPI_LINK,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .vbus_reg = NULL,
+ .hot_plug = false,
+ .remote_wakeup_supported = false,
+ .power_off_on_suspend = true,
},
- [1] = {
- .phy_config = &ulpi_phy_config,
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
- .phy_type = TEGRA_USB_PHY_TYPE_LINK_ULPI,
- .default_enable = true,
+ .u_cfg.ulpi = {
+ .shadow_clk_delay = 10,
+ .clock_out_delay = 1,
+ .data_trimmer = 4,
+ .stpdirnxt_trimmer = 4,
+ .dir_trimmer = 4,
+ .clk = "cdev2",
},
- [2] = {
- .phy_config = &utmi_phy_config[1],
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
- .hotplug = 1,
- .default_enable = true,
+ .ops = &ulpi_link_plat_ops,
+};
+
+static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
+ .port_otg = false,
+ .has_hostpc = false,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = TEGRA_GPIO_PD3,
+ .vbus_reg = NULL,
+ .hot_plug = true,
+ .remote_wakeup_supported = false,
+ .power_off_on_suspend = true,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 9,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 8,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
},
};
-static struct tegra_otg_platform_data tegra_otg_pdata = {
+static struct tegra_usb_otg_data tegra_otg_pdata = {
.ehci_device = &tegra_ehci1_device,
- .ehci_pdata = &tegra_ehci_pdata[0],
+ .ehci_pdata = &tegra_ehci1_utmi_pdata,
};
-static int __init ventana_gps_init(void)
-{
- struct clk *clk32 = clk_get_sys(NULL, "blink");
- if (!IS_ERR(clk32)) {
- clk_set_rate(clk32,clk32->parent->rate);
- clk_enable(clk32);
- }
-
- tegra_gpio_enable(TEGRA_GPIO_PZ3);
- return 0;
-}
-
static void ventana_usb_init(void)
{
- tegra_usb_phy_init(tegra_usb_phy_pdata, ARRAY_SIZE(tegra_usb_phy_pdata));
/* OTG should be the first to be registered */
tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
platform_device_register(&tegra_otg_device);
+ tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
platform_device_register(&tegra_udc_device);
+
+ tegra_ehci2_device.dev.platform_data = &tegra_ehci2_ulpi_link_pdata;
platform_device_register(&tegra_ehci2_device);
- tegra_ehci3_device.dev.platform_data=&tegra_ehci_pdata[2];
+ tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
platform_device_register(&tegra_ehci3_device);
}
@@ -576,8 +607,6 @@ static void __init tegra_ventana_init(void)
ventana_pinmux_init();
ventana_i2c_init();
ventana_uart_init();
- tegra_ehci2_device.dev.platform_data
- = &ventana_ehci2_ulpi_platform_data;
platform_add_devices(ventana_devices, ARRAY_SIZE(ventana_devices));
tegra_ram_console_debug_init();
ventana_sdhci_init();
diff --git a/arch/arm/mach-tegra/board-whistler-baseband.c b/arch/arm/mach-tegra/board-whistler-baseband.c
index 143d14a..eb50fb2 100644
--- a/arch/arm/mach-tegra/board-whistler-baseband.c
+++ b/arch/arm/mach-tegra/board-whistler-baseband.c
@@ -24,10 +24,9 @@
#include "board.h"
#include "board-whistler-baseband.h"
-static int baseband_phy_on(void);
-static int baseband_phy_off(void);
-static void baseband_phy_restore_start(void);
-static void baseband_phy_restore_end(void);
+static void baseband_phy_init(void);
+static void baseband_phy_on(void);
+static void baseband_phy_off(void);
static struct wake_lock mdm_wake_lock;
@@ -57,30 +56,38 @@ static __initdata struct tegra_pingroup_config whistler_null_ulpi_pinmux[] = {
TEGRA_TRI_NORMAL},
};
-static struct tegra_ulpi_trimmer e1219_trimmer = { 10, 1, 1, 1 };
-
-static struct tegra_ulpi_config ehci2_null_ulpi_phy_config = {
- .trimmer = &e1219_trimmer,
- .post_phy_on = baseband_phy_on,
+static struct tegra_usb_phy_platform_ops ulpi_null_plat_ops = {
+ .init = baseband_phy_init,
.pre_phy_off = baseband_phy_off,
- .phy_restore_start = baseband_phy_restore_start,
- .phy_restore_end = baseband_phy_restore_end,
- .phy_restore_gpio = MDM2AP_ACK,
- .ulpi_dir_gpio = ULPI_DIR,
- .ulpi_d0_gpio = ULPI_D0,
- .ulpi_d1_gpio = ULPI_D1,
+ .post_phy_on = baseband_phy_on,
};
-static struct tegra_ehci_platform_data ehci2_null_ulpi_platform_data = {
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 0,
- .phy_config = &ehci2_null_ulpi_phy_config,
- .phy_type = TEGRA_USB_PHY_TYPE_NULL_ULPI,
+static struct tegra_usb_platform_data tegra_ehci2_ulpi_null_pdata = {
+ .port_otg = false,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_ULPI_NULL,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .vbus_reg = NULL,
+ .hot_plug = false,
+ .remote_wakeup_supported = false,
+ .power_off_on_suspend = false,
+ },
+ .u_cfg.ulpi = {
+ .shadow_clk_delay = 10,
+ .clock_out_delay = 1,
+ .data_trimmer = 1,
+ .stpdirnxt_trimmer = 1,
+ .dir_trimmer = 1,
+ .clk = NULL,
+ },
+ .ops = &ulpi_null_plat_ops,
};
static int __init tegra_null_ulpi_init(void)
{
- tegra_ehci2_device.dev.platform_data = &ehci2_null_ulpi_platform_data;
+ tegra_ehci2_device.dev.platform_data = &tegra_ehci2_ulpi_null_pdata;
platform_device_register(&tegra_ehci2_device);
return 0;
}
@@ -98,7 +105,7 @@ static irqreturn_t mdm_start_thread(int irq, void *data)
return IRQ_HANDLED;
}
-static int baseband_phy_on(void)
+static void baseband_phy_init(void)
{
static bool phy_init;
@@ -108,22 +115,15 @@ static int baseband_phy_on(void)
phy_init = true;
}
pr_info("%s\n", __func__);
- return 0;
-}
-
-static int baseband_phy_off(void)
-{
- pr_info("%s\n", __func__);
- return 0;
}
-static void baseband_phy_restore_start(void)
+static void baseband_phy_off(void)
{
/* set AP2MDM_ACK2 high */
gpio_set_value(AP2MDM_ACK2, 1);
}
-static void baseband_phy_restore_end(void)
+static void baseband_phy_on (void)
{
/* set AP2MDM_ACK2 low */
gpio_set_value(AP2MDM_ACK2, 0);
diff --git a/arch/arm/mach-tegra/board-whistler-sdhci.c b/arch/arm/mach-tegra/board-whistler-sdhci.c
index d98b1d5..2d2a9c8 100644
--- a/arch/arm/mach-tegra/board-whistler-sdhci.c
+++ b/arch/arm/mach-tegra/board-whistler-sdhci.c
@@ -2,7 +2,7 @@
* arch/arm/mach-tegra/board-whistler-sdhci.c
*
* Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2011 NVIDIA Corporation.
+ * Copyright (C) 2011-2012 NVIDIA Corporation.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -256,8 +256,6 @@ static int __init whistler_wifi_init(void)
}
int __init whistler_sdhci_init(void)
{
- int ret;
-
tegra_gpio_enable(WHISTLER_EXT_SDCARD_DETECT);
platform_device_register(&tegra_sdhci_device3);
diff --git a/arch/arm/mach-tegra/board-whistler.c b/arch/arm/mach-tegra/board-whistler.c
index ede0d0b..874ef18 100644
--- a/arch/arm/mach-tegra/board-whistler.c
+++ b/arch/arm/mach-tegra/board-whistler.c
@@ -1,7 +1,7 @@
/*
* arch/arm/mach-tegra/board-whistler.c
*
- * Copyright (c) 2010 - 2011, NVIDIA Corporation.
+ * Copyright (c) 2010-2012 NVIDIA Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -222,32 +222,6 @@ static void __init whistler_setup_bluesleep(void)
return;
}
-static struct tegra_utmip_config utmi_phy_config[] = {
- [0] = {
- .hssync_start_delay = 9,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 15,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
- [1] = {
- .hssync_start_delay = 9,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 8,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
-};
-
-static struct tegra_ulpi_config ulpi_phy_config = {
- .reset_gpio = TEGRA_GPIO_PG2,
- .clk = "cdev2",
-};
-
static __initdata struct tegra_clk_init_table whistler_clk_init_table[] = {
/* name parent rate enabled */
{ "pwm", "clk_32k", 32768, false},
@@ -455,61 +429,71 @@ static int __init whistler_scroll_init(void)
return 0;
}
-static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
- [0] = {
- .instance = 0,
- .vbus_irq = MAX8907C_INT_BASE + MAX8907C_IRQ_VCHG_DC_R,
- .vbus_gpio = USB1_VBUS_GPIO,
- },
- [1] = {
- .instance = 1,
- .vbus_gpio = -1,
+static int __init whistler_gps_init(void)
+{
+ tegra_gpio_enable(TEGRA_GPIO_PU4);
+ return 0;
+}
+
+static struct tegra_usb_platform_data tegra_udc_pdata = {
+ .port_otg = true,
+ .has_hostpc = false,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_DEVICE,
+ .u_data.dev = {
+ .vbus_pmu_irq = 0,
+ .vbus_gpio = -1,
+ .charging_supported = false,
+ .remote_wakeup_supported = false,
},
- [2] = {
- .instance = 2,
- .vbus_gpio = -1,
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 8,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
},
};
-static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
- [0] = {
- .phy_config = &utmi_phy_config[0],
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
- .default_enable = false,
- },
- [1] = {
- .phy_config = &ulpi_phy_config,
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
- .default_enable = false,
- },
- [2] = {
- .phy_config = &utmi_phy_config[1],
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
- .default_enable = false,
+static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
+ .port_otg = true,
+ .has_hostpc = false,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = TEGRA_GPIO_PN6,
+ .vbus_reg = NULL,
+ .hot_plug = true,
+ .remote_wakeup_supported = false,
+ .power_off_on_suspend = true,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 9,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 8,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
},
};
-static struct tegra_otg_platform_data tegra_otg_pdata = {
+static struct tegra_usb_otg_data tegra_otg_pdata = {
.ehci_device = &tegra_ehci1_device,
- .ehci_pdata = &tegra_ehci_pdata[0],
+ .ehci_pdata = &tegra_ehci1_utmi_pdata,
};
-static int __init whistler_gps_init(void)
-{
- tegra_gpio_enable(TEGRA_GPIO_PU4);
- return 0;
-}
-
+#define SERIAL_NUMBER_LENGTH 20
static void whistler_usb_init(void)
{
- tegra_usb_phy_init(tegra_usb_phy_pdata, ARRAY_SIZE(tegra_usb_phy_pdata));
-
tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
platform_device_register(&tegra_otg_device);
+ tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
}
static void __init tegra_whistler_init(void)
diff --git a/arch/arm/mach-tegra/common-t2.c b/arch/arm/mach-tegra/common-t2.c
index 6f9b177..f90dfce 100644
--- a/arch/arm/mach-tegra/common-t2.c
+++ b/arch/arm/mach-tegra/common-t2.c
@@ -3,7 +3,7 @@
*
* Tegra 2 SoC-specific initialization (memory controller, etc.)
*
- * Copyright (c) 2009-2011, NVIDIA Corporation.
+ * Copyright (c) 2009-2012 NVIDIA Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -177,16 +177,18 @@ out:
return IRQ_HANDLED;
}
-void __init tegra_mc_init(void)
+static int __init tegra_mc_init(void)
{
if (request_irq(INT_MC_GENERAL, tegra_mc_error_isr, 0,
"mc_status", NULL)) {
pr_err("%s: unable to register MC error interrupt\n", __func__);
+ return -EINVAL;
} else {
void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE);
u32 reg = MC_INT_SECURITY_VIOLATION | MC_INT_INVALID_GART_PAGE |
MC_INT_DECERR_EMEM_OTHERS;
writel(reg, mc + MC_INT_MASK);
}
+ return 0;
}
arch_initcall(tegra_mc_init);
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 78bd77d..2986f1c 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -974,12 +974,14 @@ void cpufreq_store_default_gov(void)
int cpufreq_change_gov(char *target_gov)
{
- unsigned int cpu = 0;
+ unsigned int cpu = 0, ret = -EINVAL;
#ifndef CONFIG_TEGRA_AUTO_HOTPLUG
for_each_online_cpu(cpu)
#endif
- return cpufreq_set_gov(target_gov, cpu);
+ ret = cpufreq_set_gov(target_gov, cpu);
+
+ return ret;
}
int cpufreq_restore_default_gov(void)
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 2a4f94c..377772f 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -584,28 +584,6 @@ static struct resource tegra_usb3_resources[] = {
},
};
-static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
- /* All existing boards use GPIO PV0 for phy reset */
- .reset_gpio = TEGRA_GPIO_PV0,
- .clk = "cdev2",
-};
-
-static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
- .operating_mode = TEGRA_USB_OTG,
- .power_down_on_bus_suspend = 1,
-};
-
-static struct tegra_ehci_platform_data tegra_ehci2_pdata = {
- .phy_config = &tegra_ehci2_ulpi_phy_config,
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
-};
-
-static struct tegra_ehci_platform_data tegra_ehci3_pdata = {
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 1,
-};
-
static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
struct platform_device tegra_ehci1_device = {
@@ -614,7 +592,6 @@ struct platform_device tegra_ehci1_device = {
.dev = {
.dma_mask = &tegra_ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &tegra_ehci1_pdata,
},
.resource = tegra_usb1_resources,
.num_resources = ARRAY_SIZE(tegra_usb1_resources),
@@ -626,7 +603,6 @@ struct platform_device tegra_ehci2_device = {
.dev = {
.dma_mask = &tegra_ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &tegra_ehci2_pdata,
},
.resource = tegra_usb2_resources,
.num_resources = ARRAY_SIZE(tegra_usb2_resources),
@@ -638,7 +614,6 @@ struct platform_device tegra_ehci3_device = {
.dev = {
.dma_mask = &tegra_ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &tegra_ehci3_pdata,
},
.resource = tegra_usb3_resources,
.num_resources = ARRAY_SIZE(tegra_usb3_resources),
@@ -1226,18 +1201,12 @@ static struct resource tegra_udc_resources[] = {
static u64 tegra_udc_dmamask = DMA_BIT_MASK(32);
-static struct fsl_usb2_platform_data tegra_udc_pdata = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_UTMI,
-};
-
struct platform_device tegra_udc_device = {
.name = "tegra-udc",
.id = 0,
.dev = {
.dma_mask = &tegra_udc_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &tegra_udc_pdata,
},
.resource = tegra_udc_resources,
.num_resources = ARRAY_SIZE(tegra_udc_resources),
diff --git a/arch/arm/mach-tegra/include/mach/dc.h b/arch/arm/mach-tegra/include/mach/dc.h
index ab3d4e9..71f1be7 100644
--- a/arch/arm/mach-tegra/include/mach/dc.h
+++ b/arch/arm/mach-tegra/include/mach/dc.h
@@ -503,6 +503,7 @@ struct tegra_dc_platform_data {
#define TEGRA_DC_FLAG_ENABLED (1 << 0)
+int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win);
struct tegra_dc *tegra_dc_get_dc(unsigned idx);
struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win);
bool tegra_dc_get_connected(struct tegra_dc *);
diff --git a/arch/arm/mach-tegra/include/mach/latency_allowance.h b/arch/arm/mach-tegra/include/mach/latency_allowance.h
index f0d27f0..8644075 100644
--- a/arch/arm/mach-tegra/include/mach/latency_allowance.h
+++ b/arch/arm/mach-tegra/include/mach/latency_allowance.h
@@ -1,7 +1,7 @@
/*
* arch/arm/mach-tegra/include/mach/latency_allowance.h
*
- * Copyright (C) 2011, NVIDIA Corporation.
+ * Copyright (C) 2011-2012 NVIDIA Corporation.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -104,7 +104,7 @@ static inline int tegra_enable_latency_scaling(enum tegra_la_id id,
static inline void tegra_disable_latency_scaling(enum tegra_la_id id)
{
- return 0;
+ return;
}
#else
int tegra_set_latency_allowance(enum tegra_la_id id,
diff --git a/arch/arm/mach-tegra/include/mach/usb_phy.h b/arch/arm/mach-tegra/include/mach/usb_phy.h
index 3ad1128..c721642 100644
--- a/arch/arm/mach-tegra/include/mach/usb_phy.h
+++ b/arch/arm/mach-tegra/include/mach/usb_phy.h
@@ -18,150 +18,120 @@
#ifndef __MACH_USB_PHY_H
#define __MACH_USB_PHY_H
-#include <linux/clk.h>
-#include <linux/regulator/consumer.h>
-#include <linux/usb/otg.h>
-#include <linux/platform_data/tegra_usb.h>
-
-struct tegra_utmip_config {
- u8 hssync_start_delay;
- u8 elastic_limit;
- u8 idle_wait_delay;
- u8 term_range_adj;
- u8 xcvr_setup;
- signed char xcvr_setup_offset;
- u8 xcvr_use_fuses;
- u8 xcvr_lsfslew;
- u8 xcvr_lsrslew;
-};
-
-struct tegra_ulpi_trimmer {
- u8 shadow_clk_delay; /* 0 ~ 31 */
- u8 clock_out_delay; /* 0 ~ 31 */
- u8 data_trimmer; /* 0 ~ 7 */
- u8 stpdirnxt_trimmer; /* 0 ~ 7 */
-};
-
-struct tegra_ulpi_config {
- int enable_gpio;
- int reset_gpio;
- const char *clk;
- const struct tegra_ulpi_trimmer *trimmer;
- int (*pre_phy_on)(void);
- int (*post_phy_on)(void);
- int (*pre_phy_off)(void);
- int (*post_phy_off)(void);
- void (*phy_restore_start)(void);
- void (*phy_restore_end)(void);
- int phy_restore_gpio; /* null phy restore ack from device */
- int ulpi_dir_gpio; /* ulpi dir */
- int ulpi_d0_gpio; /* usb linestate[0] */
- int ulpi_d1_gpio; /* usb linestate[1] */
-};
-
-struct tegra_uhsic_config {
- int enable_gpio;
- int reset_gpio;
- u8 sync_start_delay;
- u8 idle_wait_delay;
- u8 term_range_adj;
- u8 elastic_underrun_limit;
- u8 elastic_overrun_limit;
- int (*postsuspend)(void);
- int (*preresume)(void);
- int (*usb_phy_ready)(void);
- int (*post_phy_off)(void);
-};
-
-enum tegra_usb_phy_port_speed {
- TEGRA_USB_PHY_PORT_SPEED_FULL = 0,
- TEGRA_USB_PHY_PORT_SPEED_LOW,
- TEGRA_USB_PHY_PORT_SPEED_HIGH,
-};
-
-enum tegra_usb_phy_mode {
- TEGRA_USB_PHY_MODE_DEVICE,
- TEGRA_USB_PHY_MODE_HOST,
-};
-
-struct usb_phy_plat_data {
- int instance;
- int vbus_irq;
- int vbus_gpio;
- char * vbus_reg_supply;
-};
-
-struct tegra_xtal_freq;
-
-struct tegra_usb_phy {
- int instance;
- const struct tegra_xtal_freq *freq;
- void __iomem *regs;
- void __iomem *pad_regs;
- struct clk *clk;
- struct clk *pll_u;
- struct clk *pad_clk;
- enum tegra_usb_phy_mode mode;
- void *config;
- struct regulator *reg_vdd;
- struct regulator *reg_vbus;
- enum tegra_usb_phy_type usb_phy_type;
- bool regulator_on;
- struct otg_transceiver *ulpi;
- int initialized;
- bool power_on;
- bool remote_wakeup;
- int hotplug;
- unsigned int xcvr_setup_value;
-};
-
-typedef int (*tegra_phy_fp)(struct tegra_usb_phy *phy, bool is_dpd);
-typedef void (*tegra_phy_restore_start_fp)(struct tegra_usb_phy *phy,
- enum tegra_usb_phy_port_speed);
-typedef void (*tegra_phy_restore_end_fp)(struct tegra_usb_phy *phy);
-
-struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
- void *config, enum tegra_usb_phy_mode phy_mode,
- enum tegra_usb_phy_type usb_phy_type);
-
-int tegra_usb_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd);
-
-void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy);
-
-void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy);
-
-void tegra_usb_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd);
-
-void tegra_usb_phy_postsuspend(struct tegra_usb_phy *phy, bool is_dpd);
-
-void tegra_usb_phy_preresume(struct tegra_usb_phy *phy, bool is_dpd);
-
-void tegra_usb_phy_postresume(struct tegra_usb_phy *phy, bool is_dpd);
-
-void tegra_ehci_pre_reset(struct tegra_usb_phy *phy, bool is_dpd);
-
-void tegra_ehci_post_reset(struct tegra_usb_phy *phy, bool is_dpd);
-
-void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
- enum tegra_usb_phy_port_speed port_speed);
-
-void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy);
+/**
+ * Tegra USB phy opaque handle
+ */
+struct tegra_usb_phy;
+
+/**
+ * Opens the usb phy associated to the USB platform device
+ * tegra usb phy open must be called before accessing any phy APIs
+ */
+struct tegra_usb_phy *tegra_usb_phy_open(struct platform_device *pdev);
+/**
+ * Closes the phy controller and its resources
+ */
void tegra_usb_phy_close(struct tegra_usb_phy *phy);
-int tegra_usb_phy_bus_connect(struct tegra_usb_phy *phy);
+/**
+ * Handles interrupts specific to the phy interface
+ * Note: udc or ehci driver will handle the controller interrupts
+ */
+int tegra_usb_phy_irq(struct tegra_usb_phy *phy);
+
+/**
+ * Initializes the phy specific functions after phy is power on
+ */
+int tegra_usb_phy_init(struct tegra_usb_phy *phy);
+
+/**
+ * Handles phy interface specific functionality after driver reset
+ */
+int tegra_usb_phy_reset(struct tegra_usb_phy *phy);
+
+/**
+ * Handles phy interface specific functionality before driver suspend
+ * Also, handles platform specific pre suspend functions
+ */
+int tegra_usb_phy_pre_suspend(struct tegra_usb_phy *phy);
+
+/**
+ * Handles phy interface specific suspend functionality
+ */
+int tegra_usb_phy_suspend(struct tegra_usb_phy *phy);
+
+/**
+ * Handles phy interface specific functionality after driver suspend
+ */
+int tegra_usb_phy_post_suspend(struct tegra_usb_phy *phy);
+
+/**
+ * Handles phy interface specific functionality before driver resume
+ * Also, handles platform specific pre resume functions
+ */
+int tegra_usb_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup);
+
+/**
+ * Handles phy interface specific resume functionality
+ */
+int tegra_usb_phy_resume(struct tegra_usb_phy *phy);
+/**
+ * Handles phy interface specific functionality after driver resume
+ */
+int tegra_usb_phy_post_resume(struct tegra_usb_phy *phy);
+
+/**
+ * Handles phy interface specific functionality during port power on
+ */
+int tegra_usb_phy_port_power(struct tegra_usb_phy *phy);
+
+/**
+ * Handles phy interface specific functionality during bus reset
+ */
int tegra_usb_phy_bus_reset(struct tegra_usb_phy *phy);
-int tegra_usb_phy_bus_idle(struct tegra_usb_phy *phy);
+/**
+ * Handles phy interface specific functionality for turning off the phy to
+ * put the phy in low power mode
+ */
+int tegra_usb_phy_power_off(struct tegra_usb_phy *phy);
-bool tegra_usb_phy_is_device_connected(struct tegra_usb_phy *phy);
+/**
+ * Handles phy interface specific functionality for turning on the phy to
+ * bring phy out of low power mode
+ */
+int tegra_usb_phy_power_on(struct tegra_usb_phy *phy);
-bool tegra_usb_phy_charger_detect(struct tegra_usb_phy *phy);
+/**
+ * Indicates whether phy registers are accessible or not
+ * if phy is powered off then returns false else true
+ */
+bool tegra_usb_phy_hw_accessible(struct tegra_usb_phy *phy);
+
+/**
+ * Indicates whether compliance charger is connected or not
+ * if compliance charger is detected then returns true else false
+ */
+bool tegra_usb_phy_charger_detected(struct tegra_usb_phy *phy);
+
+/**
+ * Indicates whether phy resumed due to the remote wake event or not
+ * returns true if remote wake is detected.
+ */
+bool tegra_usb_phy_remote_wakeup(struct tegra_usb_phy *phy);
+
+/**
+ * Indicates controller has HOST PC register set or not
+ */
+bool tegra_usb_phy_has_hostpc(struct tegra_usb_phy *phy);
-int __init tegra_usb_phy_init(struct usb_phy_plat_data *pdata, int size);
+/**
+ * Indicates controller port supports OTG or not
+ */
+bool tegra_usb_phy_otg_supported(struct tegra_usb_phy *phy);
-bool tegra_usb_phy_is_remotewake_detected(struct tegra_usb_phy *phy);
void tegra_usb_phy_memory_prefetch_on(struct tegra_usb_phy *phy);
diff --git a/arch/arm/mach-tegra/iovmm-gart.c b/arch/arm/mach-tegra/iovmm-gart.c
index ad1ce3a..130901c 100644
--- a/arch/arm/mach-tegra/iovmm-gart.c
+++ b/arch/arm/mach-tegra/iovmm-gart.c
@@ -4,7 +4,7 @@
* Tegra I/O VMM implementation for GART devices in Tegra and Tegra 2 series
* systems-on-a-chip.
*
- * Copyright (c) 2010-2012, NVIDIA Corporation.
+ * Copyright (c) 2010-2012 NVIDIA Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -73,7 +73,7 @@ static int gart_map(struct tegra_iovmm_domain *, struct tegra_iovmm_area *);
static void gart_unmap(struct tegra_iovmm_domain *,
struct tegra_iovmm_area *, bool);
static void gart_map_pfn(struct tegra_iovmm_domain *,
- struct tegra_iovmm_area *, tegra_iovmm_addr_t, unsigned long);
+ struct tegra_iovmm_area *, unsigned long, unsigned long);
static struct tegra_iovmm_domain *gart_alloc_domain(
struct tegra_iovmm_device *, struct tegra_iovmm_client *);
@@ -330,7 +330,7 @@ static void gart_unmap(struct tegra_iovmm_domain *domain,
}
static void gart_map_pfn(struct tegra_iovmm_domain *domain,
- struct tegra_iovmm_area *iovma, tegra_iovmm_addr_t offs,
+ struct tegra_iovmm_area *iovma, unsigned long offs,
unsigned long pfn)
{
struct gart_device *gart =
diff --git a/arch/arm/mach-tegra/p852/board-p852.c b/arch/arm/mach-tegra/p852/board-p852.c
index 21b867e..ffdf5d3 100644
--- a/arch/arm/mach-tegra/p852/board-p852.c
+++ b/arch/arm/mach-tegra/p852/board-p852.c
@@ -288,49 +288,6 @@ static struct platform_device debug_uart = {
},
};
-static struct tegra_utmip_config utmi_phy_config[] = {
- [0] = {
- .hssync_start_delay = 0,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 15,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
- [1] = {
- .hssync_start_delay = 0,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 8,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
-};
-
-static struct tegra_ulpi_config ulpi_usb2_config = {
- .reset_gpio = TEGRA_GPIO_PI5,
-};
-
-static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
- [0] = {
- .phy_config = &utmi_phy_config[0],
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 0,
- },
- [1] = {
- .phy_config = &ulpi_usb2_config,
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 0,
- .phy_type = TEGRA_USB_PHY_TYPE_LINK_ULPI,
- },
- [2] = {
- .phy_config = &utmi_phy_config[1],
- .operating_mode = TEGRA_USB_HOST,
- .power_down_on_bus_suspend = 0,
- },
-};
static void p852_usb_gpio_config(void)
{
@@ -529,6 +486,97 @@ static void __init p852_register_spidev(void)
#define p852_register_spidev() do {} while (0)
#endif
+/*
+ FixMe: Copied below GPIO value from Ventana board.
+ Plz correct it accordingly for embedded board usage
+*/
+#define TEGRA_GPIO_PV1 169
+
+static void ulpi_link_platform_open(void)
+{
+ int reset_gpio = TEGRA_GPIO_PV1;
+
+ gpio_request(reset_gpio, "ulpi_phy_reset");
+ gpio_direction_output(reset_gpio, 0);
+ tegra_gpio_enable(reset_gpio);
+
+ gpio_direction_output(reset_gpio, 0);
+ msleep(5);
+ gpio_direction_output(reset_gpio, 1);
+}
+
+static struct tegra_usb_phy_platform_ops ulpi_link_plat_ops = {
+ .open = ulpi_link_platform_open,
+};
+
+static struct tegra_usb_platform_data tegra_ehci_ulpi_link_pdata = {
+ .port_otg = false,
+ .has_hostpc = false,
+ .phy_intf = TEGRA_USB_PHY_INTF_ULPI_LINK,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .vbus_reg = NULL,
+ .hot_plug = false,
+ .remote_wakeup_supported = false,
+ .power_off_on_suspend = false,
+ },
+ .u_cfg.ulpi = {
+ .shadow_clk_delay = 10,
+ .clock_out_delay = 1,
+ .data_trimmer = 4,
+ .stpdirnxt_trimmer = 4,
+ .dir_trimmer = 4,
+ .clk = "cdev2",
+ },
+ .ops = &ulpi_link_plat_ops,
+};
+
+static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
+ .port_otg = false,
+ .has_hostpc = false,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .vbus_reg = NULL,
+ .hot_plug = true,
+ .remote_wakeup_supported = true,
+ .power_off_on_suspend = false,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .idle_wait_delay = 17,
+ .elastic_limit = 16,
+ .term_range_adj = 6,
+ .xcvr_setup = 15,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ },
+};
+
+static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
+ .port_otg = false,
+ .has_hostpc = false,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .vbus_reg = NULL,
+ .hot_plug = true,
+ .remote_wakeup_supported = true,
+ .power_off_on_suspend = false,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .idle_wait_delay = 17,
+ .elastic_limit = 16,
+ .term_range_adj = 6,
+ .xcvr_setup = 8,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ },
+};
static void __init p852_usb_init(void)
{
@@ -541,16 +589,16 @@ static void __init p852_usb_init(void)
else
*/
{
- tegra_ehci1_device.dev.platform_data = &tegra_ehci_pdata[0];
+ tegra_ehci1_device.dev.platform_data = &tegra_ehci1_utmi_pdata;
platform_device_register(&tegra_ehci1_device);
}
if (!(p852_sku_peripherals & P852_SKU_ULPI_DISABLE)) {
- tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
+ tegra_ehci2_device.dev.platform_data = &tegra_ehci_ulpi_link_pdata;
platform_device_register(&tegra_ehci2_device);
}
- tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
+ tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
platform_device_register(&tegra_ehci3_device);
}
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 1c4ee1b..80a9a12 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -294,6 +294,9 @@
#define PCIE_CONF_REG(r) \
(((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF))
+#define PCIE_CTRL_REGS 7
+#define COMBINE_PCIE_PCIX_SPACE 2
+
struct tegra_pcie_port {
int index;
u8 root_bus_nr;
@@ -349,6 +352,12 @@ static struct resource pcie_prefetch_mem_space;
static bool is_pcie_noirq_op = false;
/* used to backup config space registers of all pcie devices */
static u32 *pbackup_config_space = NULL;
+static u16 *pbackup_pcie_cap_space = NULL;
+static u16 *pbackup_pcix_cap_space = NULL;
+/* use same save state and position variables to store pcie */
+/* and pcix capability offsets at even & odd index respectively */
+static struct pci_cap_saved_state **pcie_save_state;
+static int *pos;
void __iomem *tegra_pcie_io_base;
EXPORT_SYMBOL(tegra_pcie_io_base);
@@ -986,7 +995,7 @@ static void tegra_pcie_clocks_put(void)
clk_put(tegra_pcie.pcie_xclk);
}
-static int __init tegra_pcie_get_resources(void)
+static int tegra_pcie_get_resources(void)
{
struct resource *res_mmio = 0;
int err;
@@ -1112,11 +1121,22 @@ retry:
return false;
}
-static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg)
+static void tegra_enable_clock_clamp(int index)
{
- struct tegra_pcie_port *pp;
unsigned int data;
+ /* Power mangagement settings */
+ /* Enable clock clamping by default */
+ data = rp_readl(NV_PCIE2_RP_PRIV_MISC, index);
+ data |= (PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE) |
+ (PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE);
+ rp_writel(data, NV_PCIE2_RP_PRIV_MISC, index);
+}
+
+static void tegra_pcie_add_port(int index, u32 offset, u32 reset_reg)
+{
+ struct tegra_pcie_port *pp;
+
pp = tegra_pcie.port + tegra_pcie.num_ports;
pp->index = -1;
@@ -1128,13 +1148,7 @@ static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg)
printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index);
return;
}
- /* Power mangagement settings */
- /* Enable clock clamping by default */
- data = rp_readl(NV_PCIE2_RP_PRIV_MISC, index);
- data |= (PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE) |
- (PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE);
- rp_writel(data, NV_PCIE2_RP_PRIV_MISC, index);
-
+ tegra_enable_clock_clamp(index);
tegra_pcie.num_ports++;
pp->index = index;
pp->root_bus_nr = -1;
@@ -1178,9 +1192,47 @@ static int tegra_pcie_init(void)
return err;
}
+static int tegra_pcie_allocate_config_states(int ndev, int size)
+{
+ /* backup config space registers of all devices since it gets reset in
+ save state call from suspend noirq due to disabling of read in it */
+ pbackup_config_space = kzalloc(ndev*size*sizeof(u32), GFP_KERNEL);
+ if (!pbackup_config_space)
+ return -ENODEV;
+ pbackup_pcie_cap_space = kzalloc(ndev*PCIE_CTRL_REGS*sizeof(u16), GFP_KERNEL);
+ if (!pbackup_pcie_cap_space)
+ return -ENODEV;
+ pbackup_pcix_cap_space = kzalloc(ndev*sizeof(u16), GFP_KERNEL);
+ if (!pbackup_pcix_cap_space)
+ return -ENODEV;
+ pcie_save_state = kzalloc(COMBINE_PCIE_PCIX_SPACE*ndev*
+ sizeof(struct pci_cap_saved_state*), GFP_KERNEL);
+ if (!pbackup_pcix_cap_space)
+ return -ENODEV;
+ pos = kzalloc(COMBINE_PCIE_PCIX_SPACE*ndev*sizeof(int), GFP_KERNEL);
+ if (!pos)
+ return -ENODEV;
+
+ return 0;
+}
+
+static void tegra_pcie_deallocate_config_states(void)
+{
+ if (pbackup_config_space)
+ kzfree(pbackup_config_space);
+ if (pbackup_pcie_cap_space)
+ kzfree(pbackup_pcie_cap_space);
+ if (pbackup_pcix_cap_space)
+ kzfree(pbackup_pcix_cap_space);
+ if (pcie_save_state)
+ kzfree(pcie_save_state);
+ if (pos)
+ kzfree(pos);
+}
+
static int tegra_pci_probe(struct platform_device *pdev)
{
- int ret;
+ int ret, size = 0, ndev = 0;
struct pci_dev *dev = NULL;
tegra_pcie.plat_data = pdev->dev.platform_data;
@@ -1194,39 +1246,91 @@ static int tegra_pci_probe(struct platform_device *pdev)
/* disable async PM of pci devices to ensure right order */
/* suspend/resume calls of tegra and bus driver */
- for_each_pci_dev(dev)
+ for_each_pci_dev(dev){
device_disable_async_suspend(&dev->dev);
+ size = sizeof(dev->saved_config_space) / sizeof(u32);
+ ndev++;
+ }
+ tegra_pcie_allocate_config_states(ndev, size);
return ret;
}
+static int tegra_pcie_save_state(struct pci_dev *pdev, int ndev)
+{
+ int size;
+
+ /*save pcie control registers */
+ pos[ndev] = pci_pcie_cap(pdev);
+ if (pos[ndev]){
+ pcie_save_state[ndev] = pci_find_saved_cap(pdev, PCI_CAP_ID_EXP);
+ if (!pcie_save_state[ndev]) {
+ dev_err(&pdev->dev, "buffer not found in %s\n", __func__);
+ return -ENOMEM;
+ }
+ memcpy(&pbackup_pcie_cap_space[PCIE_CTRL_REGS*(ndev/2)],
+ pcie_save_state[ndev]->cap.data, PCIE_CTRL_REGS*sizeof(u16));
+ }
+ /* save pcix state */
+ pos[ndev+1] = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
+ if (pos[ndev+1] > 0){
+ pcie_save_state[ndev+1] = pci_find_saved_cap(pdev, PCI_CAP_ID_PCIX);
+ if (!pcie_save_state[ndev+1]) {
+ dev_err(&pdev->dev, "buffer not found in %s\n", __func__);
+ return -ENOMEM;
+ }
+ memcpy(&pbackup_pcix_cap_space[ndev/2],
+ pcie_save_state[ndev+1]->cap.data, sizeof(u16));
+ }
+ /* save config space registers */
+ size = sizeof(pdev->saved_config_space) / sizeof(u32);
+ memcpy(&pbackup_config_space[size*ndev/2],
+ pdev->saved_config_space, size*sizeof(u32));
+
+ return 0;
+}
+
+static void tegra_pcie_restore_state(struct pci_dev *pdev, int ndev)
+{
+ int size;
+
+ /* restore pcie control registers */
+ if (pcie_save_state[ndev] && (pos[ndev] > 0))
+ memcpy(pcie_save_state[ndev]->cap.data,
+ &pbackup_pcie_cap_space[PCIE_CTRL_REGS*(ndev/2)],
+ PCIE_CTRL_REGS*sizeof(u16));
+
+ /* restore pcix state */
+ if (pcie_save_state[ndev+1] && (pos[ndev+1] > 0))
+ memcpy(pcie_save_state[ndev+1]->cap.data,
+ &pbackup_pcix_cap_space[ndev/2], sizeof(u16));
+
+ /* restore config space registers */
+ size = sizeof(pdev->saved_config_space) / sizeof(u32);
+ memcpy(pdev->saved_config_space,
+ &pbackup_config_space[size*ndev/2], size*sizeof(u32));
+}
+
static int tegra_pci_suspend(struct device *dev)
{
- int ret = 0;
+ int ret = 0, ndev = 0;
struct pci_dev *pdev = NULL;
- int i, size, ndev = 0;
if (!tegra_pcie.num_ports)
- return ret;
+ return ret;
for_each_pci_dev(pdev) {
/* save state of pcie devices before powering off regulators */
pci_save_state(pdev);
- size = sizeof(pdev->saved_config_space) / sizeof(u32);
- ndev++;
+ if (!pdev->subordinate)
+ pci_prepare_to_sleep(pdev);
}
- /* backup config space registers of all devices since it gets reset in
- save state call from suspend noirq due to disabling of read in it */
- pbackup_config_space = kzalloc(ndev * size* sizeof(u32), GFP_KERNEL);
- if (!pbackup_config_space)
- return -ENODEV;
- ndev = 0;
for_each_pci_dev(pdev) {
- for (i = 0;i < size;i++) {
- memcpy(&pbackup_config_space[i + size*ndev],
- &pdev->saved_config_space[i], sizeof(u32));
- }
+ /* save control and config space registers*/
+ ret = tegra_pcie_save_state(pdev, ndev*2);
+ if (ret < 0)
+ return ret;
ndev++;
}
@@ -1239,50 +1343,45 @@ static int tegra_pci_resume_noirq(struct device *dev)
{
struct pci_dev *pdev = NULL;
- for_each_pci_dev(pdev) {
- /* set this flag to avoid restore state in resume noirq */
+ /* set this flag to avoid restore state in resume noirq */
+ for_each_pci_dev(pdev)
pdev->state_saved = 0;
- }
+
return 0;
}
static int tegra_pci_resume(struct device *dev)
{
- int ret = 0;
- int i, size, ndev = 0;
+ int ret = 0, ndev = 0;
struct pci_dev *pdev = NULL;
+ int port;
if (!tegra_pcie.num_ports)
- return ret;
+ return ret;
ret = tegra_pcie_power_on();
+ /* enable read/write registers after powering on */
+ is_pcie_noirq_op = false;
tegra_pcie_enable_controller();
tegra_pcie_setup_translations();
- /* enable read/write registers after powering on */
- is_pcie_noirq_op = false;
+ for (port = 0; port < MAX_PCIE_SUPPORTED_PORTS; port++)
+ if (tegra_pcie.plat_data->port_status[port])
+ tegra_enable_clock_clamp(port);
for_each_pci_dev(pdev) {
- /* do fixup here for all dev's since not done in resume noirq */
- pci_fixup_device(pci_fixup_resume_early, pdev);
-
+ /* restore control and config space registers*/
+ tegra_pcie_restore_state(pdev, ndev*2);
/* set this flag to force restore state in resume */
pdev->state_saved = 1;
-
- /* restore config space registers from backup buffer */
- size = sizeof(pdev->saved_config_space) / sizeof(u32);
- for (i = 0;i < size;i++) {
- memcpy(&pdev->saved_config_space[i],
- &pbackup_config_space[i + size*ndev], sizeof(u32));
- }
ndev++;
}
- kzfree(pbackup_config_space);
return ret;
}
static int tegra_pci_remove(struct platform_device *pdev)
{
+ tegra_pcie_deallocate_config_states();
return 0;
}
#ifdef CONFIG_PM
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index af30cf2..fa88b11 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -779,8 +779,9 @@ static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
if (sel->input_rate == 0) {
unsigned long cfreq;
- BUG_ON(c->flags & PLLU);
struct clk_pll_freq_table cfg;
+
+ BUG_ON(c->flags & PLLU);
sel = &cfg;
switch (input_rate) {
@@ -2771,7 +2772,7 @@ unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate)
#ifdef CONFIG_PM_SLEEP
static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
- PERIPH_CLK_SOURCE_NUM + 22];
+ PERIPH_CLK_SOURCE_NUM + 24];
static int tegra_clk_suspend(void)
{
@@ -2779,6 +2780,8 @@ static int tegra_clk_suspend(void)
u32 *ctx = clk_rst_suspend;
*ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
+ *ctx++ = clk_readl(tegra_pll_p_out1.reg);
+ *ctx++ = clk_readl(tegra_pll_p_out3.reg);
*ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
*ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
*ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
@@ -2831,11 +2834,26 @@ static void tegra_clk_resume(void)
unsigned long off, i;
const u32 *ctx = clk_rst_suspend;
u32 val;
+ u32 pll_p_out12, pll_p_out34;
+ u32 pll_m_out1, pll_a_out0, pll_c_out1;
val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
val |= *ctx++;
clk_writel(val, OSC_CTRL);
+ /* Since we are going to reset devices and switch clock sources in this
+ * function, plls and secondary dividers is required to be enabled. The
+ * actual value will be restored back later. Note that boot plls: pllm,
+ * pllp, and pllu are already configured and enabled.
+ */
+
+ val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
+ val |= val << 16;
+ pll_p_out12 = *ctx++;
+ clk_writel(pll_p_out12 | val, tegra_pll_p_out1.reg);
+ pll_p_out34 = *ctx++;
+ clk_writel(pll_p_out34 | val, tegra_pll_p_out3.reg);
+
clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
@@ -2848,9 +2866,13 @@ static void tegra_clk_resume(void)
clk_writel(*ctx++, tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
udelay(1000);
- clk_writel(*ctx++, tegra_pll_m_out1.reg);
- clk_writel(*ctx++, tegra_pll_a_out0.reg);
- clk_writel(*ctx++, tegra_pll_c_out1.reg);
+ val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
+ pll_m_out1 = *ctx++;
+ clk_writel(pll_m_out1 | val, tegra_pll_m_out1.reg);
+ pll_a_out0 = *ctx++;
+ clk_writel(pll_a_out0 | val, tegra_pll_a_out0.reg);
+ pll_c_out1 = *ctx++;
+ clk_writel(pll_c_out1 | val, tegra_pll_c_out1.reg);
clk_writel(*ctx++, tegra_clk_cclk.reg);
clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
@@ -2887,6 +2909,13 @@ static void tegra_clk_resume(void)
clk_writel(*ctx++, MISC_CLK_ENB);
clk_writel(*ctx++, CLK_MASK_ARM);
+
+ /* Restore back the actual pll and secondary divider values */
+ clk_writel(pll_p_out12, tegra_pll_p_out1.reg);
+ clk_writel(pll_p_out34, tegra_pll_p_out3.reg);
+ clk_writel(pll_m_out1, tegra_pll_m_out1.reg);
+ clk_writel(pll_a_out0, tegra_pll_a_out0.reg);
+ clk_writel(pll_c_out1, tegra_pll_c_out1.reg);
}
#else
diff --git a/arch/arm/mach-tegra/tegra2_mc.c b/arch/arm/mach-tegra/tegra2_mc.c
index 6df9c23..1b72af0 100644
--- a/arch/arm/mach-tegra/tegra2_mc.c
+++ b/arch/arm/mach-tegra/tegra2_mc.c
@@ -896,8 +896,10 @@ static enum hrtimer_restart sample_timer_function(struct hrtimer *handle)
#define REGISTER_SYSFS(_name, _val) \
tegra_mc_dram_##_name##_kobj = \
kobject_create_and_add(#_name, tegra_mc_dram_kobj); \
- sysfs_create_group(tegra_mc_dram_##_name##_kobj, \
- &tegra_mc_dram_##_name##_attr_group);
+ if (sysfs_create_group(tegra_mc_dram_##_name##_kobj, \
+ &tegra_mc_dram_##_name##_attr_group)) \
+ printk(KERN_ERR "\n sysfs_create_group failed at %s" \
+ " line %d\n", __FILE__, __LINE__);
static int tegra_mc_init(void)
{
diff --git a/arch/arm/mach-tegra/tegra2_usb_phy.c b/arch/arm/mach-tegra/tegra2_usb_phy.c
new file mode 100644
index 00000000..819721c
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra2_usb_phy.c
@@ -0,0 +1,1598 @@
+/*
+ * arch/arm/mach-tegra/tegra2_usb_phy.c
+ *
+ * Copyright (C) 2011 NVIDIA Corporation
+ *
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/resource.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+#include <linux/platform_data/tegra_usb.h>
+#include <mach/iomap.h>
+#include <mach/pinmux.h>
+#include <asm/mach-types.h>
+#include <mach/usb_phy.h>
+#include "tegra_usb_phy.h"
+#include "fuse.h"
+
+
+#define USB_USBCMD 0x140
+#define USB_USBCMD_RS (1 << 0)
+#define USB_USBCMD_RESET (1 << 1)
+
+#define USB_USBSTS 0x144
+#define USB_USBSTS_PCI (1 << 2)
+#define USB_USBSTS_SRI (1 << 7)
+#define USB_USBSTS_HCH (1 << 12)
+
+#define USB_ASYNCLISTADDR 0x158
+
+#define USB_TXFILLTUNING 0x164
+#define USB_FIFO_TXFILL_THRES(x) (((x) & 0x1f) << 16)
+#define USB_FIFO_TXFILL_MASK 0x1f0000
+
+#define ULPI_VIEWPORT 0x170
+#define ULPI_WAKEUP (1 << 31)
+#define ULPI_RUN (1 << 30)
+#define ULPI_RD_WR (1 << 29)
+
+#define USB_PORTSC 0x184
+#define USB_PORTSC_PTS(x) (((x) & 0x3) << 30)
+#define USB_PORTSC_PSPD(x) (((x) & 0x3) << 26)
+#define USB_PORTSC_PHCD (1 << 23)
+#define USB_PORTSC_WKOC (1 << 22)
+#define USB_PORTSC_WKDS (1 << 21)
+#define USB_PORTSC_WKCN (1 << 20)
+#define USB_PORTSC_PTC(x) (((x) & 0xf) << 16)
+#define USB_PORTSC_PP (1 << 12)
+#define USB_PORTSC_LS(x) (((x) & 0x3) << 10)
+#define USB_PORTSC_SUSP (1 << 7)
+#define USB_PORTSC_OCC (1 << 5)
+#define USB_PORTSC_PEC (1 << 3)
+#define USB_PORTSC_PE (1 << 2)
+#define USB_PORTSC_CSC (1 << 1)
+#define USB_PORTSC_CCS (1 << 0)
+#define USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
+#define USB_PORTSC_PSPD_MASK 3
+
+#define USB_USBMODE_REG_OFFSET 0x1a8
+#define USB_USBMODE_MASK (3 << 0)
+#define USB_USBMODE_HOST (3 << 0)
+#define USB_USBMODE_DEVICE (2 << 0)
+
+#define USB_SUSP_CTRL 0x400
+#define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
+#define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
+#define USB_SUSP_CLR (1 << 5)
+#define USB_CLKEN (1 << 6)
+#define USB_PHY_CLK_VALID (1 << 7)
+#define USB_PHY_CLK_VALID_INT_ENB (1 << 9)
+#define UTMIP_RESET (1 << 11)
+#define UHSIC_RESET (1 << 11)
+#define UTMIP_PHY_ENABLE (1 << 12)
+#define UHSIC_PHY_ENABLE (1 << 12)
+#define ULPI_PHY_ENABLE (1 << 13)
+#define USB_SUSP_SET (1 << 14)
+#define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
+#define USB_PHY_CLK_VALID_INT_STS (1 << 8)
+
+#define USB_PHY_VBUS_WAKEUP_ID 0x408
+#define VDAT_DET_INT_EN (1 << 16)
+#define VDAT_DET_CHG_DET (1 << 17)
+#define VDAT_DET_STS (1 << 18)
+#define USB_ID_STATUS (1 << 2)
+
+#define USB1_LEGACY_CTRL 0x410
+#define USB1_NO_LEGACY_MODE (1 << 0)
+#define USB1_VBUS_SENSE_CTL_MASK (3 << 1)
+#define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1)
+#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
+ (1 << 1)
+#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1)
+#define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1)
+
+#define ULPIS2S_CTRL 0x418
+#define ULPIS2S_ENA (1 << 0)
+#define ULPIS2S_SUPPORT_DISCONNECT (1 << 2)
+#define ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
+#define ULPIS2S_SPARE(x) (((x) & 0xF) << 8)
+#define ULPIS2S_FORCE_ULPI_CLK_OUT (1 << 12)
+#define ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
+#define ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
+#define ULPIS2S_DISABLE_STP_PU (1 << 15)
+#define ULPIS2S_SLV0_CLAMP_XMIT (1 << 16)
+
+#define ULPI_TIMING_CTRL_0 0x424
+#define ULPI_CLOCK_OUT_DELAY(x) ((x) & 0x1F)
+#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
+#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
+#define ULPI_SHADOW_CLK_LOOPBACK_EN (1 << 12)
+#define ULPI_SHADOW_CLK_SEL (1 << 13)
+#define ULPI_CORE_CLK_SEL (1 << 14)
+#define ULPI_SHADOW_CLK_DELAY(x) (((x) & 0x1F) << 16)
+#define ULPI_LBK_PAD_EN (1 << 26)
+#define ULPI_LBK_PAD_E_INPUT_OR (1 << 27)
+#define ULPI_CLK_OUT_ENA (1 << 28)
+#define ULPI_CLK_PADOUT_ENA (1 << 29)
+
+#define ULPI_TIMING_CTRL_1 0x428
+#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
+#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
+#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
+#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
+#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
+#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
+
+#define UTMIP_PLL_CFG1 0x804
+#define UHSIC_PLL_CFG1 0x804
+#define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
+#define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
+#define UHSIC_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
+#define UHSIC_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 14)
+
+#define UTMIP_XCVR_UHSIC_HSRX_CFG0 0x808
+#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
+#define UHSIC_ELASTIC_UNDERRUN_LIMIT(x) (((x) & 0x1f) << 2)
+#define UHSIC_ELASTIC_OVERRUN_LIMIT(x) (((x) & 0x1f) << 8)
+#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
+#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
+#define UHSIC_IDLE_WAIT(x) (((x) & 0x1f) << 13)
+#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
+#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
+#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
+#define UTMIP_XCVR_LSBIAS_SEL (1 << 21)
+#define UTMIP_XCVR_SETUP_MSB(x) (((x) & 0x7) << 22)
+#define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25)
+#define UTMIP_XCVR_MAX_OFFSET 2
+#define UTMIP_XCVR_SETUP_MAX_VALUE 0x7f
+#define UTMIP_XCVR_SETUP_MIN_VALUE 0
+#define XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
+
+#define UTMIP_BIAS_CFG0 0x80c
+#define UTMIP_OTGPD (1 << 11)
+#define UTMIP_BIASPD (1 << 10)
+
+#define UHSIC_HSRX_CFG1 0x80c
+#define UHSIC_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
+
+#define UTMIP_HSRX_CFG0 0x810
+#define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
+#define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
+
+#define UTMIP_HSRX_CFG1 0x814
+#define UHSIC_MISC_CFG0 0x814
+#define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
+#define UHSIC_SUSPEND_EXIT_ON_EDGE (1 << 7)
+#define UHSIC_DETECT_SHORT_CONNECT (1 << 8)
+#define UHSIC_FORCE_XCVR_MODE (1 << 15)
+
+#define UHSIC_MISC_CFG1 0x818
+#define UHSIC_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 2)
+
+#define UHSIC_PADS_CFG0 0x81c
+#define UHSIC_TX_RTUNEN 0xf000
+#define UHSIC_TX_RTUNE(x) (((x) & 0xf) << 12)
+
+#define UTMIP_TX_CFG0 0x820
+#define UHSIC_PADS_CFG1 0x820
+#define UHSIC_PD_BG (1 << 2)
+#define UHSIC_PD_TX (1 << 3)
+#define UHSIC_PD_TRK (1 << 4)
+#define UHSIC_PD_RX (1 << 5)
+#define UHSIC_PD_ZI (1 << 6)
+#define UHSIC_RX_SEL (1 << 7)
+#define UHSIC_RPD_DATA (1 << 9)
+#define UHSIC_RPD_STROBE (1 << 10)
+#define UHSIC_RPU_DATA (1 << 11)
+#define UHSIC_RPU_STROBE (1 << 12)
+#define UTMIP_FS_PREABMLE_J (1 << 19)
+#define UTMIP_HS_DISCON_DISABLE (1 << 8)
+
+#define UTMIP_MISC_CFG0 0x824
+#define UTMIP_DPDM_OBSERVE (1 << 26)
+#define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
+#define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
+#define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
+#define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
+#define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
+#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
+#define FORCE_PULLDN_DM (1 << 8)
+#define FORCE_PULLDN_DP (1 << 9)
+#define COMB_TERMS (1 << 0)
+#define ALWAYS_FREE_RUNNING_TERMS (1 << 1)
+
+#define USB1_PREFETCH_ID 6
+#define USB2_PREFETCH_ID 18
+#define USB3_PREFETCH_ID 17
+
+#define UTMIP_MISC_CFG1 0x828
+#define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
+#define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6)
+
+#define UHSIC_STAT_CFG0 0x828
+#define UHSIC_CONNECT_DETECT (1 << 0)
+
+#define UTMIP_DEBOUNCE_CFG0 0x82c
+#define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
+
+#define UTMIP_BAT_CHRG_CFG0 0x830
+#define UTMIP_PD_CHRG (1 << 0)
+#define UTMIP_ON_SINK_EN (1 << 2)
+#define UTMIP_OP_SRC_EN (1 << 3)
+
+#define UTMIP_SPARE_CFG0 0x834
+#define FUSE_SETUP_SEL (1 << 3)
+#define FUSE_ATERM_SEL (1 << 4)
+
+#define UTMIP_XCVR_CFG1 0x838
+#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
+#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
+#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
+#define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
+
+#define UTMIP_BIAS_CFG1 0x83c
+#define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
+
+#define FUSE_USB_CALIB_0 0x1F0
+#define FUSE_USB_CALIB_XCVR_SETUP(x) (((x) & 0x7F) << 0)
+
+/* These values (in milli second) are taken from the battery charging spec */
+#define TDP_SRC_ON_MS 100
+#define TDPSRC_CON_MS 40
+
+#ifdef DEBUG
+#define DBG(stuff...) pr_info("tegra2_usb_phy: " stuff)
+#else
+#define DBG(stuff...) do {} while (0)
+#endif
+
+static DEFINE_SPINLOCK(utmip_pad_lock);
+static int utmip_pad_count;
+static int utmip_pad_state_on;
+
+static struct tegra_xtal_freq utmip_freq_table[] = {
+ {
+ .freq = 12000000,
+ .enable_delay = 0x02,
+ .stable_count = 0x2F,
+ .active_delay = 0x04,
+ .xtal_freq_count = 0x76,
+ .debounce = 0x7530,
+ .pdtrk_count = 5,
+ },
+ {
+ .freq = 13000000,
+ .enable_delay = 0x02,
+ .stable_count = 0x33,
+ .active_delay = 0x05,
+ .xtal_freq_count = 0x7F,
+ .debounce = 0x7EF4,
+ .pdtrk_count = 5,
+ },
+ {
+ .freq = 19200000,
+ .enable_delay = 0x03,
+ .stable_count = 0x4B,
+ .active_delay = 0x06,
+ .xtal_freq_count = 0xBB,
+ .debounce = 0xBB80,
+ .pdtrk_count = 7,
+ },
+ {
+ .freq = 26000000,
+ .enable_delay = 0x04,
+ .stable_count = 0x66,
+ .active_delay = 0x09,
+ .xtal_freq_count = 0xFE,
+ .debounce = 0xFDE8,
+ .pdtrk_count = 9,
+ },
+};
+
+static struct tegra_xtal_freq uhsic_freq_table[] = {
+ {
+ .freq = 12000000,
+ .enable_delay = 0x02,
+ .stable_count = 0x2F,
+ .active_delay = 0x0,
+ .xtal_freq_count = 0x1CA,
+ },
+ {
+ .freq = 13000000,
+ .enable_delay = 0x02,
+ .stable_count = 0x33,
+ .active_delay = 0x0,
+ .xtal_freq_count = 0x1F0,
+ },
+ {
+ .freq = 19200000,
+ .enable_delay = 0x03,
+ .stable_count = 0x4B,
+ .active_delay = 0x0,
+ .xtal_freq_count = 0x2DD,
+ },
+ {
+ .freq = 26000000,
+ .enable_delay = 0x04,
+ .stable_count = 0x66,
+ .active_delay = 0x0,
+ .xtal_freq_count = 0x3E0,
+ },
+};
+
+static void usb_phy_fence_read(struct tegra_usb_phy *phy)
+{
+ /* Fence read for coherency of AHB master intiated writes */
+ if (phy->inst == 0)
+ readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
+ else if (phy->inst == 1)
+ readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
+ else if (phy->inst == 2)
+ readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
+
+ return;
+}
+
+static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d] - 0\n",
+ readl(base + USB_USBSTS), readl(base + USB_PORTSC),
+ phy->port_speed);
+
+ /* enable host mode */
+ val = readl(base + USB_USBMODE_REG_OFFSET);
+ val |= USB_USBMODE_HOST;
+ writel(val, base + USB_USBMODE_REG_OFFSET);
+
+ /* Enable Port Power */
+ val = readl(base + USB_PORTSC);
+ val |= USB_PORTSC_PP;
+ writel(val, base + USB_PORTSC);
+ udelay(10);
+
+ /* Check if the phy resume from LP0. When the phy resume from LP0
+ * USB register will be reset.to zero */
+ if (!readl(base + USB_ASYNCLISTADDR)) {
+ val = readl(base + USB_USBCMD);
+ val |= USB_USBCMD_RS;
+ writel(val, base + USB_USBCMD);
+
+ /* Program the field PTC based on the saved speed mode */
+ val = readl(base + USB_PORTSC);
+ val &= ~(USB_PORTSC_PTC(~0));
+ if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
+ val |= USB_PORTSC_PTC(5);
+ else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
+ val |= USB_PORTSC_PTC(6);
+ else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
+ val |= USB_PORTSC_PTC(7);
+ writel(val, base + USB_PORTSC);
+ udelay(10);
+
+ /* Disable test mode by setting PTC field to NORMAL_OP */
+ val = readl(base + USB_PORTSC);
+ val &= ~(USB_PORTSC_PTC(~0));
+ writel(val, base + USB_PORTSC);
+ udelay(10);
+ }
+
+ /* Poll until CCS is enabled */
+ if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
+ USB_PORTSC_CCS, 2000)) {
+ pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
+ }
+
+ /* Poll until PE is enabled */
+ if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
+ USB_PORTSC_PE, 2000)) {
+ pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
+ }
+
+ /* Clear the PCI status, to avoid an interrupt taken upon resume */
+ val = readl(base + USB_USBSTS);
+ val |= USB_USBSTS_PCI;
+ writel(val, base + USB_USBSTS);
+
+ /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
+ val = readl(base + USB_PORTSC);
+ if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
+ val |= USB_PORTSC_SUSP;
+ writel(val, base + USB_PORTSC);
+ /* Need a 4ms delay before the controller goes to suspend */
+ mdelay(4);
+
+ /* Wait until port suspend completes */
+ if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
+ USB_PORTSC_SUSP, 1000)) {
+ pr_err("%s: timeout waiting for PORT_SUSPEND\n",
+ __func__);
+ }
+ }
+
+ DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
+ readl(base + USB_USBSTS), readl(base + USB_PORTSC));
+
+ return 0;
+}
+
+static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ val = readl(base + USB_USBSTS);
+ writel(val, base + USB_USBSTS);
+ udelay(20);
+ /* wait for two SOFs */
+ if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
+ USB_USBSTS_SRI, 2500))
+ pr_err("%s: timeout waiting for SOF\n", __func__);
+
+ val = readl(base + USB_USBSTS);
+ writel(val, base + USB_USBSTS);
+ if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
+ pr_err("%s: timeout waiting for SOF\n", __func__);
+
+ if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
+ USB_USBSTS_SRI, 2500))
+ pr_err("%s: timeout waiting for SOF\n", __func__);
+
+ udelay(20);
+}
+
+static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
+{
+ struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
+ signed long val;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ if (cfg->xcvr_use_fuses) {
+ val = FUSE_USB_CALIB_XCVR_SETUP(
+ tegra_fuse_readl(FUSE_USB_CALIB_0));
+ if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
+ val = val + cfg->xcvr_setup_offset;
+
+ if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
+ val = UTMIP_XCVR_SETUP_MAX_VALUE;
+ pr_info("%s: reset XCVR_SETUP to max value\n",
+ __func__);
+ } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
+ val = UTMIP_XCVR_SETUP_MIN_VALUE;
+ pr_info("%s: reset XCVR_SETUP to min value\n",
+ __func__);
+ }
+ } else {
+ val = cfg->xcvr_setup;
+ }
+
+ return (unsigned int) val;
+}
+
+
+static int utmi_phy_open(struct tegra_usb_phy *phy)
+{
+ unsigned long parent_rate;
+ int i;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
+ if (IS_ERR(phy->utmi_pad_clk)) {
+ pr_err("%s: can't get utmip pad clock\n", __func__);
+ return PTR_ERR(phy->utmi_pad_clk);
+ }
+
+ phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
+
+ parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
+ for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
+ if (utmip_freq_table[i].freq == parent_rate) {
+ phy->freq = &utmip_freq_table[i];
+ break;
+ }
+ }
+ if (!phy->freq) {
+ pr_err("invalid pll_u parent rate %ld\n", parent_rate);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void utmi_phy_close(struct tegra_usb_phy *phy)
+{
+ DBG("%s inst:[%d]\n", __func__, phy->inst);
+
+ clk_put(phy->utmi_pad_clk);
+}
+
+static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
+{
+ unsigned long val, flags;
+ void __iomem *pad_base = IO_ADDRESS(TEGRA_USB_BASE);
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ clk_enable(phy->utmi_pad_clk);
+
+ spin_lock_irqsave(&utmip_pad_lock, flags);
+
+ utmip_pad_count++;
+ val = readl(pad_base + UTMIP_BIAS_CFG0);
+ val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
+ writel(val, pad_base + UTMIP_BIAS_CFG0);
+ utmip_pad_state_on = true;
+
+ spin_unlock_irqrestore(&utmip_pad_lock, flags);
+
+ clk_disable(phy->utmi_pad_clk);
+
+ return 0;
+}
+
+static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
+{
+ unsigned long val, flags;
+ void __iomem *pad_base = IO_ADDRESS(TEGRA_USB_BASE);
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ clk_enable(phy->utmi_pad_clk);
+ spin_lock_irqsave(&utmip_pad_lock, flags);
+
+ if (!utmip_pad_count) {
+ pr_err("%s: utmip pad already powered off\n", __func__);
+ goto out;
+ }
+ if (--utmip_pad_count == 0) {
+ val = readl(pad_base + UTMIP_BIAS_CFG0);
+ val |= UTMIP_OTGPD | UTMIP_BIASPD;
+ writel(val, pad_base + UTMIP_BIAS_CFG0);
+ utmip_pad_state_on = false;
+ }
+out:
+ spin_unlock_irqrestore(&utmip_pad_lock, flags);
+ clk_disable(phy->utmi_pad_clk);
+
+ return 0;
+}
+
+static int utmi_phy_irq(struct tegra_usb_phy *phy)
+{
+ void __iomem *base = phy->regs;
+ unsigned long val = 0;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ usb_phy_fence_read(phy);
+ if (phy->pdata->u_data.host.hot_plug) {
+ val = readl(base + USB_SUSP_CTRL);
+ if ((val & USB_PHY_CLK_VALID_INT_STS)) {
+ val &= ~USB_PHY_CLK_VALID_INT_ENB |
+ USB_PHY_CLK_VALID_INT_STS;
+ writel(val , (base + USB_SUSP_CTRL));
+ pr_info("%s: usb device plugged-in\n", __func__);
+ val = readl(base + USB_USBSTS);
+ if (!(val & USB_USBSTS_PCI))
+ return IRQ_NONE;
+ val = readl(base + USB_PORTSC);
+ val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
+ writel(val , (base + USB_PORTSC));
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+
+static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ val = readl(base + UTMIP_TX_CFG0);
+ val &= ~UTMIP_HS_DISCON_DISABLE;
+ writel(val, base + UTMIP_TX_CFG0);
+ return 0;
+}
+
+static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ val = readl(base + UTMIP_TX_CFG0);
+ val |= UTMIP_HS_DISCON_DISABLE;
+ writel(val, base + UTMIP_TX_CFG0);
+
+ usb_phy_wait_for_sof(phy);
+
+ return 0;
+}
+
+static int utmi_phy_power_off(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ if (!phy->phy_clk_on) {
+ DBG("%s(%d) inst:[%d] phy clk is already off\n",
+ __func__, __LINE__, phy->inst);
+ return 0;
+ }
+
+ if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~(USB_WAKEUP_DEBOUNCE_COUNT(~0));
+ val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
+ writel(val, base + USB_SUSP_CTRL);
+
+ val = readl(base + UTMIP_BAT_CHRG_CFG0);
+ val |= UTMIP_PD_CHRG;
+ writel(val, base + UTMIP_BAT_CHRG_CFG0);
+ }
+
+ if (!phy->pdata->u_data.host.hot_plug) {
+ val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
+ val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
+ UTMIP_FORCE_PDZI_POWERDOWN);
+ writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
+ }
+
+ val = readl(base + UTMIP_XCVR_CFG1);
+ val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
+ UTMIP_FORCE_PDDR_POWERDOWN;
+ writel(val, base + UTMIP_XCVR_CFG1);
+
+ if (phy->inst != 0) {
+ val = readl(base + UTMIP_BIAS_CFG0);
+ val |= UTMIP_OTGPD;
+ writel(val, base + UTMIP_BIAS_CFG0);
+ }
+
+ phy->port_speed = (readl(base + USB_PORTSC) >> 26) &
+ USB_PORTSC_PSPD_MASK;
+
+ if (phy->pdata->u_data.host.hot_plug) {
+ bool enable_hotplug = true;
+ /* if it is OTG port then make sure to enable hot-plug feature
+ only if host adaptor is connected, i.e id is low */
+ if (phy->pdata->port_otg) {
+ val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
+ enable_hotplug = (val & USB_ID_STATUS) ? false : true;
+ }
+ if (enable_hotplug) {
+ val = readl(base + USB_PORTSC);
+ val |= USB_PORTSC_WKCN;
+ writel(val, base + USB_PORTSC);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= USB_PHY_CLK_VALID_INT_ENB;
+ writel(val, base + USB_SUSP_CTRL);
+ } else {
+ /* Disable PHY clock valid interrupts while going into suspend*/
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~USB_PHY_CLK_VALID_INT_ENB;
+ writel(val, base + USB_SUSP_CTRL);
+ }
+ }
+
+ if (phy->inst == 2) {
+ val = readl(base + USB_PORTSC);
+ val |= USB_PORTSC_PHCD;
+ writel(val, base + USB_PORTSC);
+ } else {
+ val = readl(base + USB_SUSP_CTRL);
+ val |= USB_SUSP_SET;
+ writel(val, base + USB_SUSP_CTRL);
+ udelay(10);
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~USB_SUSP_SET;
+ writel(val, base + USB_SUSP_CTRL);
+ }
+
+ if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
+ 0, 2500))
+ pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
+
+ utmi_phy_pad_power_off(phy);
+
+ phy->phy_clk_on = false;
+ phy->hw_accessible = false;
+
+ DBG("%s(%d) inst:[%d]END\n", __func__, __LINE__, phy->inst);
+
+ return 0;
+}
+
+static int utmi_phy_power_on(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+ struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ if (phy->phy_clk_on) {
+ DBG("%s(%d) inst:[%d] phy clk is already on\n",
+ __func__, __LINE__, phy->inst);
+ return 0;
+ }
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= UTMIP_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+
+ val = readl(base + UTMIP_TX_CFG0);
+ val |= UTMIP_FS_PREABMLE_J;
+ writel(val, base + UTMIP_TX_CFG0);
+
+ val = readl(base + UTMIP_HSRX_CFG0);
+ val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
+ val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
+ val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
+ writel(val, base + UTMIP_HSRX_CFG0);
+
+ val = readl(base + UTMIP_HSRX_CFG1);
+ val &= ~(UTMIP_HS_SYNC_START_DLY(~0));
+ val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
+ writel(val, base + UTMIP_HSRX_CFG1);
+
+ val = readl(base + UTMIP_DEBOUNCE_CFG0);
+ val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
+ val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
+ writel(val, base + UTMIP_DEBOUNCE_CFG0);
+
+ val = readl(base + UTMIP_MISC_CFG0);
+ val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
+ writel(val, base + UTMIP_MISC_CFG0);
+
+ val = readl(base + UTMIP_MISC_CFG1);
+ val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
+ val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
+ UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
+ writel(val, base + UTMIP_MISC_CFG1);
+
+ val = readl(base + UTMIP_PLL_CFG1);
+ val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
+ val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
+ UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
+ writel(val, base + UTMIP_PLL_CFG1);
+
+ if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
+ writel(val, base + USB_SUSP_CTRL);
+
+ val = readl(base + UTMIP_BAT_CHRG_CFG0);
+ val &= ~UTMIP_PD_CHRG;
+ writel(val, base + UTMIP_BAT_CHRG_CFG0);
+ } else {
+ val = readl(base + UTMIP_BAT_CHRG_CFG0);
+ val |= UTMIP_PD_CHRG;
+ writel(val, base + UTMIP_BAT_CHRG_CFG0);
+ }
+
+ utmi_phy_pad_power_on(phy);
+
+ val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
+ val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
+ UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
+ UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
+ UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
+ val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
+ val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
+ val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
+ val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
+
+ writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
+
+ val = readl(base + UTMIP_XCVR_CFG1);
+ val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
+ UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
+ val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
+ writel(val, base + UTMIP_XCVR_CFG1);
+
+
+ val = readl(base + UTMIP_BIAS_CFG1);
+ val &= ~(UTMIP_BIAS_PDTRK_COUNT(~0));
+ val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
+ writel(val, base + UTMIP_BIAS_CFG1);
+
+ val = readl(base + UTMIP_SPARE_CFG0);
+ val &= ~FUSE_SETUP_SEL;
+ writel(val, base + UTMIP_SPARE_CFG0);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= UTMIP_PHY_ENABLE;
+ writel(val, base + USB_SUSP_CTRL);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~UTMIP_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+
+ if (phy->inst == 0) {
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~USB_SUSP_SET;
+ writel(val, base + USB_SUSP_CTRL);
+ } else {
+ val = readl(base + USB_PORTSC);
+ val &= ~USB_PORTSC_PHCD;
+ writel(val, base + USB_PORTSC);
+ }
+
+ if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
+ USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
+ pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
+
+ if (phy->inst == 2) {
+ val = readl(base + USB_PORTSC);
+ val &= ~(USB_PORTSC_PTS(~0));
+ writel(val, base + USB_PORTSC);
+ }
+
+ phy->phy_clk_on = true;
+ phy->hw_accessible = true;
+
+ return 0;
+}
+
+static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ val = readl(base + UTMIP_MISC_CFG0);
+ val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
+
+ if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
+ val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
+ else
+ val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
+ writel(val, base + UTMIP_MISC_CFG0);
+ udelay(1);
+
+ val = readl(base + UTMIP_MISC_CFG0);
+ val |= UTMIP_DPDM_OBSERVE;
+ writel(val, base + UTMIP_MISC_CFG0);
+ udelay(10);
+}
+
+static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ val = readl(base + UTMIP_MISC_CFG0);
+ val &= ~UTMIP_DPDM_OBSERVE;
+ writel(val, base + UTMIP_MISC_CFG0);
+ udelay(10);
+}
+
+
+static int utmi_phy_resume(struct tegra_usb_phy *phy)
+{
+ int status = 0;
+ unsigned long val, flags;
+ void __iomem *base = phy->regs;
+ void __iomem *pad_base = IO_ADDRESS(TEGRA_USB_BASE);
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
+ if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
+ utmi_phy_restore_start(phy);
+ usb_phy_bringup_host_controller(phy);
+ utmi_phy_restore_end(phy);
+ } else {
+ /* device is plugged in when system is in LP0 */
+ /* bring up the controller from LP0*/
+ val = readl(base + USB_USBCMD);
+ val |= USB_USBCMD_RESET;
+ writel(val, base + USB_USBCMD);
+
+ if (usb_phy_reg_status_wait(base + USB_USBCMD,
+ USB_USBCMD_RESET, 0, 2500) < 0) {
+ pr_err("%s: timeout waiting for reset\n", __func__);
+ }
+
+ val = readl(base + USB_USBMODE_REG_OFFSET);
+ val &= ~USB_USBMODE_MASK;
+ val |= USB_USBMODE_HOST;
+ writel(val, base + USB_USBMODE_REG_OFFSET);
+
+ if (phy->inst == 2) {
+ val = readl(base + USB_PORTSC);
+ val &= ~USB_PORTSC_PTS(~0);
+ writel(val, base + USB_PORTSC);
+ }
+ writel(USB_USBCMD_RS, base + USB_USBCMD);
+
+ if (usb_phy_reg_status_wait(base + USB_USBCMD,
+ USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
+ pr_err("%s: timeout waiting for run bit\n", __func__);
+ }
+
+ /* Enable Port Power */
+ val = readl(base + USB_PORTSC);
+ val |= USB_PORTSC_PP;
+ writel(val, base + USB_PORTSC);
+ udelay(10);
+
+ DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
+ readl(base + USB_USBSTS), readl(base + USB_PORTSC));
+ }
+ } else {
+ /* Restoring the pad powers */
+ clk_enable(phy->utmi_pad_clk);
+
+ spin_lock_irqsave(&utmip_pad_lock, flags);
+
+ val = readl(pad_base + UTMIP_BIAS_CFG0);
+ if (utmip_pad_state_on)
+ val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
+ else
+ val |= (UTMIP_OTGPD | UTMIP_BIASPD);
+ writel(val, pad_base + UTMIP_BIAS_CFG0);
+
+ spin_unlock_irqrestore(&utmip_pad_lock, flags);
+ clk_disable(phy->utmi_pad_clk);
+ }
+
+ return status;
+}
+
+static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+ bool status;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ /* Enable charger detection logic */
+ val = readl(base + UTMIP_BAT_CHRG_CFG0);
+ val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
+ writel(val, base + UTMIP_BAT_CHRG_CFG0);
+
+ /* Source should be on for 100 ms as per USB charging spec */
+ msleep(TDP_SRC_ON_MS);
+
+ val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
+ /* If charger is not connected disable the interrupt */
+ val &= ~VDAT_DET_INT_EN;
+ val |= VDAT_DET_CHG_DET;
+ writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
+
+ val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
+ if (val & VDAT_DET_STS)
+ status = true;
+ else
+ status = false;
+
+ /* Disable charger detection logic */
+ val = readl(base + UTMIP_BAT_CHRG_CFG0);
+ val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
+ writel(val, base + UTMIP_BAT_CHRG_CFG0);
+
+ /* Delay of 40 ms before we pull the D+ as per battery charger spec */
+ msleep(TDPSRC_CON_MS);
+
+ return status;
+}
+
+
+static int uhsic_phy_open(struct tegra_usb_phy *phy)
+{
+ unsigned long parent_rate;
+ int i;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
+ for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
+ if (uhsic_freq_table[i].freq == parent_rate) {
+ phy->freq = &uhsic_freq_table[i];
+ break;
+ }
+ }
+ if (!phy->freq) {
+ pr_err("invalid pll_u parent rate %ld\n", parent_rate);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int uhsic_phy_irq(struct tegra_usb_phy *phy)
+{
+ usb_phy_fence_read(phy);
+ return IRQ_HANDLED;
+}
+
+static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+ struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ if (phy->phy_clk_on) {
+ DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
+ __LINE__, phy->inst);
+ return 0;
+ }
+
+ val = readl(base + UHSIC_PADS_CFG1);
+ val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
+ UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
+ val |= UHSIC_RX_SEL;
+ writel(val, base + UHSIC_PADS_CFG1);
+ udelay(2);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= UHSIC_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+ udelay(30);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= UHSIC_PHY_ENABLE;
+ writel(val, base + USB_SUSP_CTRL);
+
+ val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
+ val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
+ val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
+ val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
+ writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
+
+ val = readl(base + UHSIC_HSRX_CFG1);
+ val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
+ writel(val, base + UHSIC_HSRX_CFG1);
+
+ val = readl(base + UHSIC_MISC_CFG0);
+ val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
+ writel(val, base + UHSIC_MISC_CFG0);
+
+ val = readl(base + UHSIC_MISC_CFG1);
+ val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
+ writel(val, base + UHSIC_MISC_CFG1);
+
+ val = readl(base + UHSIC_PLL_CFG1);
+ val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
+ val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
+ writel(val, base + UHSIC_PLL_CFG1);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~(UHSIC_RESET);
+ writel(val, base + USB_SUSP_CTRL);
+ udelay(2);
+
+ val = readl(base + USB_PORTSC);
+ val &= ~(USB_PORTSC_PTS(~0));
+ writel(val, base + USB_PORTSC);
+
+ val = readl(base + USB_TXFILLTUNING);
+ if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
+ val = USB_FIFO_TXFILL_THRES(0x10);
+ writel(val, base + USB_TXFILLTUNING);
+ }
+
+ val = readl(base + USB_PORTSC);
+ val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
+ writel(val, base + USB_PORTSC);
+
+ val = readl(base + UHSIC_PADS_CFG0);
+ val &= ~(UHSIC_TX_RTUNEN);
+ /* set Rtune impedance to 40 ohm */
+ val |= UHSIC_TX_RTUNE(0);
+ writel(val, base + UHSIC_PADS_CFG0);
+
+ if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
+ USB_PHY_CLK_VALID, 2500)) {
+ pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ phy->phy_clk_on = true;
+ phy->hw_accessible = true;
+
+ return 0;
+}
+
+static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ if (!phy->phy_clk_on) {
+ DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
+ __LINE__, phy->inst);
+ return 0;
+ }
+
+ val = readl(base + UHSIC_PADS_CFG1);
+ val &= ~UHSIC_RPU_STROBE;
+ val |= UHSIC_RPD_STROBE;
+ writel(val, base + UHSIC_PADS_CFG1);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= UHSIC_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+ udelay(30);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~UHSIC_PHY_ENABLE;
+ writel(val, base + USB_SUSP_CTRL);
+
+ phy->phy_clk_on = false;
+ phy->hw_accessible = false;
+
+ return 0;
+}
+
+static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ val = readl(base + UHSIC_MISC_CFG0);
+ val |= UHSIC_DETECT_SHORT_CONNECT;
+ writel(val, base + UHSIC_MISC_CFG0);
+ udelay(1);
+
+ val = readl(base + UHSIC_MISC_CFG0);
+ val |= UHSIC_FORCE_XCVR_MODE;
+ writel(val, base + UHSIC_MISC_CFG0);
+
+ val = readl(base + UHSIC_PADS_CFG1);
+ val &= ~UHSIC_RPD_STROBE;
+ val |= UHSIC_RPU_STROBE;
+ writel(val, base + UHSIC_PADS_CFG1);
+
+ val = readl(base + USB_USBCMD);
+ val &= ~USB_USBCMD_RS;
+ writel(val, base + USB_USBCMD);
+
+ if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
+ UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 2000)) {
+ pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
+ __func__);
+ return -ETIMEDOUT;
+ }
+
+/* FIXME : need to check whether this piece is required or not
+ if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(2),
+ USB_PORTSC_LS(2), 2000)) {
+ pr_err("%s: timeout waiting for dplus state\n", __func__);
+ return -ETIMEDOUT;
+ }
+*/
+ return 0;
+}
+
+
+static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ val = readl(base + USB_PORTSC);
+ val |= USB_PORTSC_PTC(5);
+ writel(val, base + USB_PORTSC);
+ udelay(2);
+
+ val = readl(base + USB_PORTSC);
+ val &= ~(USB_PORTSC_PTC(~0));
+ writel(val, base + USB_PORTSC);
+ udelay(2);
+
+ if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
+ 0, 2000)) {
+ pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ /* Poll until CCS is enabled */
+ if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
+ USB_PORTSC_CCS, 2000)) {
+ pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PSPD(2),
+ USB_PORTSC_PSPD(2), 2000)) {
+ pr_err("%s: timeout waiting for USB_PORTSC_PSPD\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ val = readl(base + USB_USBCMD);
+ val &= ~USB_USBCMD_RS;
+ writel(val, base + USB_USBCMD);
+
+ if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
+ USB_USBSTS_HCH, 2000)) {
+ pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ val = readl(base + UHSIC_PADS_CFG1);
+ val &= ~UHSIC_RPU_STROBE;
+ val |= UHSIC_RPD_STROBE;
+ writel(val, base + UHSIC_PADS_CFG1);
+
+ mdelay(50);
+
+ val = readl(base + UHSIC_PADS_CFG1);
+ val &= ~UHSIC_RPD_STROBE;
+ val |= UHSIC_RPU_STROBE;
+ writel(val, base + UHSIC_PADS_CFG1);
+
+ val = readl(base + USB_USBCMD);
+ val |= USB_USBCMD_RS;
+ writel(val, base + USB_USBCMD);
+
+ val = readl(base + UHSIC_PADS_CFG1);
+ val &= ~UHSIC_RPU_STROBE;
+ writel(val, base + UHSIC_PADS_CFG1);
+
+ if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
+ USB_USBCMD_RS, 2000)) {
+ pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+
+static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
+{
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ usb_phy_wait_for_sof(phy);
+
+ return 0;
+}
+
+static int uhsic_phy_resume(struct tegra_usb_phy *phy)
+{
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ uhsic_phy_bus_port_power(phy);
+
+ return 0;
+}
+
+
+static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ val = readl(base + USB_TXFILLTUNING);
+ if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
+ val = USB_FIFO_TXFILL_THRES(0x10);
+ writel(val, base + USB_TXFILLTUNING);
+ }
+
+ return 0;
+}
+
+static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
+{
+ struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
+ void __iomem *base = phy->regs;
+ unsigned long val;
+
+ val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
+ val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
+ val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
+ writel(val, base + ULPI_TIMING_CTRL_1);
+ udelay(10);
+
+ val |= ULPI_DATA_TRIMMER_LOAD;
+ val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
+ val |= ULPI_DIR_TRIMMER_LOAD;
+ writel(val, base + ULPI_TIMING_CTRL_1);
+}
+
+
+static int ulpi_link_phy_open(struct tegra_usb_phy *phy)
+{
+ struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
+ int err = 0;
+
+ phy->ulpi_clk = NULL;
+
+ if (config->clk) {
+ phy->ulpi_clk = clk_get_sys(NULL, config->clk);
+ if (IS_ERR(phy->ulpi_clk)) {
+ pr_err("%s: can't get ulpi clock\n", __func__);
+ err = -ENXIO;
+ }
+ }
+
+ phy->ulpi_vp = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
+ phy->ulpi_vp->io_priv = phy->regs + ULPI_VIEWPORT;
+
+ return err;
+}
+
+static void ulpi_link_phy_close(struct tegra_usb_phy *phy)
+{
+ DBG("%s inst:[%d]\n", __func__, phy->inst);
+ if (phy->ulpi_clk)
+ clk_put(phy->ulpi_clk);
+}
+
+static int ulpi_link_phy_irq(struct tegra_usb_phy *phy)
+{
+ usb_phy_fence_read(phy);
+ return IRQ_HANDLED;
+}
+
+static int ulpi_link_phy_power_off(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+ int ret;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ if (!phy->phy_clk_on) {
+ DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
+ __LINE__, phy->inst);
+ return 0;
+ }
+
+ /* Disable VbusValid, SessEnd comparators */
+ ret = otg_io_write(phy->ulpi_vp, 0x00, 0x0D);
+ if (ret)
+ pr_err("%s: ulpi write 0x0D failed\n", __func__);
+
+ ret = otg_io_write(phy->ulpi_vp, 0x00, 0x10);
+ if (ret)
+ pr_err("%s: ulpi write 0x10 failed\n", __func__);
+
+ /* Disable IdFloat comparator */
+ ret = otg_io_write(phy->ulpi_vp, 0x00, 0x19);
+ if (ret)
+ pr_err("%s: ulpi write 0x19 failed\n", __func__);
+
+ ret = otg_io_write(phy->ulpi_vp, 0x00, 0x1D);
+ if (ret)
+ pr_err("%s: ulpi write 0x1D failed\n", __func__);
+
+ phy->port_speed = (readl(base + USB_PORTSC) >> 26) &
+ USB_PORTSC_PSPD_MASK;
+
+ /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
+ * Controller to immediately bring the ULPI PHY out of low power
+ */
+ val = readl(base + USB_PORTSC);
+ val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
+ writel(val, base + USB_PORTSC);
+
+ /* Put the PHY in the low power mode */
+ val = readl(base + USB_PORTSC);
+ val |= USB_PORTSC_PHCD;
+ writel(val, base + USB_PORTSC);
+
+ if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
+ 0, 2500)) {
+ pr_err("%s: timeout waiting for phy to stop\n", __func__);
+ }
+
+ if (phy->ulpi_clk)
+ clk_disable(phy->ulpi_clk);
+
+ phy->phy_clk_on = false;
+ phy->hw_accessible = false;
+
+ return 0;
+}
+
+static int ulpi_link_phy_power_on(struct tegra_usb_phy *phy)
+{
+ int ret;
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ if (phy->phy_clk_on) {
+ DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
+ __LINE__, phy->inst);
+ return 0;
+ }
+
+ if (phy->ulpi_clk) {
+ clk_enable(phy->ulpi_clk);
+ mdelay(1);
+ }
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= UHSIC_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+
+ val = readl(base + ULPI_TIMING_CTRL_0);
+ val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
+ writel(val, base + ULPI_TIMING_CTRL_0);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= ULPI_PHY_ENABLE;
+ writel(val, base + USB_SUSP_CTRL);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= USB_SUSP_CLR;
+ writel(val, base + USB_SUSP_CTRL);
+
+ if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
+ USB_PHY_CLK_VALID, 2500))
+ pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
+
+ if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_CLKEN,
+ USB_CLKEN, 2500))
+ pr_err("%s: timeout waiting for AHB clock\n", __func__);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~USB_SUSP_CLR;
+ writel(val, base + USB_SUSP_CTRL);
+
+ val = 0;
+ writel(val, base + ULPI_TIMING_CTRL_1);
+
+ ulpi_set_trimmer(phy);
+
+ /* Fix VbusInvalid due to floating VBUS */
+ ret = otg_io_write(phy->ulpi_vp, 0x40, 0x08);
+ if (ret) {
+ pr_err("%s: ulpi write failed\n", __func__);
+ return ret;
+ }
+
+ ret = otg_io_write(phy->ulpi_vp, 0x80, 0x0B);
+ if (ret) {
+ pr_err("%s: ulpi write failed\n", __func__);
+ return ret;
+ }
+
+ val = readl(base + USB_PORTSC);
+ val |= USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN;
+ writel(val, base + USB_PORTSC);
+
+ phy->phy_clk_on = true;
+ phy->hw_accessible = true;
+
+ return 0;
+}
+
+static inline void ulpi_link_phy_set_tristate(bool enable)
+{
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+ int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
+
+ tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate);
+ tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate);
+ tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate);
+#endif
+}
+
+static void ulpi_link_phy_restore_start(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ /*Tristate ulpi interface before USB controller resume*/
+ ulpi_link_phy_set_tristate(true);
+
+ val = readl(base + ULPI_TIMING_CTRL_0);
+ val &= ~ULPI_OUTPUT_PINMUX_BYP;
+ writel(val, base + ULPI_TIMING_CTRL_0);
+}
+
+static void ulpi_link_phy_restore_end(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ val = readl(base + ULPI_TIMING_CTRL_0);
+ val |= ULPI_OUTPUT_PINMUX_BYP;
+ writel(val, base + ULPI_TIMING_CTRL_0);
+
+ ulpi_link_phy_set_tristate(false);
+}
+
+static int ulpi_link_phy_resume(struct tegra_usb_phy *phy)
+{
+ int status = 0;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ if (phy->pdata->u_data.host.power_off_on_suspend) {
+ status = ulpi_link_phy_power_on(phy);
+ if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
+ ulpi_link_phy_restore_start(phy);
+ usb_phy_bringup_host_controller(phy);
+ ulpi_link_phy_restore_end(phy);
+ }
+ }
+
+ return status;
+}
+
+static struct tegra_usb_phy_ops utmi_phy_ops = {
+ .open = utmi_phy_open,
+ .close = utmi_phy_close,
+ .irq = utmi_phy_irq,
+ .power_on = utmi_phy_power_on,
+ .power_off = utmi_phy_power_off,
+ .pre_resume = utmi_phy_pre_resume,
+ .resume = utmi_phy_resume,
+ .post_resume = utmi_phy_post_resume,
+ .charger_detect = utmi_phy_charger_detect,
+};
+
+static struct tegra_usb_phy_ops uhsic_phy_ops = {
+ .open = uhsic_phy_open,
+ .irq = uhsic_phy_irq,
+ .power_on = uhsic_phy_power_on,
+ .power_off = uhsic_phy_power_off,
+ .pre_resume = uhsic_phy_pre_resume,
+ .resume = uhsic_phy_resume,
+ .post_resume = uhsic_phy_post_resume,
+ .port_power = uhsic_phy_bus_port_power,
+ .bus_reset = uhsic_phy_bus_reset,
+};
+
+static struct tegra_usb_phy_ops ulpi_link_phy_ops = {
+ .open = ulpi_link_phy_open,
+ .close = ulpi_link_phy_close,
+ .irq = ulpi_link_phy_irq,
+ .power_on = ulpi_link_phy_power_on,
+ .power_off = ulpi_link_phy_power_off,
+ .resume = ulpi_link_phy_resume,
+};
+
+static struct tegra_usb_phy_ops ulpi_null_phy_ops;
+static struct tegra_usb_phy_ops icusb_phy_ops;
+
+
+static struct tegra_usb_phy_ops *phy_ops[] = {
+ [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
+ [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
+ [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
+ [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
+ [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
+};
+
+int tegra2_usb_phy_init_ops(struct tegra_usb_phy *phy)
+{
+ phy->ops = phy_ops[phy->pdata->phy_intf];
+
+ return 0;
+}
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c
index 2dfdb1d..9ff1833 100644
--- a/arch/arm/mach-tegra/tegra3_clocks.c
+++ b/arch/arm/mach-tegra/tegra3_clocks.c
@@ -284,7 +284,7 @@
#define PLLE_SS_COEFFICIENTS_12MHZ \
((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
(0x24<<PLLE_SS_MAX_SHIFT))
-#define PLLE_SS_DISABLE ((1<<12) | (1<<11) | (1<<10))
+#define PLLE_SS_DISABLE ((1<<14) | (1<<12) | (1<<11) | (1<<10))
#define PLLE_AUX 0x48c
#define PLLE_AUX_PLLP_SEL (1<<2)
@@ -3906,7 +3906,7 @@ static struct clk tegra_clk_sclk = {
.reg = 0x28,
.ops = &tegra_super_ops,
.max_rate = 378000000,
- .min_rate = 40000000,
+ .min_rate = 12000000,
};
static struct clk tegra_clk_virtual_cpu_g = {
@@ -3961,7 +3961,7 @@ static struct clk tegra_clk_hclk = {
.reg_shift = 4,
.ops = &tegra_bus_ops,
.max_rate = 378000000,
- .min_rate = 40000000,
+ .min_rate = 12000000,
};
static struct clk tegra_clk_pclk = {
@@ -3972,7 +3972,7 @@ static struct clk tegra_clk_pclk = {
.reg_shift = 0,
.ops = &tegra_bus_ops,
.max_rate = 167000000,
- .min_rate = 40000000,
+ .min_rate = 12000000,
};
static struct raw_notifier_head sbus_rate_change_nh;
diff --git a/arch/arm/mach-tegra/tegra3_usb_phy.c b/arch/arm/mach-tegra/tegra3_usb_phy.c
new file mode 100644
index 00000000..5b3e519
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra3_usb_phy.c
@@ -0,0 +1,2409 @@
+/*
+ * arch/arm/mach-tegra/tegra3_usb_phy.c
+ *
+ * Copyright (C) 2011 NVIDIA Corporation
+ *
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/resource.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+#include <linux/platform_data/tegra_usb.h>
+#include <mach/iomap.h>
+#include <mach/pinmux.h>
+#include "tegra_usb_phy.h"
+#include "fuse.h"
+
+#define USB_USBCMD 0x130
+#define USB_USBCMD_RS (1 << 0)
+#define USB_CMD_RESET (1<<1)
+
+#define USB_USBSTS 0x134
+#define USB_USBSTS_PCI (1 << 2)
+#define USB_USBSTS_SRI (1 << 7)
+#define USB_USBSTS_HCH (1 << 12)
+
+#define USB_USBINTR 0x138
+
+#define USB_TXFILLTUNING 0x154
+#define USB_FIFO_TXFILL_THRES(x) (((x) & 0x1f) << 16)
+#define USB_FIFO_TXFILL_MASK 0x1f0000
+
+#define USB_ASYNCLISTADDR 0x148
+
+#define ICUSB_CTRL 0x15c
+
+#define USB_PORTSC 0x174
+#define USB_PORTSC_WKOC (1 << 22)
+#define USB_PORTSC_WKDS (1 << 21)
+#define USB_PORTSC_WKCN (1 << 20)
+#define USB_PORTSC_PTC(x) (((x) & 0xf) << 16)
+#define USB_PORTSC_PP (1 << 12)
+#define USB_PORTSC_LS(x) (((x) & 0x3) << 10)
+#define USB_PORTSC_SUSP (1 << 7)
+#define USB_PORTSC_RESUME (1 << 6)
+#define USB_PORTSC_OCC (1 << 5)
+#define USB_PORTSC_PEC (1 << 3)
+#define USB_PORTSC_PE (1 << 2)
+#define USB_PORTSC_CSC (1 << 1)
+#define USB_PORTSC_CCS (1 << 0)
+#define USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
+
+#define HOSTPC1_DEVLC 0x1b4
+#define HOSTPC1_DEVLC_PHCD (1 << 22)
+#define HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29)
+#define HOSTPC1_DEVLC_PTS_MASK 7
+#define HOSTPC1_DEVLC_PTS_HSIC 4
+#define HOSTPC1_DEVLC_STS (1 << 28)
+#define HOSTPC1_DEVLC_PSPD(x) (((x) & 0x3) << 25)
+#define HOSTPC1_DEVLC_PSPD_MASK 3
+#define HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
+
+#define USB_USBMODE 0x1f8
+#define USB_USBMODE_MASK (3 << 0)
+#define USB_USBMODE_HOST (3 << 0)
+#define USB_USBMODE_DEVICE (2 << 0)
+
+#define USB_SUSP_CTRL 0x400
+#define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
+#define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
+#define USB_SUSP_CLR (1 << 5)
+#define USB_PHY_CLK_VALID (1 << 7)
+#define USB_PHY_CLK_VALID_INT_ENB (1 << 9)
+#define USB_PHY_CLK_VALID_INT_STS (1 << 8)
+#define UTMIP_RESET (1 << 11)
+#define UTMIP_PHY_ENABLE (1 << 12)
+#define ULPI_PHY_ENABLE (1 << 13)
+#define UHSIC_RESET (1 << 14)
+#define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
+#define UHSIC_PHY_ENABLE (1 << 19)
+#define ULPIS2S_SLV0_RESET (1 << 20)
+#define ULPIS2S_SLV1_RESET (1 << 21)
+#define ULPIS2S_LINE_RESET (1 << 22)
+#define ULPI_PADS_RESET (1 << 23)
+#define ULPI_PADS_CLKEN_RESET (1 << 24)
+
+#define USB_PHY_VBUS_WAKEUP_ID 0x408
+#define VDAT_DET_INT_EN (1 << 16)
+#define VDAT_DET_CHG_DET (1 << 17)
+#define VDAT_DET_STS (1 << 18)
+#define USB_ID_STATUS (1 << 2)
+
+#define ULPIS2S_CTRL 0x418
+#define ULPIS2S_ENA (1 << 0)
+#define ULPIS2S_SUPPORT_DISCONNECT (1 << 2)
+#define ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
+#define ULPIS2S_SPARE(x) (((x) & 0xF) << 8)
+#define ULPIS2S_FORCE_ULPI_CLK_OUT (1 << 12)
+#define ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
+#define ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
+#define ULPIS2S_DISABLE_STP_PU (1 << 15)
+#define ULPIS2S_SLV0_CLAMP_XMIT (1 << 16)
+
+#define ULPI_TIMING_CTRL_0 0x424
+#define ULPI_CLOCK_OUT_DELAY(x) ((x) & 0x1F)
+#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
+#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
+#define ULPI_SHADOW_CLK_LOOPBACK_EN (1 << 12)
+#define ULPI_SHADOW_CLK_SEL (1 << 13)
+#define ULPI_CORE_CLK_SEL (1 << 14)
+#define ULPI_SHADOW_CLK_DELAY(x) (((x) & 0x1F) << 16)
+#define ULPI_LBK_PAD_EN (1 << 26)
+#define ULPI_LBK_PAD_E_INPUT_OR (1 << 27)
+#define ULPI_CLK_OUT_ENA (1 << 28)
+#define ULPI_CLK_PADOUT_ENA (1 << 29)
+
+#define ULPI_TIMING_CTRL_1 0x428
+#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
+#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
+#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
+#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
+#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
+#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
+
+#define UTMIP_XCVR_CFG0 0x808
+#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
+#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
+#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
+#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
+#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
+#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
+#define UTMIP_XCVR_LSBIAS_SEL (1 << 21)
+#define UTMIP_XCVR_SETUP_MSB(x) (((x) & 0x7) << 22)
+#define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25)
+#define UTMIP_XCVR_MAX_OFFSET 2
+#define UTMIP_XCVR_SETUP_MAX_VALUE 0x7f
+#define UTMIP_XCVR_SETUP_MIN_VALUE 0
+#define XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
+
+#define UTMIP_BIAS_CFG0 0x80c
+#define UTMIP_OTGPD (1 << 11)
+#define UTMIP_BIASPD (1 << 10)
+#define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0)
+#define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2)
+#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24)
+
+#define UTMIP_HSRX_CFG0 0x810
+#define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
+#define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
+
+#define UTMIP_HSRX_CFG1 0x814
+#define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
+
+#define UTMIP_TX_CFG0 0x820
+#define UTMIP_FS_PREABMLE_J (1 << 19)
+#define UTMIP_HS_DISCON_DISABLE (1 << 8)
+
+#define UTMIP_DEBOUNCE_CFG0 0x82c
+#define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
+
+#define UTMIP_BAT_CHRG_CFG0 0x830
+#define UTMIP_PD_CHRG (1 << 0)
+#define UTMIP_ON_SINK_EN (1 << 2)
+#define UTMIP_OP_SRC_EN (1 << 3)
+
+#define UTMIP_XCVR_CFG1 0x838
+#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
+#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
+#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
+#define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
+
+#define UTMIP_BIAS_CFG1 0x83c
+#define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
+#define UTMIP_BIAS_PDTRK_POWERDOWN (1 << 0)
+#define UTMIP_BIAS_PDTRK_POWERUP (1 << 1)
+
+#define UTMIP_MISC_CFG0 0x824
+#define UTMIP_DPDM_OBSERVE (1 << 26)
+#define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
+#define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
+#define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
+#define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
+#define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
+#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
+#define FORCE_PULLDN_DM (1 << 8)
+#define FORCE_PULLDN_DP (1 << 9)
+#define COMB_TERMS (1 << 0)
+#define ALWAYS_FREE_RUNNING_TERMS (1 << 1)
+
+#define UTMIP_SPARE_CFG0 0x834
+#define FUSE_SETUP_SEL (1 << 3)
+#define FUSE_ATERM_SEL (1 << 4)
+
+#define UTMIP_PMC_WAKEUP0 0x84c
+#define EVENT_INT_ENB (1 << 0)
+
+#define UTMIP_BIAS_STS0 0x840
+#define UTMIP_RCTRL_VAL(x) (((x) & 0xffff) << 0)
+#define UTMIP_TCTRL_VAL(x) (((x) & (0xffff << 16)) >> 16)
+
+#define UHSIC_PLL_CFG1 0xc04
+#define UHSIC_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
+#define UHSIC_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 14)
+
+#define UHSIC_HSRX_CFG0 0xc08
+#define UHSIC_ELASTIC_UNDERRUN_LIMIT(x) (((x) & 0x1f) << 2)
+#define UHSIC_ELASTIC_OVERRUN_LIMIT(x) (((x) & 0x1f) << 8)
+#define UHSIC_IDLE_WAIT(x) (((x) & 0x1f) << 13)
+
+#define UHSIC_HSRX_CFG1 0xc0c
+#define UHSIC_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
+
+#define UHSIC_TX_CFG0 0xc10
+#define UHSIC_HS_READY_WAIT_FOR_VALID (1 << 9)
+#define UHSIC_MISC_CFG0 0xc14
+#define UHSIC_SUSPEND_EXIT_ON_EDGE (1 << 7)
+#define UHSIC_DETECT_SHORT_CONNECT (1 << 8)
+#define UHSIC_FORCE_XCVR_MODE (1 << 15)
+#define UHSIC_DISABLE_BUSRESET (1 << 20)
+#define UHSIC_MISC_CFG1 0xc18
+#define UHSIC_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 2)
+
+#define UHSIC_PADS_CFG0 0xc1c
+#define UHSIC_TX_RTUNEN 0xf000
+#define UHSIC_TX_RTUNE(x) (((x) & 0xf) << 12)
+
+#define UHSIC_PADS_CFG1 0xc20
+#define UHSIC_PD_BG (1 << 2)
+#define UHSIC_PD_TX (1 << 3)
+#define UHSIC_PD_TRK (1 << 4)
+#define UHSIC_PD_RX (1 << 5)
+#define UHSIC_PD_ZI (1 << 6)
+#define UHSIC_RX_SEL (1 << 7)
+#define UHSIC_RPD_DATA (1 << 9)
+#define UHSIC_RPD_STROBE (1 << 10)
+#define UHSIC_RPU_DATA (1 << 11)
+#define UHSIC_RPU_STROBE (1 << 12)
+
+#define UHSIC_STAT_CFG0 0xc28
+#define UHSIC_CONNECT_DETECT (1 << 0)
+
+#define PMC_USB_DEBOUNCE 0xec
+#define UTMIP_LINE_DEB_CNT(x) (((x) & 0xf) << 16)
+
+#define PMC_USB_AO 0xf0
+#define PMC_POWER_DOWN_MASK 0xffff
+#define HSIC_RESERVED_P0 (3 << 14)
+#define HSIC_STOBE_VAL_PD_P0 (1 << 13)
+#define HSIC_DATA_VAL_PD_P0 (1 << 12)
+#define USB_ID_PD(inst) (1 << ((4*(inst))+3))
+#define VBUS_WAKEUP_PD(inst) (1 << ((4*(inst))+2))
+#define USBON_VAL_PD(inst) (1 << ((4*(inst))+1))
+#define USBON_VAL_PD_P2 (1 << 9)
+#define USBON_VAL_PD_P1 (1 << 5)
+#define USBON_VAL_PD_P0 (1 << 1)
+#define USBOP_VAL_PD(inst) (1 << (4*(inst)))
+#define USBOP_VAL_PD_P2 (1 << 8)
+#define USBOP_VAL_PD_P1 (1 << 4)
+#define USBOP_VAL_PD_P0 (1 << 0)
+#define PMC_USB_AO_PD_P2 (0xf << 8)
+#define PMC_USB_AO_ID_PD_P0 (1 << 3)
+#define PMC_USB_AO_VBUS_WAKEUP_PD_P0 (1 << 2)
+
+#define PMC_TRIGGERS 0x1ec
+#define UTMIP_CLR_WALK_PTR(inst) (1 << (inst))
+#define UTMIP_CLR_WALK_PTR_P2 (1 << 2)
+#define UTMIP_CLR_WALK_PTR_P1 (1 << 1)
+#define UTMIP_CLR_WALK_PTR_P0 (1 << 0)
+#define UTMIP_CAP_CFG(inst) (1 << ((inst)+4))
+#define UTMIP_CAP_CFG_P2 (1 << 6)
+#define UTMIP_CAP_CFG_P1 (1 << 5)
+#define UTMIP_CAP_CFG_P0 (1 << 4)
+#define UTMIP_CLR_WAKE_ALARM(inst) (1 << ((inst)+12))
+#define UTMIP_CLR_WAKE_ALARM_P2 (1 << 14)
+
+#define PMC_PAD_CFG (0x1f4)
+
+#define PMC_UTMIP_TERM_PAD_CFG 0x1f8
+#define PMC_TCTRL_VAL(x) (((x) & 0x1f) << 5)
+#define PMC_RCTRL_VAL(x) (((x) & 0x1f) << 0)
+
+#define UHSIC_SLEEPWALK_REG 0x210
+#define UHSIC_DATA_RPD_D (1 << 25)
+#define UHSIC_STRB_RPD_D (1 << 24)
+#define UHSIC_DATA_RPD_C (1 << 17)
+#define UHSIC_STRB_RPD_C (1 << 16)
+#define UHSIC_DATA_RPD_B (1 << 9)
+#define UHSIC_STRB_RPD_B (1 << 8)
+#define UHSIC_DATA_RPD_A (1 << 1)
+#define UHSIC_STRB_RPD_A (1 << 0)
+
+#define PMC_SLEEP_CFG 0x1fc
+#define UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
+#define UTMIP_TCTRL_USE_PMC_P2 (1 << 19)
+#define UTMIP_TCTRL_USE_PMC_P1 (1 << 11)
+#define UTMIP_TCTRL_USE_PMC_P0 (1 << 3)
+#define UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
+#define UTMIP_RCTRL_USE_PMC_P2 (1 << 18)
+#define UTMIP_RCTRL_USE_PMC_P1 (1 << 10)
+#define UTMIP_RCTRL_USE_PMC_P0 (1 << 2)
+#define UTMIP_FSLS_USE_PMC(inst) (1 << ((8*(inst))+1))
+#define UTMIP_FSLS_USE_PMC_P2 (1 << 17)
+#define UTMIP_FSLS_USE_PMC_P1 (1 << 9)
+#define UTMIP_FSLS_USE_PMC_P0 (1 << 1)
+#define UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
+#define UTMIP_MASTER_ENABLE_P2 (1 << 16)
+#define UTMIP_MASTER_ENABLE_P1 (1 << 8)
+#define UTMIP_MASTER_ENABLE_P0 (1 << 0)
+#define UHSIC_MASTER_ENABLE_P0 (1 << 24)
+#define UHSIC_WAKE_VAL_P0(x) (((x) & 0xf) << 28)
+
+#define PMC_SLEEPWALK_CFG 0x200
+#define UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
+#define UTMIP_LINEVAL_WALK_EN_P2 (1 << 23)
+#define UTMIP_LINEVAL_WALK_EN_P1 (1 << 15)
+#define UTMIP_LINEVAL_WALK_EN_P0 (1 << 7)
+#define UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
+#define UTMIP_WAKE_VAL_P2(x) (((x) & 0xf) << 20)
+#define UTMIP_WAKE_VAL_P1(x) (((x) & 0xf) << 12)
+#define UTMIP_WAKE_VAL_P0(x) (((x) & 0xf) << 4)
+#define WAKE_VAL_NONE 0xc
+#define WAKE_VAL_ANY 0xF
+#define WAKE_VAL_FSJ 0x2
+#define WAKE_VAL_FSK 0x1
+#define WAKE_VAL_SE0 0x0
+
+#define PMC_SLEEPWALK_REG(inst) (0x204 + (4*(inst)))
+#define UTMIP_USBOP_RPD_A (1 << 0)
+#define UTMIP_USBON_RPD_A (1 << 1)
+#define UTMIP_AP_A (1 << 4)
+#define UTMIP_AN_A (1 << 5)
+#define UTMIP_HIGHZ_A (1 << 6)
+#define UTMIP_USBOP_RPD_B (1 << 8)
+#define UTMIP_USBON_RPD_B (1 << 9)
+#define UTMIP_AP_B (1 << 12)
+#define UTMIP_AN_B (1 << 13)
+#define UTMIP_HIGHZ_B (1 << 14)
+#define UTMIP_USBOP_RPD_C (1 << 16)
+#define UTMIP_USBON_RPD_C (1 << 17)
+#define UTMIP_AP_C (1 << 20)
+#define UTMIP_AN_C (1 << 21)
+#define UTMIP_HIGHZ_C (1 << 22)
+#define UTMIP_USBOP_RPD_D (1 << 24)
+#define UTMIP_USBON_RPD_D (1 << 25)
+#define UTMIP_AP_D (1 << 28)
+#define UTMIP_AN_D (1 << 29)
+#define UTMIP_HIGHZ_D (1 << 30)
+
+#define UTMIP_UHSIC_STATUS 0x214
+#define UTMIP_WALK_PTR_VAL(inst) (0x3 << ((inst)*2))
+#define UTMIP_USBOP_VAL(inst) (1 << ((2*(inst)) + 8))
+#define UTMIP_USBOP_VAL_P2 (1 << 12)
+#define UTMIP_USBOP_VAL_P1 (1 << 10)
+#define UTMIP_USBOP_VAL_P0 (1 << 8)
+#define UTMIP_USBON_VAL(inst) (1 << ((2*(inst)) + 9))
+#define UTMIP_USBON_VAL_P2 (1 << 13)
+#define UTMIP_USBON_VAL_P1 (1 << 11)
+#define UTMIP_USBON_VAL_P0 (1 << 9)
+#define UTMIP_WAKE_ALARM(inst) (1 << ((inst) + 16))
+#define UTMIP_WAKE_ALARM_P2 (1 << 18)
+#define UTMIP_WAKE_ALARM_P1 (1 << 17)
+#define UTMIP_WAKE_ALARM_P0 (1 << 16)
+#define UTMIP_WALK_PTR(inst) (1 << ((inst)*2))
+#define UTMIP_WALK_PTR_P2 (1 << 4)
+#define UTMIP_WALK_PTR_P1 (1 << 2)
+#define UTMIP_WALK_PTR_P0 (1 << 0)
+
+#define USB1_PREFETCH_ID 6
+#define USB2_PREFETCH_ID 18
+#define USB3_PREFETCH_ID 17
+
+#define PMC_UTMIP_UHSIC_FAKE 0x218
+#define USBON_VAL(inst) (1 << ((4*(inst))+1))
+#define USBON_VAL_P2 (1 << 9)
+#define USBON_VAL_P1 (1 << 5)
+#define USBON_VAL_P0 (1 << 1)
+#define USBOP_VAL(inst) (1 << (4*(inst)))
+#define USBOP_VAL_P2 (1 << 8)
+#define USBOP_VAL_P1 (1 << 4)
+#define USBOP_VAL_P0 (1 << 0)
+
+#define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
+#define BIAS_MASTER_PROG_VAL (1 << 1)
+
+#define PMC_UTMIP_MASTER_CONFIG 0x310
+#define UTMIP_PWR(inst) (1 << (inst))
+
+#define FUSE_USB_CALIB_0 0x1F0
+#define FUSE_USB_CALIB_XCVR_SETUP(x) (((x) & 0x7F) << 0)
+
+/* These values (in milli second) are taken from the battery charging spec */
+#define TDP_SRC_ON_MS 100
+#define TDPSRC_CON_MS 40
+
+#ifdef DEBUG
+#define DBG(stuff...) pr_info("tegra3_usb_phy: " stuff)
+#else
+#define DBG(stuff...) do {} while (0)
+#endif
+
+#if 0
+#define PHY_DBG(stuff...) pr_info("tegra3_usb_phy: " stuff)
+#else
+#define PHY_DBG(stuff...) do {} while (0)
+#endif
+
+static u32 utmip_rctrl_val, utmip_tctrl_val;
+static DEFINE_SPINLOCK(utmip_pad_lock);
+static int utmip_pad_count;
+
+static struct tegra_xtal_freq utmip_freq_table[] = {
+ {
+ .freq = 12000000,
+ .enable_delay = 0x02,
+ .stable_count = 0x2F,
+ .active_delay = 0x04,
+ .xtal_freq_count = 0x76,
+ .debounce = 0x7530,
+ .pdtrk_count = 5,
+ },
+ {
+ .freq = 13000000,
+ .enable_delay = 0x02,
+ .stable_count = 0x33,
+ .active_delay = 0x05,
+ .xtal_freq_count = 0x7F,
+ .debounce = 0x7EF4,
+ .pdtrk_count = 5,
+ },
+ {
+ .freq = 19200000,
+ .enable_delay = 0x03,
+ .stable_count = 0x4B,
+ .active_delay = 0x06,
+ .xtal_freq_count = 0xBB,
+ .debounce = 0xBB80,
+ .pdtrk_count = 7,
+ },
+ {
+ .freq = 26000000,
+ .enable_delay = 0x04,
+ .stable_count = 0x66,
+ .active_delay = 0x09,
+ .xtal_freq_count = 0xFE,
+ .debounce = 0xFDE8,
+ .pdtrk_count = 9,
+ },
+};
+
+static struct tegra_xtal_freq uhsic_freq_table[] = {
+ {
+ .freq = 12000000,
+ .enable_delay = 0x02,
+ .stable_count = 0x2F,
+ .active_delay = 0x0,
+ .xtal_freq_count = 0x1CA,
+ },
+ {
+ .freq = 13000000,
+ .enable_delay = 0x02,
+ .stable_count = 0x33,
+ .active_delay = 0x0,
+ .xtal_freq_count = 0x1F0,
+ },
+ {
+ .freq = 19200000,
+ .enable_delay = 0x03,
+ .stable_count = 0x4B,
+ .active_delay = 0x0,
+ .xtal_freq_count = 0x2DD,
+ },
+ {
+ .freq = 26000000,
+ .enable_delay = 0x04,
+ .stable_count = 0x66,
+ .active_delay = 0x0,
+ .xtal_freq_count = 0x3E0,
+ },
+};
+
+static void usb_phy_fence_read(struct tegra_usb_phy *phy)
+{
+ /* Fence read for coherency of AHB master intiated writes */
+ if (phy->inst == 0)
+ readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
+ else if (phy->inst == 1)
+ readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
+ else if (phy->inst == 2)
+ readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
+
+ return;
+}
+
+static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
+{
+ unsigned long val, pmc_pad_cfg_val;
+ void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+ unsigned int inst = phy->inst;
+ void __iomem *base = phy->regs;
+ bool port_connected;
+ enum usb_phy_port_speed port_speed;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ /* check for port connect status */
+ val = readl(base + USB_PORTSC);
+ port_connected = val & USB_PORTSC_CCS;
+
+ if (!port_connected)
+ return;
+
+ port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
+ HOSTPC1_DEVLC_PSPD_MASK;
+ /*Set PMC MASTER bits to do the following
+ * a. Take over the UTMI drivers
+ * b. set up such that it will take over resume
+ * if remote wakeup is detected
+ * Prepare PMC to take over suspend-wake detect-drive resume until USB
+ * controller ready
+ */
+
+ /* disable master enable in PMC */
+ val = readl(pmc_base + PMC_SLEEP_CFG);
+ val &= ~UTMIP_MASTER_ENABLE(inst);
+ writel(val, pmc_base + PMC_SLEEP_CFG);
+
+ /* UTMIP_PWR_PX=1 for power savings mode */
+ val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
+ val |= UTMIP_PWR(inst);
+ writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
+
+ /* config debouncer */
+ val = readl(pmc_base + PMC_USB_DEBOUNCE);
+ val &= ~UTMIP_LINE_DEB_CNT(~0);
+ val |= UTMIP_LINE_DEB_CNT(4);
+ writel(val, pmc_base + PMC_USB_DEBOUNCE);
+
+ /* Make sure nothing is happening on the line with respect to PMC */
+ val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
+ val &= ~USBOP_VAL(inst);
+ val &= ~USBON_VAL(inst);
+ writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
+
+ /* Make sure wake value for line is none */
+ val = readl(pmc_base + PMC_SLEEPWALK_CFG);
+ val &= ~UTMIP_LINEVAL_WALK_EN(inst);
+ writel(val, pmc_base + PMC_SLEEPWALK_CFG);
+ val = readl(pmc_base + PMC_SLEEP_CFG);
+ val &= ~UTMIP_WAKE_VAL(inst, ~0);
+ val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
+ writel(val, pmc_base + PMC_SLEEP_CFG);
+
+ /* turn off pad detectors */
+ val = readl(pmc_base + PMC_USB_AO);
+ val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
+ writel(val, pmc_base + PMC_USB_AO);
+
+ /* Remove fake values and make synchronizers work a bit */
+ val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
+ val &= ~USBOP_VAL(inst);
+ val &= ~USBON_VAL(inst);
+ writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
+
+ /* Enable which type of event can trigger a walk,
+ in this case usb_line_wake */
+ val = readl(pmc_base + PMC_SLEEPWALK_CFG);
+ val |= UTMIP_LINEVAL_WALK_EN(inst);
+ writel(val, pmc_base + PMC_SLEEPWALK_CFG);
+
+ /* Enable which type of event can trigger a walk,
+ * in this case usb_line_wake */
+ val = readl(pmc_base + PMC_SLEEPWALK_CFG);
+ val |= UTMIP_LINEVAL_WALK_EN(inst);
+ writel(val, pmc_base + PMC_SLEEPWALK_CFG);
+
+ /* Clear the walk pointers and wake alarm */
+ val = readl(pmc_base + PMC_TRIGGERS);
+ val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
+ writel(val, pmc_base + PMC_TRIGGERS);
+
+
+ /* Capture FS/LS pad configurations */
+ pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
+ val = readl(pmc_base + PMC_TRIGGERS);
+ val |= UTMIP_CAP_CFG(inst);
+ writel(val, pmc_base + PMC_TRIGGERS);
+ udelay(1);
+ pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
+
+ /* BIAS MASTER_ENABLE=0 */
+ val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
+ val &= ~BIAS_MASTER_PROG_VAL;
+ writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
+
+ /* program walk sequence, maintain a J, followed by a driven K
+ * to signal a resume once an wake event is detected */
+ val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
+ val &= ~UTMIP_AP_A;
+ val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
+ UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
+ UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
+ UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
+ writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
+
+ if (port_speed == USB_PHY_PORT_SPEED_LOW) {
+ val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
+ val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
+ UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
+ writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
+ } else {
+ val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
+ val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
+ UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
+ writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
+ }
+
+ /* turn on pad detectors */
+ val = readl(pmc_base + PMC_USB_AO);
+ val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
+ writel(val, pmc_base + PMC_USB_AO);
+
+ /* Add small delay before usb detectors provide stable line values */
+ mdelay(1);
+
+ /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
+ val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
+ val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
+ writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
+
+ phy->remote_wakeup = false;
+
+ /* Turn over pad configuration to PMC for line wake events*/
+ val = readl(pmc_base + PMC_SLEEP_CFG);
+ val &= ~UTMIP_WAKE_VAL(inst, ~0);
+ val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
+ val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
+ val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
+ writel(val, pmc_base + PMC_SLEEP_CFG);
+
+ val = readl(base + UTMIP_PMC_WAKEUP0);
+ val |= EVENT_INT_ENB;
+ writel(val, base + UTMIP_PMC_WAKEUP0);
+ PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
+}
+
+static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+ unsigned int inst = phy->inst;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ val = readl(pmc_base + PMC_SLEEP_CFG);
+ val &= ~UTMIP_WAKE_VAL(inst, 0xF);
+ val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
+ writel(val, pmc_base + PMC_SLEEP_CFG);
+
+ val = readl(pmc_base + PMC_TRIGGERS);
+ val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
+ writel(val, pmc_base + PMC_TRIGGERS);
+
+ val = readl(base + UTMIP_PMC_WAKEUP0);
+ val &= ~EVENT_INT_ENB;
+ writel(val, base + UTMIP_PMC_WAKEUP0);
+
+ /* Disable PMC master mode by clearing MASTER_EN */
+ val = readl(pmc_base + PMC_SLEEP_CFG);
+ val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
+ UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
+ writel(val, pmc_base + PMC_SLEEP_CFG);
+
+ val = readl(pmc_base + PMC_TRIGGERS);
+ val &= ~UTMIP_CAP_CFG(inst);
+ writel(val, pmc_base + PMC_TRIGGERS);
+
+ /* turn off pad detectors */
+ val = readl(pmc_base + PMC_USB_AO);
+ val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
+ writel(val, pmc_base + PMC_USB_AO);
+
+ phy->remote_wakeup = false;
+ PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
+}
+
+bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
+{
+ void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+ void __iomem *base = phy->regs;
+ unsigned int inst = phy->inst;
+ u32 val;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ val = readl(base + UTMIP_PMC_WAKEUP0);
+ if (val & EVENT_INT_ENB) {
+ val = readl(pmc_base + UTMIP_UHSIC_STATUS);
+ if (UTMIP_WAKE_ALARM(inst) & val) {
+ val = readl(pmc_base + PMC_SLEEP_CFG);
+ val &= ~UTMIP_WAKE_VAL(inst, 0xF);
+ val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
+ writel(val, pmc_base + PMC_SLEEP_CFG);
+
+ val = readl(pmc_base + PMC_TRIGGERS);
+ val |= UTMIP_CLR_WAKE_ALARM(inst) |
+ UTMIP_CLR_WALK_PTR(inst);
+ writel(val, pmc_base + PMC_TRIGGERS);
+
+ val = readl(base + UTMIP_PMC_WAKEUP0);
+ val &= ~EVENT_INT_ENB;
+ writel(val, base + UTMIP_PMC_WAKEUP0);
+ phy->remote_wakeup = true;
+ return true;
+ }
+ }
+ return false;
+}
+
+static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
+{
+ void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
+ void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+ static bool init_done = false;
+ u32 val;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ /* Should be done only once after system boot */
+ if (init_done)
+ return;
+
+ clk_enable(phy->utmi_pad_clk);
+ /* Bias pad MASTER_ENABLE=1 */
+ val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
+ val |= BIAS_MASTER_PROG_VAL;
+ writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
+
+ /* Setting the tracking length time */
+ val = readl(base + UTMIP_BIAS_CFG1);
+ val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
+ val |= UTMIP_BIAS_PDTRK_COUNT(5);
+ writel(val, base + UTMIP_BIAS_CFG1);
+
+ /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
+ val = readl(base + UTMIP_BIAS_CFG1);
+ val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
+ writel(val, base + UTMIP_BIAS_CFG1);
+
+ val = readl(base + UTMIP_BIAS_CFG1);
+ val |= UTMIP_BIAS_PDTRK_POWERUP;
+ writel(val, base + UTMIP_BIAS_CFG1);
+
+ /* Wait for 25usec */
+ udelay(25);
+
+ /* Bias pad MASTER_ENABLE=0 */
+ val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
+ val &= ~BIAS_MASTER_PROG_VAL;
+ writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
+
+ /* Wait for 1usec */
+ udelay(1);
+
+ /* Bias pad MASTER_ENABLE=1 */
+ val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
+ val |= BIAS_MASTER_PROG_VAL;
+ writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
+
+ /* Read RCTRL and TCTRL from UTMIP space */
+ val = readl(base + UTMIP_BIAS_STS0);
+ utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
+ utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
+
+ /* PD_TRK=1 */
+ val = readl(base + UTMIP_BIAS_CFG1);
+ val |= UTMIP_BIAS_PDTRK_POWERDOWN;
+ writel(val, base + UTMIP_BIAS_CFG1);
+
+ /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
+ val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
+ val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
+ writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
+ clk_disable(phy->utmi_pad_clk);
+ init_done = true;
+}
+
+static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+ unsigned int inst = phy->inst;
+
+ /* power down UTMIP interfaces */
+ val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
+ val |= UTMIP_PWR(inst);
+ writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
+
+ /* setup sleep walk usb controller */
+ val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
+ UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
+ UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
+ UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
+ writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
+
+ /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
+ val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
+ val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
+ writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
+
+ /* Turn over pad configuration to PMC */
+ val = readl(pmc_base + PMC_SLEEP_CFG);
+ val &= ~UTMIP_WAKE_VAL(inst, ~0);
+ val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
+ UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
+ UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
+ writel(val, pmc_base + PMC_SLEEP_CFG);
+ PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
+}
+
+static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+ unsigned int inst = phy->inst;
+
+ /* Disable PMC master mode by clearing MASTER_EN */
+ val = readl(pmc_base + PMC_SLEEP_CFG);
+ val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
+ UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
+ writel(val, pmc_base + PMC_SLEEP_CFG);
+ mdelay(1);
+ PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
+}
+
+static void uhsic_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+
+ /* turn on pad detectors for HSIC*/
+ val = readl(pmc_base + PMC_USB_AO);
+ val |= (HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
+ writel(val, pmc_base + PMC_USB_AO);
+
+ /* enable pull downs on HSIC PMC */
+ val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
+ UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
+ UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
+ writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
+
+ /* Turn over pad configuration to PMC */
+ val = readl(pmc_base + PMC_SLEEP_CFG);
+ val &= ~UHSIC_WAKE_VAL_P0(~0);
+ val |= UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) | UHSIC_MASTER_ENABLE_P0;
+ writel(val, pmc_base + PMC_SLEEP_CFG);
+}
+
+static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+
+ /* turn on pad detectors for HSIC*/
+ val = readl(pmc_base + PMC_USB_AO);
+ val &= ~(HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
+ writel(val, pmc_base + PMC_USB_AO);
+
+ /* Disable PMC master mode by clearing MASTER_EN */
+ val = readl(pmc_base + PMC_SLEEP_CFG);
+ val &= ~(UHSIC_MASTER_ENABLE_P0);
+ writel(val, pmc_base + PMC_SLEEP_CFG);
+ mdelay(1);
+}
+
+static void usb_phy_power_down_pmc(void)
+{
+ unsigned long val;
+ void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+
+ /* power down all 3 UTMIP interfaces */
+ val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
+ val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
+ writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
+
+ /* turn on pad detectors */
+ writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
+
+ /* setup sleep walk fl all 3 usb controllers */
+ val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
+ UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
+ UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
+ UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
+ writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
+ writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
+ writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
+
+ /* enable pull downs on HSIC PMC */
+ val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
+ UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
+ UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
+ writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
+
+ /* Turn over pad configuration to PMC */
+ val = readl(pmc_base + PMC_SLEEP_CFG);
+ val &= ~UTMIP_WAKE_VAL(0, ~0);
+ val &= ~UTMIP_WAKE_VAL(1, ~0);
+ val &= ~UTMIP_WAKE_VAL(2, ~0);
+ val &= ~UHSIC_WAKE_VAL_P0(~0);
+ val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
+ UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
+ UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
+ UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
+ UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
+ UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
+ UHSIC_MASTER_ENABLE_P0;
+ writel(val, pmc_base + PMC_SLEEP_CFG);
+}
+
+static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
+ readl(base + USB_USBSTS), readl(base + USB_PORTSC),
+ phy->port_speed);
+
+ /* Device is plugged in when system is in LP0 */
+ /* Bring up the controller from LP0*/
+ val = readl(base + USB_USBCMD);
+ val |= USB_CMD_RESET;
+ writel(val, base + USB_USBCMD);
+
+ if (usb_phy_reg_status_wait(base + USB_USBCMD,
+ USB_CMD_RESET, 0, 2500) < 0) {
+ pr_err("%s: timeout waiting for reset\n", __func__);
+ }
+
+ val = readl(base + USB_USBMODE);
+ val &= ~USB_USBMODE_MASK;
+ val |= USB_USBMODE_HOST;
+ writel(val, base + USB_USBMODE);
+
+ val = readl(base + HOSTPC1_DEVLC);
+ val &= ~HOSTPC1_DEVLC_PTS(~0);
+ val |= HOSTPC1_DEVLC_STS;
+ writel(val, base + HOSTPC1_DEVLC);
+
+ /* Enable Port Power */
+ val = readl(base + USB_PORTSC);
+ val |= USB_PORTSC_PP;
+ writel(val, base + USB_PORTSC);
+ udelay(10);
+
+ /* Check if the phy resume from LP0. When the phy resume from LP0
+ * USB register will be reset.to zero */
+ if (!readl(base + USB_ASYNCLISTADDR)) {
+ /* Program the field PTC based on the saved speed mode */
+ val = readl(base + USB_PORTSC);
+ val &= ~USB_PORTSC_PTC(~0);
+ if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
+ val |= USB_PORTSC_PTC(5);
+ else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
+ val |= USB_PORTSC_PTC(6);
+ else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
+ val |= USB_PORTSC_PTC(7);
+ writel(val, base + USB_PORTSC);
+ udelay(10);
+
+ /* Disable test mode by setting PTC field to NORMAL_OP */
+ val = readl(base + USB_PORTSC);
+ val &= ~USB_PORTSC_PTC(~0);
+ writel(val, base + USB_PORTSC);
+ udelay(10);
+ }
+
+ /* Poll until CCS is enabled */
+ if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
+ USB_PORTSC_CCS, 2000)) {
+ pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
+ }
+
+ /* Poll until PE is enabled */
+ if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
+ USB_PORTSC_PE, 2000)) {
+ pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
+ }
+
+ /* Clear the PCI status, to avoid an interrupt taken upon resume */
+ val = readl(base + USB_USBSTS);
+ val |= USB_USBSTS_PCI;
+ writel(val, base + USB_USBSTS);
+
+ if (!phy->remote_wakeup) {
+ /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
+ val = readl(base + USB_PORTSC);
+ if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
+ val |= USB_PORTSC_SUSP;
+ writel(val, base + USB_PORTSC);
+ /* Need a 4ms delay before the controller goes to suspend */
+ mdelay(4);
+
+ /* Wait until port suspend completes */
+ if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
+ USB_PORTSC_SUSP, 1000)) {
+ pr_err("%s: timeout waiting for PORT_SUSPEND\n",
+ __func__);
+ }
+ }
+ }
+ PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
+ readl(base + USB_USBSTS), readl(base + USB_PORTSC),
+ phy->port_speed);
+
+ DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
+ readl(base + USB_USBSTS), readl(base + USB_PORTSC));
+ return 0;
+}
+
+static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ val = readl(base + USB_USBSTS);
+ writel(val, base + USB_USBSTS);
+ udelay(20);
+ /* wait for two SOFs */
+ if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
+ USB_USBSTS_SRI, 2500))
+ pr_err("%s: timeout waiting for SOF\n", __func__);
+
+ val = readl(base + USB_USBSTS);
+ writel(val, base + USB_USBSTS);
+ if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
+ pr_err("%s: timeout waiting for SOF\n", __func__);
+
+ if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
+ USB_USBSTS_SRI, 2500))
+ pr_err("%s: timeout waiting for SOF\n", __func__);
+
+ udelay(20);
+}
+
+static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
+{
+ struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
+ signed long val;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ if (cfg->xcvr_use_fuses) {
+ val = FUSE_USB_CALIB_XCVR_SETUP(
+ tegra_fuse_readl(FUSE_USB_CALIB_0));
+ if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
+ val = val + cfg->xcvr_setup_offset;
+
+ if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
+ val = UTMIP_XCVR_SETUP_MAX_VALUE;
+ pr_info("%s: reset XCVR_SETUP to max value\n",
+ __func__);
+ } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
+ val = UTMIP_XCVR_SETUP_MIN_VALUE;
+ pr_info("%s: reset XCVR_SETUP to min value\n",
+ __func__);
+ }
+ } else {
+ val = cfg->xcvr_setup;
+ }
+
+ return (unsigned int) val;
+}
+
+static int utmi_phy_open(struct tegra_usb_phy *phy)
+{
+ void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+ unsigned long parent_rate, val;
+ int i;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
+ if (IS_ERR(phy->utmi_pad_clk)) {
+ pr_err("%s: can't get utmip pad clock\n", __func__);
+ return PTR_ERR(phy->utmi_pad_clk);
+ }
+
+ phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
+
+ parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
+ for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
+ if (utmip_freq_table[i].freq == parent_rate) {
+ phy->freq = &utmip_freq_table[i];
+ break;
+ }
+ }
+ if (!phy->freq) {
+ pr_err("invalid pll_u parent rate %ld\n", parent_rate);
+ return -EINVAL;
+ }
+
+ /* Power-up the VBUS detector for UTMIP PHY */
+ val = readl(pmc_base + PMC_USB_AO);
+ val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
+ writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
+
+ utmip_powerup_pmc_wake_detect(phy);
+
+ return 0;
+}
+
+static void utmi_phy_close(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s inst:[%d]\n", __func__, phy->inst);
+
+ /* Disable PHY clock valid interrupts while going into suspend*/
+ if (phy->pdata->u_data.host.hot_plug) {
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~USB_PHY_CLK_VALID_INT_ENB;
+ writel(val, base + USB_SUSP_CTRL);
+ }
+
+ val = readl(base + USB_PORTSC);
+ val |= USB_PORTSC_WKCN;
+ writel(val, base + USB_PORTSC);
+
+ clk_put(phy->utmi_pad_clk);
+}
+
+static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
+{
+ unsigned long val, flags;
+ void __iomem *pad_base = IO_ADDRESS(TEGRA_USB_BASE);
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ clk_enable(phy->utmi_pad_clk);
+
+ spin_lock_irqsave(&utmip_pad_lock, flags);
+ utmip_pad_count++;
+
+ val = readl(pad_base + UTMIP_BIAS_CFG0);
+ val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
+ val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
+ UTMIP_HSDISCON_LEVEL_MSB;
+ writel(val, pad_base + UTMIP_BIAS_CFG0);
+
+ spin_unlock_irqrestore(&utmip_pad_lock, flags);
+
+ clk_disable(phy->utmi_pad_clk);
+
+ return 0;
+}
+
+static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
+{
+ unsigned long val, flags;
+ void __iomem *pad_base = IO_ADDRESS(TEGRA_USB_BASE);
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ clk_enable(phy->utmi_pad_clk);
+ spin_lock_irqsave(&utmip_pad_lock, flags);
+
+ if (!utmip_pad_count) {
+ pr_err("%s: utmip pad already powered off\n", __func__);
+ goto out;
+ }
+ if (--utmip_pad_count == 0) {
+ val = readl(pad_base + UTMIP_BIAS_CFG0);
+ val |= UTMIP_OTGPD | UTMIP_BIASPD;
+ val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
+ UTMIP_HSDISCON_LEVEL_MSB);
+ writel(val, pad_base + UTMIP_BIAS_CFG0);
+ }
+out:
+ spin_unlock_irqrestore(&utmip_pad_lock, flags);
+ clk_disable(phy->utmi_pad_clk);
+
+ return 0;
+}
+
+static int utmi_phy_irq(struct tegra_usb_phy *phy)
+{
+ void __iomem *base = phy->regs;
+ unsigned long val = 0;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
+ readl(base + USB_USBSTS), readl(base + USB_PORTSC));
+ DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
+ readl(base + USB_USBMODE), readl(base + USB_USBCMD));
+
+ usb_phy_fence_read(phy);
+ /* check if there is any remote wake event */
+ if (utmi_phy_remotewake_detected(phy))
+ pr_info("%s: utmip remote wake detected\n", __func__);
+
+ if (phy->pdata->u_data.host.hot_plug) {
+ val = readl(base + USB_SUSP_CTRL);
+ if ((val & USB_PHY_CLK_VALID_INT_STS)) {
+ val &= ~USB_PHY_CLK_VALID_INT_ENB |
+ USB_PHY_CLK_VALID_INT_STS;
+ writel(val , (base + USB_SUSP_CTRL));
+ pr_info("%s: usb device plugged-in\n", __func__);
+ val = readl(base + USB_USBSTS);
+ if (!(val & USB_USBSTS_PCI))
+ return IRQ_NONE;
+ val = readl(base + USB_PORTSC);
+ val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
+ writel(val , (base + USB_PORTSC));
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ /* (2LS WAR)is not required for LS and FS devices and is only for HS */
+ if ((phy->port_speed == USB_PHY_PORT_SPEED_LOW) ||
+ (phy->port_speed == USB_PHY_PORT_SPEED_FULL)) {
+ /* do not enable the OBS bus */
+ val = readl(base + UTMIP_MISC_CFG0);
+ val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
+ writel(val, base + UTMIP_MISC_CFG0);
+ DBG("%s(%d) Disable OBS bus\n", __func__, __LINE__);
+ return;
+ }
+ /* Force DP/DM pulldown active for Host mode */
+ val = readl(base + UTMIP_MISC_CFG0);
+ val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
+ COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
+ writel(val, base + UTMIP_MISC_CFG0);
+ val = readl(base + UTMIP_MISC_CFG0);
+ val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
+ if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
+ val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
+ else
+ val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
+ writel(val, base + UTMIP_MISC_CFG0);
+ udelay(1);
+
+ val = readl(base + UTMIP_MISC_CFG0);
+ val |= UTMIP_DPDM_OBSERVE;
+ writel(val, base + UTMIP_MISC_CFG0);
+ udelay(10);
+ DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
+ PHY_DBG("ENABLE_OBS_BUS\n");
+}
+
+static int utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ /* check if OBS bus is already enabled */
+ val = readl(base + UTMIP_MISC_CFG0);
+ if (val & UTMIP_DPDM_OBSERVE) {
+ PHY_DBG("DISABLE_OBS_BUS\n");
+ /* Change the UTMIP OBS bus to drive SE0 */
+ val = readl(base + UTMIP_MISC_CFG0);
+ val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
+ val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
+ writel(val, base + UTMIP_MISC_CFG0);
+
+ /* Wait for 3us(2 LS bit times) */
+ udelay(3);
+
+ /* Release UTMIP OBS bus */
+ val = readl(base + UTMIP_MISC_CFG0);
+ val &= ~UTMIP_DPDM_OBSERVE;
+ writel(val, base + UTMIP_MISC_CFG0);
+
+ /* Release DP/DM pulldown for Host mode */
+ val = readl(base + UTMIP_MISC_CFG0);
+ val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
+ COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
+ writel(val, base + UTMIP_MISC_CFG0);
+
+ val = readl(base + USB_USBCMD);
+ val |= USB_USBCMD_RS;
+ writel(val, base + USB_USBCMD);
+ if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
+ USB_USBCMD_RS, 2000)) {
+ pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
+ return -ETIMEDOUT;
+ }
+ }
+ return 0;
+}
+
+static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+ unsigned int inst = phy->inst;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ val = readl(pmc_base + PMC_SLEEP_CFG);
+ /* if PMC is not disabled by now then disable it */
+ if (val & UTMIP_MASTER_ENABLE(inst)) {
+ utmip_phy_disable_pmc_bus_ctrl(phy);
+ }
+
+ utmi_phy_disable_obs_bus(phy);
+
+ return 0;
+}
+
+static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
+{
+ unsigned long val;
+ void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+ void __iomem *base = phy->regs;
+ unsigned int inst = phy->inst;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ val = (readl(base + HOSTPC1_DEVLC) >> 25) &
+ HOSTPC1_DEVLC_PSPD_MASK;
+ if (val == USB_PHY_PORT_SPEED_HIGH) {
+ /* Disable interrupts */
+ writel(0, base + USB_USBINTR);
+ /* Clear the run bit to stop SOFs - 2LS WAR */
+ val = readl(base + USB_USBCMD);
+ val &= ~USB_USBCMD_RS;
+ writel(val, base + USB_USBCMD);
+ }
+
+ val = readl(pmc_base + PMC_SLEEP_CFG);
+ if (val & UTMIP_MASTER_ENABLE(inst)) {
+ if (!remote_wakeup)
+ utmip_phy_disable_pmc_bus_ctrl(phy);
+ } else {
+ utmi_phy_enable_obs_bus(phy);
+ }
+
+ return 0;
+}
+
+static int utmi_phy_power_off(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ PHY_DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
+ if (!phy->phy_clk_on) {
+ PHY_DBG("%s(%d) inst:[%d] phy clk is already off\n",
+ __func__, __LINE__, phy->inst);
+ return 0;
+ }
+
+ if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
+ utmip_powerdown_pmc_wake_detect(phy);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
+ val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
+ writel(val, base + USB_SUSP_CTRL);
+
+ val = readl(base + UTMIP_BAT_CHRG_CFG0);
+ val |= UTMIP_PD_CHRG;
+ writel(val, base + UTMIP_BAT_CHRG_CFG0);
+ } else {
+ utmip_setup_pmc_wake_detect(phy);
+ }
+
+ if (!phy->pdata->u_data.host.hot_plug) {
+ val = readl(base + UTMIP_XCVR_CFG0);
+ val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
+ UTMIP_FORCE_PDZI_POWERDOWN);
+ writel(val, base + UTMIP_XCVR_CFG0);
+ }
+
+ val = readl(base + UTMIP_XCVR_CFG1);
+ val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
+ UTMIP_FORCE_PDDR_POWERDOWN;
+ writel(val, base + UTMIP_XCVR_CFG1);
+
+ val = readl(base + UTMIP_BIAS_CFG1);
+ val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
+ writel(val, base + UTMIP_BIAS_CFG1);
+
+ utmi_phy_pad_power_off(phy);
+
+ phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
+ HOSTPC1_DEVLC_PSPD_MASK;
+
+ if (phy->pdata->u_data.host.hot_plug) {
+ bool enable_hotplug = true;
+ /* if it is OTG port then make sure to enable hot-plug feature
+ only if host adaptor is connected, i.e id is low */
+ if (phy->pdata->port_otg) {
+ val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
+ enable_hotplug = (val & USB_ID_STATUS) ? false : true;
+ }
+ if (enable_hotplug) {
+ val = readl(base + USB_PORTSC);
+ val |= USB_PORTSC_WKCN;
+ writel(val, base + USB_PORTSC);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= USB_PHY_CLK_VALID_INT_ENB;
+ writel(val, base + USB_SUSP_CTRL);
+ } else {
+ /* Disable PHY clock valid interrupts while going into suspend*/
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~USB_PHY_CLK_VALID_INT_ENB;
+ writel(val, base + USB_SUSP_CTRL);
+ }
+ }
+
+ val = readl(base + HOSTPC1_DEVLC);
+ val |= HOSTPC1_DEVLC_PHCD;
+ writel(val, base + HOSTPC1_DEVLC);
+
+ if (!phy->pdata->u_data.host.hot_plug) {
+ val = readl(base + USB_SUSP_CTRL);
+ val |= UTMIP_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+ }
+
+ phy->phy_clk_on = false;
+ phy->hw_accessible = false;
+
+ PHY_DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
+
+ return 0;
+}
+
+
+static int utmi_phy_power_on(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+ struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
+
+ PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ if (phy->phy_clk_on) {
+ PHY_DBG("%s(%d) inst:[%d] phy clk is already On\n",
+ __func__, __LINE__, phy->inst);
+ return 0;
+ }
+ val = readl(base + USB_SUSP_CTRL);
+ val |= UTMIP_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+
+ val = readl(base + UTMIP_TX_CFG0);
+ val |= UTMIP_FS_PREABMLE_J;
+ writel(val, base + UTMIP_TX_CFG0);
+
+ val = readl(base + UTMIP_HSRX_CFG0);
+ val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
+ val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
+ val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
+ writel(val, base + UTMIP_HSRX_CFG0);
+
+ val = readl(base + UTMIP_HSRX_CFG1);
+ val &= ~UTMIP_HS_SYNC_START_DLY(~0);
+ val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
+ writel(val, base + UTMIP_HSRX_CFG1);
+
+ val = readl(base + UTMIP_DEBOUNCE_CFG0);
+ val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
+ val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
+ writel(val, base + UTMIP_DEBOUNCE_CFG0);
+
+ val = readl(base + UTMIP_MISC_CFG0);
+ val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
+ writel(val, base + UTMIP_MISC_CFG0);
+
+ if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
+ writel(val, base + USB_SUSP_CTRL);
+
+ val = readl(base + UTMIP_BAT_CHRG_CFG0);
+ val &= ~UTMIP_PD_CHRG;
+ writel(val, base + UTMIP_BAT_CHRG_CFG0);
+ } else {
+ val = readl(base + UTMIP_BAT_CHRG_CFG0);
+ val |= UTMIP_PD_CHRG;
+ writel(val, base + UTMIP_BAT_CHRG_CFG0);
+ }
+
+ utmi_phy_pad_power_on(phy);
+
+ val = readl(base + UTMIP_XCVR_CFG0);
+ val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
+ UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
+ UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
+ UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
+ val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
+ val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
+ val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
+ val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
+ val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
+ writel(val, base + UTMIP_XCVR_CFG0);
+
+ val = readl(base + UTMIP_XCVR_CFG1);
+ val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
+ UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
+ val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
+ writel(val, base + UTMIP_XCVR_CFG1);
+
+ val = readl(base + UTMIP_BIAS_CFG1);
+ val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
+ val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
+ writel(val, base + UTMIP_BIAS_CFG1);
+
+ val = readl(base + UTMIP_SPARE_CFG0);
+ val &= ~FUSE_SETUP_SEL;
+ val |= FUSE_ATERM_SEL;
+ writel(val, base + UTMIP_SPARE_CFG0);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= UTMIP_PHY_ENABLE;
+ writel(val, base + USB_SUSP_CTRL);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~UTMIP_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+
+ val = readl(base + HOSTPC1_DEVLC);
+ val &= ~HOSTPC1_DEVLC_PHCD;
+ writel(val, base + HOSTPC1_DEVLC);
+
+ if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
+ USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
+ pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
+
+ utmi_phy_enable_trking_data(phy);
+
+ if (phy->inst == 2)
+ writel(0, base + ICUSB_CTRL);
+
+ val = readl(base + USB_USBMODE);
+ val &= ~USB_USBMODE_MASK;
+ if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
+ val |= USB_USBMODE_HOST;
+ else
+ val |= USB_USBMODE_DEVICE;
+ writel(val, base + USB_USBMODE);
+
+ val = readl(base + HOSTPC1_DEVLC);
+ val &= ~HOSTPC1_DEVLC_PTS(~0);
+ val |= HOSTPC1_DEVLC_STS;
+ writel(val, base + HOSTPC1_DEVLC);
+
+ if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
+ utmip_powerup_pmc_wake_detect(phy);
+ phy->phy_clk_on = true;
+ phy->hw_accessible = true;
+ PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst);
+ return 0;
+}
+
+static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+ int inst = phy->inst;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ val = readl(pmc_base + UTMIP_UHSIC_STATUS);
+ /* check whether we wake up from the remote resume */
+ if (UTMIP_WALK_PTR_VAL(inst) & val) {
+ phy->remote_wakeup = true;
+ } else {
+ if (!((UTMIP_USBON_VAL(phy->inst) |
+ UTMIP_USBOP_VAL(phy->inst)) & val)) {
+ utmip_phy_disable_pmc_bus_ctrl(phy);
+ }
+ }
+ utmi_phy_enable_obs_bus(phy);
+}
+
+static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+ int wait_time_us = 25000; /* FPR should be set by this time */
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ /* check whether we wake up from the remote resume */
+ if (phy->remote_wakeup) {
+ /* wait until SUSPEND and RESUME bit is cleared on remote resume */
+ do {
+ val = readl(base + USB_PORTSC);
+ udelay(1);
+ if (wait_time_us == 0) {
+ PHY_DBG("%s PMC REMOTE WAKEUP FPR timeout val = 0x%x instance = %d\n", __func__, val, phy->inst);
+ utmip_phy_disable_pmc_bus_ctrl(phy);
+ utmi_phy_post_resume(phy);
+ return;
+ }
+ wait_time_us--;
+ } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
+
+ /* wait for 25 ms to port resume complete */
+ msleep(25);
+ /* disable PMC master control */
+ utmip_phy_disable_pmc_bus_ctrl(phy);
+
+ /* Clear PCI and SRI bits to avoid an interrupt upon resume */
+ val = readl(base + USB_USBSTS);
+ writel(val, base + USB_USBSTS);
+ /* wait to avoid SOF if there is any */
+ if (usb_phy_reg_status_wait(base + USB_USBSTS,
+ USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
+ pr_err("%s: timeout waiting for SOF\n", __func__);
+ }
+ utmi_phy_post_resume(phy);
+ }
+}
+
+static int utmi_phy_resume(struct tegra_usb_phy *phy)
+{
+ int status = 0;
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
+ if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
+ utmi_phy_restore_start(phy);
+ usb_phy_bringup_host_controller(phy);
+ utmi_phy_restore_end(phy);
+ } else {
+ /* device is plugged in when system is in LP0 */
+ /* bring up the controller from LP0*/
+ val = readl(base + USB_USBCMD);
+ val |= USB_CMD_RESET;
+ writel(val, base + USB_USBCMD);
+
+ if (usb_phy_reg_status_wait(base + USB_USBCMD,
+ USB_CMD_RESET, 0, 2500) < 0) {
+ pr_err("%s: timeout waiting for reset\n", __func__);
+ }
+
+ val = readl(base + USB_USBMODE);
+ val &= ~USB_USBMODE_MASK;
+ val |= USB_USBMODE_HOST;
+ writel(val, base + USB_USBMODE);
+
+ val = readl(base + HOSTPC1_DEVLC);
+ val &= ~HOSTPC1_DEVLC_PTS(~0);
+ val |= HOSTPC1_DEVLC_STS;
+ writel(val, base + HOSTPC1_DEVLC);
+
+ writel(USB_USBCMD_RS, base + USB_USBCMD);
+
+ if (usb_phy_reg_status_wait(base + USB_USBCMD,
+ USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
+ pr_err("%s: timeout waiting for run bit\n", __func__);
+ }
+
+ /* Enable Port Power */
+ val = readl(base + USB_PORTSC);
+ val |= USB_PORTSC_PP;
+ writel(val, base + USB_PORTSC);
+ udelay(10);
+
+ DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
+ readl(base + USB_USBSTS), readl(base + USB_PORTSC));
+ }
+ }
+
+ return status;
+}
+
+bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+ bool status;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
+ /* Charger detection is not there for ULPI
+ * return Charger not available */
+ return false;
+ }
+
+ /* Enable charger detection logic */
+ val = readl(base + UTMIP_BAT_CHRG_CFG0);
+ val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
+ writel(val, base + UTMIP_BAT_CHRG_CFG0);
+
+ /* Source should be on for 100 ms as per USB charging spec */
+ msleep(TDP_SRC_ON_MS);
+
+ val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
+ /* If charger is not connected disable the interrupt */
+ val &= ~VDAT_DET_INT_EN;
+ val |= VDAT_DET_CHG_DET;
+ writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
+
+ val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
+ if (val & VDAT_DET_STS)
+ status = true;
+ else
+ status = false;
+
+ /* Disable charger detection logic */
+ val = readl(base + UTMIP_BAT_CHRG_CFG0);
+ val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
+ writel(val, base + UTMIP_BAT_CHRG_CFG0);
+
+ /* Delay of 40 ms before we pull the D+ as per battery charger spec */
+ msleep(TDPSRC_CON_MS);
+
+ return status;
+}
+
+static int uhsic_phy_open(struct tegra_usb_phy *phy)
+{
+ unsigned long parent_rate;
+ int i;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
+ for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
+ if (uhsic_freq_table[i].freq == parent_rate) {
+ phy->freq = &uhsic_freq_table[i];
+ break;
+ }
+ }
+ if (!phy->freq) {
+ pr_err("invalid pll_u parent rate %ld\n", parent_rate);
+ return -EINVAL;
+ }
+
+ utmip_powerup_pmc_wake_detect(phy);
+
+ return 0;
+}
+
+static int uhsic_phy_irq(struct tegra_usb_phy *phy)
+{
+ usb_phy_fence_read(phy);
+ return IRQ_HANDLED;
+}
+
+static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+ struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ utmip_powerup_pmc_wake_detect(phy);
+
+ if (phy->phy_clk_on) {
+ DBG("%s(%d) inst:[%d] phy clk is already On\n",
+ __func__, __LINE__, phy->inst);
+ return 0;
+ }
+
+ val = readl(base + UHSIC_PADS_CFG1);
+ val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
+ UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
+ val |= UHSIC_RX_SEL;
+ writel(val, base + UHSIC_PADS_CFG1);
+ udelay(2);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= UHSIC_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+ udelay(30);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= UHSIC_PHY_ENABLE;
+ writel(val, base + USB_SUSP_CTRL);
+
+ val = readl(base + UHSIC_HSRX_CFG0);
+ val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
+ val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
+ val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
+ writel(val, base + UHSIC_HSRX_CFG0);
+
+ val = readl(base + UHSIC_HSRX_CFG1);
+ val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
+ writel(val, base + UHSIC_HSRX_CFG1);
+
+ /* WAR HSIC TX */
+ val = readl(base + UHSIC_TX_CFG0);
+ val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
+ writel(val, base + UHSIC_TX_CFG0);
+
+ val = readl(base + UHSIC_MISC_CFG0);
+ val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
+ /* Disable generic bus reset, to allow AP30 specific bus reset*/
+ val |= UHSIC_DISABLE_BUSRESET;
+ writel(val, base + UHSIC_MISC_CFG0);
+
+ val = readl(base + UHSIC_MISC_CFG1);
+ val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
+ writel(val, base + UHSIC_MISC_CFG1);
+
+ val = readl(base + UHSIC_PLL_CFG1);
+ val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
+ val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
+ writel(val, base + UHSIC_PLL_CFG1);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~(UHSIC_RESET);
+ writel(val, base + USB_SUSP_CTRL);
+ udelay(2);
+
+ val = readl(base + USB_USBMODE);
+ val |= USB_USBMODE_HOST;
+ writel(val, base + USB_USBMODE);
+
+ /* Change the USB controller PHY type to HSIC */
+ val = readl(base + HOSTPC1_DEVLC);
+ val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
+ val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
+ val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
+ val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
+ writel(val, base + HOSTPC1_DEVLC);
+
+ val = readl(base + USB_TXFILLTUNING);
+ if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
+ val = USB_FIFO_TXFILL_THRES(0x10);
+ writel(val, base + USB_TXFILLTUNING);
+ }
+
+ val = readl(base + USB_PORTSC);
+ val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
+ writel(val, base + USB_PORTSC);
+
+ val = readl(base + UHSIC_PADS_CFG0);
+ val &= ~(UHSIC_TX_RTUNEN);
+ /* set Rtune impedance to 50 ohm */
+ val |= UHSIC_TX_RTUNE(8);
+ writel(val, base + UHSIC_PADS_CFG0);
+
+ if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
+ USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
+ pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ phy->phy_clk_on = true;
+ phy->hw_accessible = true;
+
+ return 0;
+}
+
+static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ if (!phy->phy_clk_on) {
+ DBG("%s(%d) inst:[%d] phy clk is already off\n",
+ __func__, __LINE__, phy->inst);
+ return 0;
+ }
+
+ val = readl(base + UHSIC_PADS_CFG1);
+ val &= ~UHSIC_RPU_STROBE;
+ val |= UHSIC_RPD_STROBE;
+ writel(val, base + UHSIC_PADS_CFG1);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= UHSIC_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+ udelay(30);
+
+ utmip_powerdown_pmc_wake_detect(phy);
+
+ phy->phy_clk_on = false;
+ phy->hw_accessible = false;
+
+ return 0;
+}
+
+int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ val = readl(base + UHSIC_STAT_CFG0);
+ val &= ~UHSIC_CONNECT_DETECT;
+ writel(val, base + UHSIC_STAT_CFG0);
+
+ val = readl(base + USB_USBMODE);
+ val |= USB_USBMODE_HOST;
+ writel(val, base + USB_USBMODE);
+
+ /* Change the USB controller PHY type to HSIC */
+ val = readl(base + HOSTPC1_DEVLC);
+ val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
+ val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
+ val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
+ val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
+ writel(val, base + HOSTPC1_DEVLC);
+
+ val = readl(base + UHSIC_MISC_CFG0);
+ val |= UHSIC_DETECT_SHORT_CONNECT;
+ writel(val, base + UHSIC_MISC_CFG0);
+ udelay(1);
+
+ val = readl(base + UHSIC_MISC_CFG0);
+ val |= UHSIC_FORCE_XCVR_MODE;
+ writel(val, base + UHSIC_MISC_CFG0);
+
+ val = readl(base + UHSIC_PADS_CFG1);
+ val &= ~UHSIC_RPD_STROBE;
+ /* safe to enable RPU on STROBE at all times during idle */
+ val |= UHSIC_RPU_STROBE;
+ writel(val, base + UHSIC_PADS_CFG1);
+
+ val = readl(base + USB_USBCMD);
+ val &= ~USB_USBCMD_RS;
+ writel(val, base + USB_USBCMD);
+
+ if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
+ UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
+ pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
+ __func__);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ /* Change the USB controller PHY type to HSIC */
+ val = readl(base + HOSTPC1_DEVLC);
+ val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
+ val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
+ val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
+ val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
+ writel(val, base + HOSTPC1_DEVLC);
+ /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
+ mdelay(5);
+
+ val = readl(base + USB_PORTSC);
+ val |= USB_PORTSC_PTC(5);
+ writel(val, base + USB_PORTSC);
+ udelay(2);
+
+ val = readl(base + USB_PORTSC);
+ val &= ~(USB_PORTSC_PTC(~0));
+ writel(val, base + USB_PORTSC);
+ udelay(2);
+
+ if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
+ 0, 2000)) {
+ pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ /* Poll until CCS is enabled */
+ if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
+ USB_PORTSC_CCS, 2000)) {
+ pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
+ HOSTPC1_DEVLC_PSPD(2),
+ HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
+ pr_err("%s: timeout waiting hsic high speed configuration\n",
+ __func__);
+ return -ETIMEDOUT;
+ }
+
+ val = readl(base + USB_USBCMD);
+ val &= ~USB_USBCMD_RS;
+ writel(val, base + USB_USBCMD);
+
+ if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
+ USB_USBSTS_HCH, 2000)) {
+ pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ val = readl(base + UHSIC_PADS_CFG1);
+ val &= ~UHSIC_RPU_STROBE;
+ val |= UHSIC_RPD_STROBE;
+ writel(val, base + UHSIC_PADS_CFG1);
+
+ mdelay(50);
+
+ val = readl(base + UHSIC_PADS_CFG1);
+ val &= ~UHSIC_RPD_STROBE;
+ val |= UHSIC_RPU_STROBE;
+ writel(val, base + UHSIC_PADS_CFG1);
+
+ val = readl(base + USB_USBCMD);
+ val |= USB_USBCMD_RS;
+ writel(val, base + USB_USBCMD);
+
+ val = readl(base + UHSIC_PADS_CFG1);
+ val &= ~UHSIC_RPU_STROBE;
+ writel(val, base + UHSIC_PADS_CFG1);
+
+ if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
+ USB_USBCMD_RS, 2000)) {
+ pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+
+int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
+{
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ usb_phy_wait_for_sof(phy);
+
+ return 0;
+}
+
+int uhsic_phy_resume(struct tegra_usb_phy *phy)
+{
+ void __iomem *base = phy->regs;
+ unsigned long val;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ /* Check if the phy resume from LP0. When the phy resume from LP0
+ * USB register will be reset.to zero */
+ if (!readl(base + USB_ASYNCLISTADDR)) {
+
+ val = readl(base + USB_USBCMD);
+ val |= USB_CMD_RESET;
+ writel(val, base + USB_USBCMD);
+
+ if (usb_phy_reg_status_wait(base + USB_USBCMD,
+ USB_CMD_RESET, 0, 2500) < 0) {
+ pr_err("%s: timeout waiting for reset\n", __func__);
+ }
+
+ val = readl(base + USB_USBMODE);
+ val &= ~USB_USBMODE_MASK;
+ val |= USB_USBMODE_HOST;
+ writel(val, base + USB_USBMODE);
+
+ /* Enable Port Power */
+ val = readl(base + USB_PORTSC);
+ val |= USB_PORTSC_PP;
+ writel(val, base + USB_PORTSC);
+ udelay(10);
+
+ DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
+ readl(base + USB_USBSTS), readl(base + USB_PORTSC));
+
+ uhsic_phy_bus_port_power(phy);
+ }
+
+ return 0;
+}
+
+static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ val = readl(base + USB_TXFILLTUNING);
+ if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
+ val = USB_FIFO_TXFILL_THRES(0x10);
+ writel(val, base + USB_TXFILLTUNING);
+ }
+
+ return 0;
+}
+
+static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
+{
+ struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
+ void __iomem *base = phy->regs;
+ unsigned long val;
+
+ val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
+ val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
+ val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
+ writel(val, base + ULPI_TIMING_CTRL_1);
+ udelay(10);
+
+ val |= ULPI_DATA_TRIMMER_LOAD;
+ val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
+ val |= ULPI_DIR_TRIMMER_LOAD;
+ writel(val, base + ULPI_TIMING_CTRL_1);
+}
+
+static void reset_utmip_uhsic(void __iomem *base)
+{
+ unsigned long val;
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= UHSIC_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= UTMIP_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+}
+
+static void ulpi_set_host(void __iomem *base)
+{
+ unsigned long val;
+
+ val = readl(base + USB_USBMODE);
+ val |= USB_USBMODE_HOST;
+ writel(val, base + USB_USBMODE);
+
+ val = readl(base + HOSTPC1_DEVLC);
+ val |= HOSTPC1_DEVLC_PTS(2);
+ writel(val, base + HOSTPC1_DEVLC);
+}
+
+
+
+static inline void null_phy_set_tristate(bool enable)
+{
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+ int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
+ DBG("%s(%d) inst:[%s] FIXME enable pin group +++\n", __func__,
+ __LINE__, enable ? "TRISTATE" : "NORMAL");
+
+ tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
+ tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
+ tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
+ tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
+ tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
+ tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
+ tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
+ tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
+ tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
+
+ if (enable)
+ tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
+#endif
+
+}
+
+
+static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
+{
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ if (!phy->phy_clk_on) {
+ DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
+ __LINE__, phy->inst);
+ return 0;
+ }
+
+ null_phy_set_tristate(true);
+
+ phy->phy_clk_on = false;
+ phy->hw_accessible = false;
+
+ return 0;
+}
+
+static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ val = readl(base + ULPIS2S_CTRL);
+ val |= ULPIS2S_SLV0_CLAMP_XMIT;
+ writel(val, base + ULPIS2S_CTRL);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= ULPIS2S_SLV0_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+ udelay(10);
+
+ return 0;
+}
+
+static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
+{
+ usb_phy_fence_read(phy);
+ return IRQ_HANDLED;
+}
+
+static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ ulpi_set_host(base);
+
+ /* remove slave0 reset */
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~ULPIS2S_SLV0_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+
+ val = readl(base + ULPIS2S_CTRL);
+ val &= ~ULPIS2S_SLV0_CLAMP_XMIT;
+ writel(val, base + ULPIS2S_CTRL);
+ udelay(10);
+
+ return 0;
+}
+
+static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
+{
+ unsigned long val;
+ void __iomem *base = phy->regs;
+ struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
+ static bool cold_boot = true;
+
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ if (phy->phy_clk_on) {
+ DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
+ __LINE__, phy->inst);
+ return 0;
+ }
+ reset_utmip_uhsic(base);
+
+ /* remove ULPI PADS CLKEN reset */
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~ULPI_PADS_CLKEN_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+ udelay(10);
+
+ val = readl(base + ULPI_TIMING_CTRL_0);
+ val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
+ writel(val, base + ULPI_TIMING_CTRL_0);
+
+ val = readl(base + USB_SUSP_CTRL);
+ val |= ULPI_PHY_ENABLE;
+ writel(val, base + USB_SUSP_CTRL);
+ udelay(10);
+
+ /* set timming parameters */
+ val = readl(base + ULPI_TIMING_CTRL_0);
+ val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
+ val &= ~ULPI_SHADOW_CLK_SEL;
+ val &= ~ULPI_LBK_PAD_EN;
+ val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
+ val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
+ val |= ULPI_LBK_PAD_E_INPUT_OR;
+ writel(val, base + ULPI_TIMING_CTRL_0);
+
+ writel(0, base + ULPI_TIMING_CTRL_1);
+ udelay(10);
+
+ /* start internal 60MHz clock */
+ val = readl(base + ULPIS2S_CTRL);
+ val |= ULPIS2S_ENA;
+ val |= ULPIS2S_SUPPORT_DISCONNECT;
+ val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
+ val |= ULPIS2S_PLLU_MASTER_BLASTER60;
+ writel(val, base + ULPIS2S_CTRL);
+
+ /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
+ val = readl(base + ULPI_TIMING_CTRL_0);
+ val |= ULPI_CORE_CLK_SEL;
+ writel(val, base + ULPI_TIMING_CTRL_0);
+ udelay(10);
+
+ /* enable ULPI null phy clock - can't set the trimmers before this */
+ val = readl(base + ULPI_TIMING_CTRL_0);
+ val |= ULPI_CLK_OUT_ENA;
+ writel(val, base + ULPI_TIMING_CTRL_0);
+ udelay(10);
+
+ if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
+ USB_PHY_CLK_VALID, 2500)) {
+ pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ /* set ULPI trimmers */
+ ulpi_set_trimmer(phy);
+
+ ulpi_set_host(base);
+
+ /* remove slave0 reset */
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~ULPIS2S_SLV0_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+
+ /* remove slave1 and line reset */
+ val = readl(base + USB_SUSP_CTRL);
+ val &= ~ULPIS2S_SLV1_RESET;
+ val &= ~ULPIS2S_LINE_RESET;
+
+ /* remove ULPI PADS reset */
+ val &= ~ULPI_PADS_RESET;
+ writel(val, base + USB_SUSP_CTRL);
+
+ if (cold_boot) {
+ val = readl(base + ULPI_TIMING_CTRL_0);
+ val |= ULPI_CLK_PADOUT_ENA;
+ writel(val, base + ULPI_TIMING_CTRL_0);
+ cold_boot = false;
+ }
+ udelay(10);
+
+ phy->phy_clk_on = true;
+ phy->hw_accessible = true;
+
+ return 0;
+}
+
+
+int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
+{
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ usb_phy_wait_for_sof(phy);
+ return 0;
+}
+
+static struct tegra_usb_phy_ops utmi_phy_ops = {
+ .open = utmi_phy_open,
+ .close = utmi_phy_close,
+ .irq = utmi_phy_irq,
+ .power_on = utmi_phy_power_on,
+ .power_off = utmi_phy_power_off,
+ .pre_resume = utmi_phy_pre_resume,
+ .resume = utmi_phy_resume,
+ .post_resume = utmi_phy_post_resume,
+ .charger_detect = utmi_phy_charger_detect,
+};
+
+static struct tegra_usb_phy_ops uhsic_phy_ops = {
+ .open = uhsic_phy_open,
+ .irq = uhsic_phy_irq,
+ .power_on = uhsic_phy_power_on,
+ .power_off = uhsic_phy_power_off,
+ .pre_resume = uhsic_phy_pre_resume,
+ .resume = uhsic_phy_resume,
+ .post_resume = uhsic_phy_post_resume,
+ .port_power = uhsic_phy_bus_port_power,
+ .bus_reset = uhsic_phy_bus_reset,
+};
+
+static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
+ .init = ulpi_null_phy_init,
+ .irq = ulpi_null_phy_irq,
+ .power_on = ulpi_null_phy_power_on,
+ .power_off = ulpi_null_phy_power_off,
+ .pre_resume = ulpi_null_phy_pre_resume,
+ .reset = ulpi_null_phy_cmd_reset,
+};
+
+static struct tegra_usb_phy_ops ulpi_link_phy_ops;
+static struct tegra_usb_phy_ops icusb_phy_ops;
+
+static struct tegra_usb_phy_ops *phy_ops[] = {
+ [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
+ [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
+ [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
+ [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
+ [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
+};
+
+int tegra3_usb_phy_init_ops(struct tegra_usb_phy *phy)
+{
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+
+ phy->ops = phy_ops[phy->pdata->phy_intf];
+
+ /* FIXME: uncommenting below line to make USB host mode fail*/
+ /* usb_phy_power_down_pmc(); */
+
+ return 0;
+}
diff --git a/arch/arm/mach-tegra/tegra_usb_phy.h b/arch/arm/mach-tegra/tegra_usb_phy.h
new file mode 100644
index 00000000..36b88db
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra_usb_phy.h
@@ -0,0 +1,104 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tegra_usb_phy.h
+ *
+ * Copyright (C) 2011 NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_USB_PHY_H
+#define __MACH_TEGRA_USB_PHY_H
+
+/**
+ * defines USB port speeds supported in USB2.0
+ */
+enum usb_phy_port_speed {
+ USB_PHY_PORT_SPEED_FULL = 0,
+ USB_PHY_PORT_SPEED_LOW,
+ USB_PHY_PORT_SPEED_HIGH,
+ USB_PHY_PORT_SPEED_UNKNOWN,
+};
+
+/**
+ * defines structure for oscillator dependent parameters
+ */
+struct tegra_xtal_freq {
+ int freq;
+ u8 enable_delay;
+ u8 stable_count;
+ u8 active_delay;
+ u16 xtal_freq_count;
+ u16 debounce;
+ u8 pdtrk_count;
+};
+
+/**
+ * pre decleration of the usb phy data structure
+ */
+struct tegra_usb_phy;
+
+/**
+ * defines function pointers used for differnt phy interfaces
+ */
+struct tegra_usb_phy_ops {
+ int (*open)(struct tegra_usb_phy *phy);
+ void (*close)(struct tegra_usb_phy *phy);
+ int (*irq)(struct tegra_usb_phy *phy);
+ int (*init)(struct tegra_usb_phy *phy);
+ int (*reset)(struct tegra_usb_phy *phy);
+ int (*pre_suspend)(struct tegra_usb_phy *phy);
+ int (*suspend)(struct tegra_usb_phy *phy);
+ int (*post_suspend)(struct tegra_usb_phy *phy);
+ int (*pre_resume)(struct tegra_usb_phy *phy, bool remote_wakeup);
+ int (*resume)(struct tegra_usb_phy *phy);
+ int (*post_resume)(struct tegra_usb_phy *phy);
+ int (*port_power)(struct tegra_usb_phy *phy);
+ int (*bus_reset)(struct tegra_usb_phy *phy);
+ int (*power_off)(struct tegra_usb_phy *phy);
+ int (*power_on)(struct tegra_usb_phy *phy);
+ bool (*charger_detect)(struct tegra_usb_phy *phy);
+};
+
+/**
+ * defines usb phy data structure
+ */
+struct tegra_usb_phy {
+ struct platform_device *pdev;
+ struct tegra_usb_platform_data *pdata;
+ struct clk *pllu_clk;
+ struct clk *ctrlr_clk;
+ struct clk *ulpi_clk;
+ struct clk *utmi_pad_clk;
+ struct clk *emc_clk;
+ struct clk *sys_clk;
+ struct regulator *vdd_reg;
+ struct regulator *vbus_reg;
+ struct tegra_usb_phy_ops *ops;
+ struct tegra_xtal_freq *freq;
+ struct otg_transceiver *ulpi_vp;
+ enum usb_phy_port_speed port_speed;
+ signed char utmi_xcvr_setup;
+ void __iomem *regs;
+ int inst;
+ bool phy_clk_on;
+ bool phy_power_on;
+ bool remote_wakeup;
+ bool hw_accessible;
+};
+
+int usb_phy_reg_status_wait(void __iomem *reg, u32 mask,
+ u32 result, u32 timeout);
+
+int tegra3_usb_phy_init_ops(struct tegra_usb_phy *phy);
+int tegra2_usb_phy_init_ops(struct tegra_usb_phy *phy);
+
+
+#endif /* __MACH_TEGRA_USB_PHY_H */
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index 8c36159..6f568fd 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -18,7 +18,6 @@
* GNU General Public License for more details.
*
*/
-
#include <linux/resource.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
@@ -27,581 +26,16 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <asm/mach-types.h>
-#include <mach/usb_phy.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+#include <linux/platform_data/tegra_usb.h>
+#include "tegra_usb_phy.h"
#include <mach/iomap.h>
-#include <mach/pinmux.h>
-#include "fuse.h"
-
-
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-#define USB_USBCMD 0x140
-#define USB_USBCMD_RS (1 << 0)
-
-#define USB_USBSTS 0x144
-#define USB_USBSTS_PCI (1 << 2)
-#define USB_USBSTS_HCH (1 << 12)
-
-#define USB_TXFILLTUNING 0x164
-#define USB_FIFO_TXFILL_THRES(x) (((x) & 0x1f) << 16)
-#define USB_FIFO_TXFILL_MASK 0x1f0000
-
-#define ULPI_VIEWPORT 0x170
-#define ULPI_WAKEUP (1 << 31)
-#define ULPI_RUN (1 << 30)
-#define ULPI_RD_WR (1 << 29)
-
-#define USB_PORTSC1 0x184
-#define USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
-#define USB_PORTSC1_PSPD(x) (((x) & 0x3) << 26)
-#define USB_PORTSC1_PHCD (1 << 23)
-#define USB_PORTSC1_WKOC (1 << 22)
-#define USB_PORTSC1_WKDS (1 << 21)
-#define USB_PORTSC1_WKCN (1 << 20)
-#define USB_PORTSC1_PTC(x) (((x) & 0xf) << 16)
-#define USB_PORTSC1_PP (1 << 12)
-#define USB_PORTSC1_LS(x) (((x) & 0x3) << 10)
-#define USB_PORTSC1_SUSP (1 << 7)
-#define USB_PORTSC1_PE (1 << 2)
-#define USB_PORTSC1_CCS (1 << 0)
-
-#define USB_SUSP_CTRL 0x400
-#define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
-#define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
-#define USB_SUSP_CLR (1 << 5)
-#define USB_CLKEN (1 << 6)
-#define USB_PHY_CLK_VALID (1 << 7)
-#define USB_PHY_CLK_VALID_INT_ENB (1 << 9)
-#define UTMIP_RESET (1 << 11)
-#define UHSIC_RESET (1 << 11)
-#define UTMIP_PHY_ENABLE (1 << 12)
-#define UHSIC_PHY_ENABLE (1 << 12)
-#define ULPI_PHY_ENABLE (1 << 13)
-#define USB_SUSP_SET (1 << 14)
-#define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
-
-#define USB_PHY_VBUS_WAKEUP_ID 0x408
-#define VDAT_DET_INT_EN (1 << 16)
-#define VDAT_DET_CHG_DET (1 << 17)
-#define VDAT_DET_STS (1 << 18)
-
-#define USB1_LEGACY_CTRL 0x410
-#define USB1_NO_LEGACY_MODE (1 << 0)
-#define USB1_VBUS_SENSE_CTL_MASK (3 << 1)
-#define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1)
-#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
- (1 << 1)
-#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1)
-#define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1)
-
-
-#define UTMIP_PLL_CFG1 0x804
-#define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
-#define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
-
-#define UTMIP_XCVR_CFG0 0x808
-#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
-#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
-#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
-#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
-#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
-#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
-#define UTMIP_XCVR_LSBIAS_SEL (1 << 21)
-#define UTMIP_XCVR_SETUP_MSB(x) (((x) & 0x7) << 22)
-#define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25)
-
-#define UTMIP_XCVR_MAX_OFFSET 2
-#define UTMIP_XCVR_SETUP_MAX_VALUE 0x7f
-#define UTMIP_XCVR_SETUP_MIN_VALUE 0
-#define XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
-
-#define UTMIP_BIAS_CFG0 0x80c
-#define UTMIP_OTGPD (1 << 11)
-#define UTMIP_BIASPD (1 << 10)
-
-#define UTMIP_HSRX_CFG0 0x810
-#define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
-#define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
-
-#define UTMIP_HSRX_CFG1 0x814
-#define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
-
-#define UTMIP_TX_CFG0 0x820
-#define UTMIP_FS_PREABMLE_J (1 << 19)
-#define UTMIP_HS_DISCON_DISABLE (1 << 8)
-
-#define UTMIP_MISC_CFG1 0x828
-#define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
-#define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6)
-
-#define UTMIP_DEBOUNCE_CFG0 0x82c
-#define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
-
-#define UTMIP_BAT_CHRG_CFG0 0x830
-#define UTMIP_PD_CHRG (1 << 0)
-#define UTMIP_ON_SINK_EN (1 << 2)
-#define UTMIP_OP_SRC_EN (1 << 3)
-
-#define UTMIP_XCVR_CFG1 0x838
-#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
-#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
-#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
-#define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
-
-#define UTMIP_BIAS_CFG1 0x83c
-#define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
-
-#define UHSIC_PLL_CFG1 0x804
-#define UHSIC_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
-#define UHSIC_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 14)
-
-#define UHSIC_HSRX_CFG0 0x808
-#define UHSIC_ELASTIC_UNDERRUN_LIMIT(x) (((x) & 0x1f) << 2)
-#define UHSIC_ELASTIC_OVERRUN_LIMIT(x) (((x) & 0x1f) << 8)
-#define UHSIC_IDLE_WAIT(x) (((x) & 0x1f) << 13)
-
-#define UHSIC_HSRX_CFG1 0x80c
-#define UHSIC_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
-
-#define UHSIC_TX_CFG0 0x810
-#define UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE (1 << 6)
-
-#define UHSIC_MISC_CFG0 0x814
-#define UHSIC_SUSPEND_EXIT_ON_EDGE (1 << 7)
-#define UHSIC_DETECT_SHORT_CONNECT (1 << 8)
-#define UHSIC_FORCE_XCVR_MODE (1 << 15)
-
-#define UHSIC_MISC_CFG1 0X818
-#define UHSIC_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 2)
-
-#define UHSIC_PADS_CFG0 0x81c
-#define UHSIC_TX_RTUNEN 0xf000
-#define UHSIC_TX_RTUNE(x) (((x) & 0xf) << 12)
-
-#define UHSIC_PADS_CFG1 0x820
-#define UHSIC_PD_BG (1 << 2)
-#define UHSIC_PD_TX (1 << 3)
-#define UHSIC_PD_TRK (1 << 4)
-#define UHSIC_PD_RX (1 << 5)
-#define UHSIC_PD_ZI (1 << 6)
-#define UHSIC_RX_SEL (1 << 7)
-#define UHSIC_RPD_DATA (1 << 9)
-#define UHSIC_RPD_STROBE (1 << 10)
-#define UHSIC_RPU_DATA (1 << 11)
-#define UHSIC_RPU_STROBE (1 << 12)
-
-#define UHSIC_STAT_CFG0 0x828
-#define UHSIC_CONNECT_DETECT (1 << 0)
-
-
-#else
-#define USB_USBCMD 0x130
-#define USB_USBCMD_RS (1 << 0)
-
-#define USB_USBSTS 0x134
-#define USB_USBSTS_PCI (1 << 2)
-#define USB_USBSTS_SRI (1 << 7)
-#define USB_USBSTS_HCH (1 << 12)
-
-#define USB_TXFILLTUNING 0x154
-#define USB_FIFO_TXFILL_THRES(x) (((x) & 0x1f) << 16)
-#define USB_FIFO_TXFILL_MASK 0x1f0000
-
-#define ULPI_VIEWPORT 0x160
-
-#define USB_PORTSC1 0x174
-#define USB_PORTSC1_WKOC (1 << 22)
-#define USB_PORTSC1_WKDS (1 << 21)
-#define USB_PORTSC1_WKCN (1 << 20)
-#define USB_PORTSC1_PTC(x) (((x) & 0xf) << 16)
-#define USB_PORTSC1_PP (1 << 12)
-#define USB_PORTSC1_LS(x) (((x) & 0x3) << 10)
-#define USB_PORTSC1_SUSP (1 << 7)
-#define USB_PORTSC1_RESUME (1 << 6)
-#define USB_PORTSC1_PE (1 << 2)
-#define USB_PORTSC1_CCS (1 << 0)
-
-#define USB_SUSP_CTRL 0x400
-#define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
-#define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
-#define USB_SUSP_CLR (1 << 5)
-#define USB_PHY_CLK_VALID (1 << 7)
-#define USB_PHY_CLK_VALID_INT_ENB (1 << 9)
-
-
-#define UTMIP_RESET (1 << 11)
-#define UTMIP_PHY_ENABLE (1 << 12)
-#define ULPI_PHY_ENABLE (1 << 13)
-#define UHSIC_RESET (1 << 14)
-
-#define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
-#define UHSIC_PHY_ENABLE (1 << 19)
-#define ULPIS2S_SLV0_RESET (1 << 20)
-#define ULPIS2S_SLV1_RESET (1 << 21)
-#define ULPIS2S_LINE_RESET (1 << 22)
-#define ULPI_PADS_RESET (1 << 23)
-#define ULPI_PADS_CLKEN_RESET (1 << 24)
-
-#define USB_PHY_VBUS_WAKEUP_ID 0x408
-#define VDAT_DET_INT_EN (1 << 16)
-#define VDAT_DET_CHG_DET (1 << 17)
-#define VDAT_DET_STS (1 << 18)
-
-#define USB1_LEGACY_CTRL 0x410
-#define USB1_NO_LEGACY_MODE (1 << 0)
-#define USB1_VBUS_SENSE_CTL_MASK (3 << 1)
-#define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1)
-#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
- (1 << 1)
-#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1)
-#define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1)
-
-#define UTMIP_PLL_CFG1 0x804
-#define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
-#define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
-
-#define UTMIP_XCVR_CFG0 0x808
-#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
-#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
-#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
-#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
-#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
-#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
-#define UTMIP_XCVR_LSBIAS_SEL (1 << 21)
-#define UTMIP_XCVR_SETUP_MSB(x) (((x) & 0x7) << 22)
-#define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25)
-
-#define UTMIP_XCVR_MAX_OFFSET 2
-#define UTMIP_XCVR_SETUP_MAX_VALUE 0x7f
-#define UTMIP_XCVR_SETUP_MIN_VALUE 0
-#define XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
-
-#define UTMIP_BIAS_CFG0 0x80c
-#define UTMIP_OTGPD (1 << 11)
-#define UTMIP_BIASPD (1 << 10)
-#define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0)
-#define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2)
-#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24)
-
-#define UTMIP_HSRX_CFG0 0x810
-#define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
-#define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
-
-#define UTMIP_HSRX_CFG1 0x814
-#define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
-
-#define UTMIP_TX_CFG0 0x820
-#define UTMIP_FS_PREABMLE_J (1 << 19)
-#define UTMIP_HS_DISCON_DISABLE (1 << 8)
-
-#define UTMIP_MISC_CFG1 0x828
-#define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
-#define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6)
-
-#define UTMIP_DEBOUNCE_CFG0 0x82c
-#define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
-
-#define UTMIP_BAT_CHRG_CFG0 0x830
-#define UTMIP_PD_CHRG (1 << 0)
-#define UTMIP_ON_SINK_EN (1 << 2)
-#define UTMIP_OP_SRC_EN (1 << 3)
-
-#define UTMIP_XCVR_CFG1 0x838
-#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
-#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
-#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
-#define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
-
-#define UTMIP_BIAS_CFG1 0x83c
-#define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
-#define UTMIP_BIAS_PDTRK_POWERDOWN (1 << 0)
-#define UTMIP_BIAS_PDTRK_POWERUP (1 << 1)
-
-#define HOSTPC1_DEVLC 0x1b4
-#define HOSTPC1_DEVLC_PHCD (1 << 22)
-#define HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29)
-#define HOSTPC1_DEVLC_PTS_MASK 7
-#define HOSTPC1_DEVLC_PTS_HSIC 4
-#define HOSTPC1_DEVLC_STS (1 << 28)
-#define HOSTPC1_DEVLC_PSPD(x) (((x) & 0x3) << 25)
-#define HOSTPC1_DEVLC_PSPD_MASK 3
-#define HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
-
-#define TEGRA_USB_USBMODE_REG_OFFSET 0x1f8
-#define TEGRA_USB_USBMODE_HOST (3 << 0)
-
-#define TEGRA_PMC_USB_AO 0xf0
-#define TEGRA_PMC_USB_AO_VBUS_WAKEUP_PD_P0 (1 << 2)
-#define TEGRA_PMC_USB_AO_ID_PD_P0 (1 << 3)
-#define TEGRA_PMC_USB_AO_PD_P2 (0xf << 8)
-
-#define ICUSB_CTRL 0x15c
-
-#define UHSIC_PLL_CFG1 0xc04
-#define UHSIC_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
-#define UHSIC_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 14)
-
-#define UHSIC_HSRX_CFG0 0xc08
-#define UHSIC_ELASTIC_UNDERRUN_LIMIT(x) (((x) & 0x1f) << 2)
-#define UHSIC_ELASTIC_OVERRUN_LIMIT(x) (((x) & 0x1f) << 8)
-#define UHSIC_IDLE_WAIT(x) (((x) & 0x1f) << 13)
-
-#define UHSIC_HSRX_CFG1 0xc0c
-#define UHSIC_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
-
-#define UHSIC_TX_CFG0 0xc10
-#define UHSIC_HS_READY_WAIT_FOR_VALID (1 << 9)
-
-#define UHSIC_MISC_CFG0 0xc14
-#define UHSIC_SUSPEND_EXIT_ON_EDGE (1 << 7)
-#define UHSIC_DETECT_SHORT_CONNECT (1 << 8)
-#define UHSIC_FORCE_XCVR_MODE (1 << 15)
-#define UHSIC_DISABLE_BUSRESET (1 << 20)
-
-#define UHSIC_MISC_CFG1 0xc18
-#define UHSIC_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 2)
-
-#define UHSIC_PADS_CFG0 0xc1c
-#define UHSIC_TX_RTUNEN 0xf000
-#define UHSIC_TX_RTUNE(x) (((x) & 0xf) << 12)
-
-#define UHSIC_PADS_CFG1 0xc20
-#define UHSIC_PD_BG (1 << 2)
-#define UHSIC_PD_TX (1 << 3)
-#define UHSIC_PD_TRK (1 << 4)
-#define UHSIC_PD_RX (1 << 5)
-#define UHSIC_PD_ZI (1 << 6)
-#define UHSIC_RX_SEL (1 << 7)
-#define UHSIC_RPD_DATA (1 << 9)
-#define UHSIC_RPD_STROBE (1 << 10)
-#define UHSIC_RPU_DATA (1 << 11)
-#define UHSIC_RPU_STROBE (1 << 12)
-
-#define UHSIC_STAT_CFG0 0xc28
-#define UHSIC_CONNECT_DETECT (1 << 0)
-
-#define PMC_UTMIP_MASTER_CONFIG 0x310
-#define UTMIP_PWR(inst) (1 << (inst))
-
-#define PMC_USB_DEBOUNCE 0xec
-#define UTMIP_LINE_DEB_CNT(x) (((x) & 0xf) << 16)
-
-#define PMC_UTMIP_UHSIC_FAKE 0x218
-#define USBON_VAL(inst) (1 << ((4*(inst))+1))
-#define USBON_VAL_P2 (1 << 9)
-#define USBON_VAL_P1 (1 << 5)
-#define USBON_VAL_P0 (1 << 1)
-#define USBOP_VAL(inst) (1 << (4*(inst)))
-#define USBOP_VAL_P2 (1 << 8)
-#define USBOP_VAL_P1 (1 << 4)
-#define USBOP_VAL_P0 (1 << 0)
-
-#define PMC_SLEEPWALK_CFG 0x200
-#define UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
-#define UTMIP_LINEVAL_WALK_EN_P2 (1 << 23)
-#define UTMIP_LINEVAL_WALK_EN_P1 (1 << 15)
-#define UTMIP_LINEVAL_WALK_EN_P0 (1 << 7)
-#define UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
-#define UTMIP_WAKE_VAL_P2(x) (((x) & 0xf) << 20)
-#define UTMIP_WAKE_VAL_P1(x) (((x) & 0xf) << 12)
-#define UTMIP_WAKE_VAL_P0(x) (((x) & 0xf) << 4)
-#define WAKE_VAL_NONE 0xc
-#define WAKE_VAL_FSJ 0x2
-#define WAKE_VAL_FSK 0x1
-#define WAKE_VAL_SE0 0x0
-#define WAKE_VAL_ANY 0xf
-
-#define PMC_SLEEP_CFG 0x1fc
-#define UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
-#define UTMIP_TCTRL_USE_PMC_P2 (1 << 19)
-#define UTMIP_TCTRL_USE_PMC_P1 (1 << 11)
-#define UTMIP_TCTRL_USE_PMC_P0 (1 << 3)
-#define UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
-#define UTMIP_RCTRL_USE_PMC_P2 (1 << 18)
-#define UTMIP_RCTRL_USE_PMC_P1 (1 << 10)
-#define UTMIP_RCTRL_USE_PMC_P0 (1 << 2)
-#define UTMIP_FSLS_USE_PMC(inst) (1 << ((8*(inst))+1))
-#define UTMIP_FSLS_USE_PMC_P2 (1 << 17)
-#define UTMIP_FSLS_USE_PMC_P1 (1 << 9)
-#define UTMIP_FSLS_USE_PMC_P0 (1 << 1)
-#define UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
-#define UTMIP_MASTER_ENABLE_P2 (1 << 16)
-#define UTMIP_MASTER_ENABLE_P1 (1 << 8)
-#define UTMIP_MASTER_ENABLE_P0 (1 << 0)
-#define UHSIC_MASTER_ENABLE_P0 (1 << 24)
-#define UHSIC_WAKE_VAL_P0(x) (((x) & 0xf) << 28)
-
-#define PMC_USB_AO 0xf0
-#define PMC_POWER_DOWN_MASK 0xffff
-#define HSIC_RESERVED_P0 (3 << 14)
-#define HSIC_STOBE_VAL_PD_P0 (1 << 13)
-#define HSIC_DATA_VAL_PD_P0 (1 << 12)
-#define USB_ID_PD(inst) (1 << ((4*(inst))+3))
-#define VBUS_WAKEUP_PD(inst) (1 << ((4*(inst))+2))
-#define USBON_VAL_PD(inst) (1 << ((4*(inst))+1))
-#define USBON_VAL_PD_P2 (1 << 9)
-#define USBON_VAL_PD_P1 (1 << 5)
-#define USBON_VAL_PD_P0 (1 << 1)
-#define USBOP_VAL_PD(inst) (1 << (4*(inst)))
-#define USBOP_VAL_PD_P2 (1 << 8)
-#define USBOP_VAL_PD_P1 (1 << 4)
-#define USBOP_VAL_PD_P0 (1 << 0)
-
-#define PMC_TRIGGERS 0x1ec
-#define UTMIP_CLR_WALK_PTR(inst) (1 << (inst))
-#define UTMIP_CLR_WALK_PTR_P2 (1 << 2)
-#define UTMIP_CLR_WALK_PTR_P1 (1 << 1)
-#define UTMIP_CLR_WALK_PTR_P0 (1 << 0)
-#define UTMIP_CAP_CFG(inst) (1 << ((inst)+4))
-#define UTMIP_CAP_CFG_P2 (1 << 6)
-#define UTMIP_CAP_CFG_P1 (1 << 5)
-#define UTMIP_CAP_CFG_P0 (1 << 4)
-#define UTMIP_CLR_WAKE_ALARM(inst) (1 << ((inst)+12))
-#define UTMIP_CLR_WAKE_ALARM_P2 (1 << 14)
-
-#define PMC_PAD_CFG (0x1f4)
-
-#define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
-#define BIAS_MASTER_PROG_VAL (1 << 1)
-
-#define PMC_SLEEPWALK_REG(inst) (0x204 + (4*(inst)))
-#define PMC_SLEEPWALK_P0 0x204
-#define PMC_SLEEPWALK_P1 0x208
-#define PMC_SLEEPWALK_P2 0x20c
-#define UTMIP_USBOP_RPD_A (1 << 0)
-#define UTMIP_USBON_RPD_A (1 << 1)
-#define UTMIP_AP_A (1 << 4)
-#define UTMIP_AN_A (1 << 5)
-#define UTMIP_HIGHZ_A (1 << 6)
-#define UTMIP_USBOP_RPD_B (1 << 8)
-#define UTMIP_USBON_RPD_B (1 << 9)
-#define UTMIP_AP_B (1 << 12)
-#define UTMIP_AN_B (1 << 13)
-#define UTMIP_HIGHZ_B (1 << 14)
-#define UTMIP_USBOP_RPD_C (1 << 16)
-#define UTMIP_USBON_RPD_C (1 << 17)
-#define UTMIP_AP_C (1 << 20)
-#define UTMIP_AN_C (1 << 21)
-#define UTMIP_HIGHZ_C (1 << 22)
-#define UTMIP_USBOP_RPD_D (1 << 24)
-#define UTMIP_USBON_RPD_D (1 << 25)
-#define UTMIP_AP_D (1 << 28)
-#define UTMIP_AN_D (1 << 29)
-#define UTMIP_HIGHZ_D (1 << 30)
-
-#define UTMIP_PMC_WAKEUP0 0x84c
-#define EVENT_INT_ENB (1 << 0)
-
-#define UTMIP_UHSIC_STATUS 0x214
-#define UTMIP_WALK_PTR_VAL(inst) (0x3 << ((inst)*2))
-#define UTMIP_USBOP_VAL(inst) (1 << ((2*(inst)) + 8))
-#define UTMIP_USBOP_VAL_P2 (1 << 12)
-#define UTMIP_USBOP_VAL_P1 (1 << 10)
-#define UTMIP_USBOP_VAL_P0 (1 << 8)
-#define UTMIP_USBON_VAL(inst) (1 << ((2*(inst)) + 9))
-#define UTMIP_USBON_VAL_P2 (1 << 13)
-#define UTMIP_USBON_VAL_P1 (1 << 11)
-#define UTMIP_USBON_VAL_P0 (1 << 9)
-#define UTMIP_WAKE_ALARM(inst) (1 << ((inst) + 16))
-#define UTMIP_WAKE_ALARM_P2 (1 << 18)
-#define UTMIP_WAKE_ALARM_P1 (1 << 17)
-#define UTMIP_WAKE_ALARM_P0 (1 << 16)
-#define UTMIP_WALK_PTR(inst) (1 << ((inst)*2))
-#define UTMIP_WALK_PTR_P2 (1 << 4)
-#define UTMIP_WALK_PTR_P1 (1 << 2)
-#define UTMIP_WALK_PTR_P0 (1 << 0)
-
-#define UTMIP_BIAS_STS0 0x840
-#define UTMIP_RCTRL_VAL(x) (((x) & 0xffff) << 0)
-#define UTMIP_TCTRL_VAL(x) (((x) & (0xffff << 16)) >> 16)
-
-#define PMC_UTMIP_TERM_PAD_CFG 0x1f8
-#define PMC_TCTRL_VAL(x) (((x) & 0x1f) << 5)
-#define PMC_RCTRL_VAL(x) (((x) & 0x1f) << 0)
-
-#define UHSIC_SLEEPWALK_REG 0x210
-#define UHSIC_DATA_RPD_D (1 << 25)
-#define UHSIC_STRB_RPD_D (1 << 24)
-#define UHSIC_DATA_RPD_C (1 << 17)
-#define UHSIC_STRB_RPD_C (1 << 16)
-#define UHSIC_DATA_RPD_B (1 << 9)
-#define UHSIC_STRB_RPD_B (1 << 8)
-#define UHSIC_DATA_RPD_A (1 << 1)
-#define UHSIC_STRB_RPD_A (1 << 0)
-
-static u32 utmip_rctrl_val, utmip_tctrl_val;
-
-#endif
-
-/* Common registers */
-#define UTMIP_MISC_CFG0 0x824
-#define UTMIP_DPDM_OBSERVE (1 << 26)
-#define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
-#define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
-#define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
-#define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
-#define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
-#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
-#define FORCE_PULLDN_DM (1 << 8)
-#define FORCE_PULLDN_DP (1 << 9)
-#define COMB_TERMS (1 << 0)
-#define ALWAYS_FREE_RUNNING_TERMS (1 << 1)
-
-#define ULPIS2S_CTRL 0x418
-#define ULPIS2S_ENA (1 << 0)
-#define ULPIS2S_SUPPORT_DISCONNECT (1 << 2)
-#define ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
-#define ULPIS2S_SPARE(x) (((x) & 0xF) << 8)
-#define ULPIS2S_FORCE_ULPI_CLK_OUT (1 << 12)
-#define ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
-#define ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
-#define ULPIS2S_DISABLE_STP_PU (1 << 15)
-#define ULPIS2S_SLV0_CLAMP_XMIT (1 << 16)
-
-
-#define ULPI_TIMING_CTRL_0 0x424
-#define ULPI_CLOCK_OUT_DELAY(x) ((x) & 0x1F)
-#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
-#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
-#define ULPI_SHADOW_CLK_LOOPBACK_EN (1 << 12)
-#define ULPI_SHADOW_CLK_SEL (1 << 13)
-#define ULPI_CORE_CLK_SEL (1 << 14)
-#define ULPI_SHADOW_CLK_DELAY(x) (((x) & 0x1F) << 16)
-#define ULPI_LBK_PAD_EN (1 << 26)
-#define ULPI_LBK_PAD_E_INPUT_OR (1 << 27)
-#define ULPI_CLK_OUT_ENA (1 << 28)
-#define ULPI_CLK_PADOUT_ENA (1 << 29)
-
-#define ULPI_TIMING_CTRL_1 0x428
-#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
-#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
-#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
-#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
-#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
-#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
-
-#define UTMIP_SPARE_CFG0 0x834
-#define FUSE_SETUP_SEL (1 << 3)
-#define FUSE_ATERM_SEL (1 << 4)
-
-#define FUSE_USB_CALIB_0 0x1F0
-#define FUSE_USB_CALIB_XCVR_SETUP(x) (((x) & 0x7F) << 0)
-
-#define UHSIC_PLL_CFG0 0x800
-
-#define UHSIC_CMD_CFG0 0x824
-#define UHSIC_PRETEND_CONNECT_DETECT (1 << 5)
-
-#define UHSIC_SPARE_CFG0 0x82c
-
-/* These values (in milli second) are taken from the battery charging spec */
-#define TDP_SRC_ON_MS 100
-#define TDPSRC_CON_MS 40
-
-#define CONNECT_DETECT_TIMEOUT 25000
+#define ERR(stuff...) pr_err("usb_phy: " stuff)
+#define WARNING(stuff...) pr_warning("usb_phy: " stuff)
+#define INFO(stuff...) pr_info("usb_phy: " stuff)
#define AHB_MEM_PREFETCH_CFG3 0xe0
#define AHB_MEM_PREFETCH_CFG4 0xe4
@@ -609,2587 +43,599 @@ static u32 utmip_rctrl_val, utmip_tctrl_val;
#define AHB_MEM_PREFETCH_CFG2 0xf0
#define PREFETCH_ENB (1 << 31)
-static DEFINE_SPINLOCK(utmip_pad_lock);
-static int utmip_pad_count;
-
-struct tegra_xtal_freq {
- int freq;
- u8 enable_delay;
- u8 stable_count;
- u8 active_delay;
- u16 xtal_freq_count;
- u16 debounce;
- u8 pdtrk_count;
-};
-
-static const struct tegra_xtal_freq tegra_freq_table[] = {
- {
- .freq = 12000000,
- .enable_delay = 0x02,
- .stable_count = 0x2F,
- .active_delay = 0x04,
- .xtal_freq_count = 0x76,
- .debounce = 0x7530,
- .pdtrk_count = 5,
- },
- {
- .freq = 13000000,
- .enable_delay = 0x02,
- .stable_count = 0x33,
- .active_delay = 0x05,
- .xtal_freq_count = 0x7F,
- .debounce = 0x7EF4,
- .pdtrk_count = 5,
- },
- {
- .freq = 19200000,
- .enable_delay = 0x03,
- .stable_count = 0x4B,
- .active_delay = 0x06,
- .xtal_freq_count = 0xBB,
- .debounce = 0xBB80,
- .pdtrk_count = 7,
- },
- {
- .freq = 26000000,
- .enable_delay = 0x04,
- .stable_count = 0x66,
- .active_delay = 0x09,
- .xtal_freq_count = 0xFE,
- .debounce = 0xFDE8,
- .pdtrk_count = 9,
- },
-};
-
-static const struct tegra_xtal_freq tegra_uhsic_freq_table[] = {
- {
- .freq = 12000000,
- .enable_delay = 0x02,
- .stable_count = 0x2F,
- .active_delay = 0x0,
- .xtal_freq_count = 0x1CA,
- },
- {
- .freq = 13000000,
- .enable_delay = 0x02,
- .stable_count = 0x33,
- .active_delay = 0x0,
- .xtal_freq_count = 0x1F0,
- },
- {
- .freq = 19200000,
- .enable_delay = 0x03,
- .stable_count = 0x4B,
- .active_delay = 0x0,
- .xtal_freq_count = 0x2DD,
- },
- {
- .freq = 26000000,
- .enable_delay = 0x04,
- .stable_count = 0x66,
- .active_delay = 0x0,
- .xtal_freq_count = 0x3E0,
- },
-};
-
-static struct tegra_utmip_config utmip_default[] = {
- [0] = {
- .hssync_start_delay = 9,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup = 9,
- .xcvr_setup_offset = 0,
- .xcvr_use_fuses = 1,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
- [2] = {
- .hssync_start_delay = 9,
- .idle_wait_delay = 17,
- .elastic_limit = 16,
- .term_range_adj = 6,
- .xcvr_setup_offset = 0,
- .xcvr_use_fuses = 1,
- .xcvr_setup = 9,
- .xcvr_lsfslew = 2,
- .xcvr_lsrslew = 2,
- },
-};
-
-struct usb_phy_plat_data usb_phy_data[] = {
- { 0, 0, -1, NULL},
- { 0, 0, -1, NULL},
- { 0, 0, -1, NULL},
-};
-
-static int utmip_pad_open(struct tegra_usb_phy *phy)
+#ifdef DEBUG
+#define DBG(stuff...) pr_info("usb_phy: " stuff)
+#else
+#define DBG(stuff...) do {} while (0)
+#endif
+
+static void print_usb_plat_data_info(struct tegra_usb_phy *phy)
{
- phy->pad_clk = clk_get_sys("utmip-pad", NULL);
- if (IS_ERR(phy->pad_clk)) {
- pr_err("%s: can't get utmip pad clock\n", __func__);
- return PTR_ERR(phy->pad_clk);
- }
+ struct tegra_usb_platform_data *pdata = phy->pdata;
+ char op_mode[][50] = {
+ "TEGRA_USB_OPMODE_DEVICE",
+ "TEGRA_USB_OPMODE_HOST"
+ };
+ char phy_intf[][50] = {
+ "USB_PHY_INTF_UTMI",
+ "USB_PHY_INTF_ULPI_LINK",
+ "USB_PHY_INTF_ULPI_NULL",
+ "USB_PHY_INTF_HSIC",
+ "USB_PHY_INTF_ICUSB"
+ };
- if (phy->instance == 0) {
- phy->pad_regs = phy->regs;
+ pr_info("tegra USB phy - inst[%d] platform info:\n", phy->inst);
+ pr_info("port_otg: %s\n", pdata->port_otg ? "yes" : "no");
+ pr_info("has_hostpc: %s\n", pdata->has_hostpc ? "yes" : "no");
+ pr_info("phy_interface: %s\n", phy_intf[pdata->phy_intf]);
+ pr_info("op_mode: %s\n", op_mode[pdata->op_mode]);
+ if (pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
+ pr_info("vbus_pmu_irq: %d\n", pdata->u_data.dev.vbus_pmu_irq);
+ pr_info("vbus_gpio: %d\n", pdata->u_data.dev.vbus_gpio);
+ pr_info("charging: %s\n", pdata->u_data.dev.charging_supported ?
+ "enabled" : "disabled");
+ pr_info("remote_wakeup: %s\n", pdata->u_data.dev.remote_wakeup_supported
+ ? "enabled" : "disabled");
} else {
- phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE);
- if (!phy->pad_regs) {
- pr_err("%s: can't remap usb registers\n", __func__);
- clk_put(phy->pad_clk);
- return -ENOMEM;
- }
+ pr_info("vbus_gpio: %d\n", pdata->u_data.host.vbus_gpio);
+ pr_info("vbus_reg: %s\n", pdata->u_data.host.vbus_reg ?
+ pdata->u_data.host.vbus_reg : "NULL");
+ pr_info("hot_plug: %s\n", pdata->u_data.host.hot_plug ?
+ "enabled" : "disabled");
+ pr_info("remote_wakeup: %s\n", pdata->u_data.host.remote_wakeup_supported
+ ? "enabled" : "disabled");
}
- return 0;
}
-static void utmip_pad_close(struct tegra_usb_phy *phy)
+static void usb_host_vbus_enable(struct tegra_usb_phy *phy, bool enable)
{
- if (phy->instance != 0)
- iounmap(phy->pad_regs);
- clk_put(phy->pad_clk);
-}
-
-static int utmip_pad_power_on(struct tegra_usb_phy *phy)
-{
- unsigned long val, flags;
- void __iomem *base = phy->pad_regs;
-
- clk_enable(phy->pad_clk);
-
- spin_lock_irqsave(&utmip_pad_lock, flags);
-
- utmip_pad_count++;
- val = readl(base + UTMIP_BIAS_CFG0);
- val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
- UTMIP_HSDISCON_LEVEL_MSB;
-#endif
- writel(val, base + UTMIP_BIAS_CFG0);
-
- spin_unlock_irqrestore(&utmip_pad_lock, flags);
-
- clk_disable(phy->pad_clk);
-
- return 0;
-}
-
-static int utmip_pad_power_off(struct tegra_usb_phy *phy, bool is_dpd)
-{
- unsigned long val, flags;
- void __iomem *base = phy->pad_regs;
-
- if (!utmip_pad_count) {
- pr_err("%s: utmip pad already powered off\n", __func__);
- return -EINVAL;
- }
-
- clk_enable(phy->pad_clk);
-
- spin_lock_irqsave(&utmip_pad_lock, flags);
-
- if (--utmip_pad_count == 0 && is_dpd) {
- val = readl(base + UTMIP_BIAS_CFG0);
- val |= UTMIP_OTGPD | UTMIP_BIASPD;
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
- UTMIP_HSDISCON_LEVEL_MSB);
-#endif
- writel(val, base + UTMIP_BIAS_CFG0);
+ if (phy->vbus_reg) {
+ if (enable)
+ regulator_enable(phy->vbus_reg);
+ else
+ regulator_disable(phy->vbus_reg);
+ } else {
+ int gpio = phy->pdata->u_data.host.vbus_gpio;
+ if (gpio == -1)
+ return;
+ gpio_set_value_cansleep(gpio, enable ? 1 : 0);
}
-
- spin_unlock_irqrestore(&utmip_pad_lock, flags);
-
- clk_disable(phy->pad_clk);
-
- return 0;
}
-static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
+int usb_phy_reg_status_wait(void __iomem *reg, u32 mask,
+ u32 result, u32 timeout)
{
- unsigned long timeout = 2500;
do {
if ((readl(reg) & mask) == result)
return 0;
udelay(1);
timeout--;
} while (timeout);
- return -1;
-}
-static int utmi_wait_register_timeout(void __iomem *reg, u32 mask, u32 result,
- unsigned long timeout)
-{
- do {
- if ((readl(reg) & mask) == result)
- return 0;
- udelay(1);
- timeout--;
- } while (timeout);
return -1;
}
-static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
-{
- unsigned long val;
- void __iomem *base = phy->regs;
-
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- if (phy->instance == 0) {
- val = readl(base + USB_SUSP_CTRL);
- val |= USB_SUSP_SET;
- writel(val, base + USB_SUSP_CTRL);
-
- udelay(10);
-
- val = readl(base + USB_SUSP_CTRL);
- val &= ~USB_SUSP_SET;
- writel(val, base + USB_SUSP_CTRL);
- }
-
- if (phy->instance == 2) {
- val = readl(base + USB_PORTSC1);
- val |= USB_PORTSC1_PHCD;
- writel(val, base + USB_PORTSC1);
- }
-#else
- val = readl(base + HOSTPC1_DEVLC);
- val |= HOSTPC1_DEVLC_PHCD;
- writel(val, base + HOSTPC1_DEVLC);
-#endif
- if (phy->hotplug) {
- val = readl(base + USB_SUSP_CTRL);
- val |= USB_PHY_CLK_VALID_INT_ENB;
- writel(val, base + USB_SUSP_CTRL);
- } else {
- val = readl(base + USB_SUSP_CTRL);
- val |= UTMIP_RESET;
- writel(val, base + USB_SUSP_CTRL);
- }
-
- if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
- pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
-}
-
-static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
-{
- unsigned long val;
- void __iomem *base = phy->regs;
-
- if (phy->instance == 0) {
- val = readl(base + USB_SUSP_CTRL);
- val |= USB_SUSP_CLR;
- writel(val, base + USB_SUSP_CTRL);
-
- udelay(10);
-
- val = readl(base + USB_SUSP_CTRL);
- val &= ~USB_SUSP_CLR;
- writel(val, base + USB_SUSP_CTRL);
- }
-
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- if (phy->instance == 2) {
- val = readl(base + USB_PORTSC1);
- val &= ~USB_PORTSC1_PHCD;
- writel(val, base + USB_PORTSC1);
- }
-#endif
-
- if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
- USB_PHY_CLK_VALID) < 0)
- pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
-}
-
-static void vbus_enable(struct tegra_usb_phy *phy)
+int tegra_usb_phy_init_ops(struct tegra_usb_phy *phy)
{
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- int gpio_status;
- int gpio = usb_phy_data[phy->instance].vbus_gpio;
-
- if (gpio == -1)
- return;
-
- gpio_status = gpio_request(gpio,"VBUS_USB");
- if (gpio_status < 0) {
- printk("VBUS_USB request GPIO FAILED\n");
- WARN_ON(1);
- return;
- }
- if (gpio < TEGRA_NR_GPIOS) tegra_gpio_enable(gpio);
- gpio_status = gpio_direction_output(gpio, 1);
- if (gpio_status < 0) {
- printk("VBUS_USB request GPIO DIRECTION FAILED \n");
- WARN_ON(1);
- return;
- }
- gpio_set_value_cansleep(gpio, 1);
-#else
- if (phy->reg_vbus)
- regulator_enable(phy->reg_vbus);
-#endif
-}
+ int err = 0;
-static void vbus_disable(struct tegra_usb_phy *phy)
-{
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- int gpio = usb_phy_data[phy->instance].vbus_gpio;
-
- if (gpio == -1)
- return;
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
- gpio_set_value_cansleep(gpio, 0);
- gpio_free(gpio);
-#else
- if (phy->reg_vbus)
- regulator_disable(phy->reg_vbus);
-#endif
-}
-
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
-static void utmip_phy_enable_trking_data(struct tegra_usb_phy *phy)
-{
- void __iomem *base = phy->pad_regs;
- void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
- static bool init_done = false;
- u32 val;
-
- /* Should be done only once after system boot */
- if (init_done)
- return;
-
- clk_enable(phy->pad_clk);
- /* Bias pad MASTER_ENABLE=1 */
- val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
- val |= BIAS_MASTER_PROG_VAL;
- writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
-
- /* Setting the tracking length time */
- val = readl(base + UTMIP_BIAS_CFG1);
- val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
- val |= UTMIP_BIAS_PDTRK_COUNT(5);
- writel(val, base + UTMIP_BIAS_CFG1);
-
- /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
- val = readl(base + UTMIP_BIAS_CFG1);
- val &= ~ UTMIP_BIAS_PDTRK_POWERDOWN;
- writel(val, base + UTMIP_BIAS_CFG1);
-
- val = readl(base + UTMIP_BIAS_CFG1);
- val |= UTMIP_BIAS_PDTRK_POWERUP;
- writel(val, base + UTMIP_BIAS_CFG1);
-
- /* Wait for 25usec */
- udelay(25);
-
- /* Bias pad MASTER_ENABLE=0 */
- val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
- val &= ~BIAS_MASTER_PROG_VAL;
- writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
-
- /* Wait for 1usec */
- udelay(1);
-
- /* Bias pad MASTER_ENABLE=1 */
- val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
- val |= BIAS_MASTER_PROG_VAL;
- writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
-
- /* Read RCTRL and TCTRL from UTMIP space */
- val = readl(base + UTMIP_BIAS_STS0);
- utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
- utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
-
- /* PD_TRK=1 */
- val = readl(base + UTMIP_BIAS_CFG1);
- val |= UTMIP_BIAS_PDTRK_POWERDOWN;
- writel(val, base + UTMIP_BIAS_CFG1);
-
- /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
- val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
- val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
- writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
- clk_disable(phy->pad_clk);
- init_done = true;
-}
-
-static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
-{
- unsigned long val;
- void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
- unsigned int inst = phy->instance;
-
- /* power down UTMIP interfaces */
- val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
- val |= UTMIP_PWR(inst);
- writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
-
- /* setup sleep walk usb controller */
- val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
- UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
- UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
- UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
- writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
-
- /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
- val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
- val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
- writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
-
- /* Turn over pad configuration to PMC */
- val = readl(pmc_base + PMC_SLEEP_CFG);
- val &= ~UTMIP_WAKE_VAL(inst, ~0);
- val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
- UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
- UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
- writel(val, pmc_base + PMC_SLEEP_CFG);
-}
+ if (phy->pdata->has_hostpc)
+ err = tegra3_usb_phy_init_ops(phy);
+ else
+ err = tegra2_usb_phy_init_ops(phy);
-static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
-{
- unsigned long val;
- void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
- unsigned int inst = phy->instance;
-
- /* Disable PMC master mode by clearing MASTER_EN */
- val = readl(pmc_base + PMC_SLEEP_CFG);
- val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
- UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
- writel(val, pmc_base + PMC_SLEEP_CFG);
- mdelay(1);
+ return err;
}
-static void uhsic_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
+static irqreturn_t usb_phy_dev_vbus_pmu_irq_thr(int irq, void *pdata)
{
- unsigned long val;
- void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
-
- /* turn on pad detectors for HSIC*/
- val = readl(pmc_base + PMC_USB_AO);
- val |= (HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
- writel(val, pmc_base + PMC_USB_AO);
-
- /* enable pull downs on HSIC PMC */
- val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
- UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
- UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
- writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
-
- /* Turn over pad configuration to PMC */
- val = readl(pmc_base + PMC_SLEEP_CFG);
- val &= ~UHSIC_WAKE_VAL_P0(~0);
- val |= UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) | UHSIC_MASTER_ENABLE_P0;
- writel(val, pmc_base + PMC_SLEEP_CFG);
-}
+ /* FIXME : Need to enable pmu vbus handling */
-static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
-{
- unsigned long val;
- void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
-
- /* turn on pad detectors for HSIC*/
- val = readl(pmc_base + PMC_USB_AO);
- val &= ~(HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
- writel(val, pmc_base + PMC_USB_AO);
-
- /* Disable PMC master mode by clearing MASTER_EN */
- val = readl(pmc_base + PMC_SLEEP_CFG);
- val &= ~(UHSIC_MASTER_ENABLE_P0);
- writel(val, pmc_base + PMC_SLEEP_CFG);
- mdelay(1);
+ return IRQ_NONE;
}
-#endif
-static unsigned int tegra_phy_xcvr_setup_value(struct tegra_utmip_config *cfg)
+static void tegra_usb_phy_release_clocks(struct tegra_usb_phy *phy)
{
- signed long val;
-
- if (cfg->xcvr_use_fuses) {
- val = FUSE_USB_CALIB_XCVR_SETUP(
- tegra_fuse_readl(FUSE_USB_CALIB_0));
- if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
- val = val + cfg->xcvr_setup_offset;
-
- if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
- val = UTMIP_XCVR_SETUP_MAX_VALUE;
- pr_info("%s: reset XCVR_SETUP to max value\n",
- __func__);
- } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
- val = UTMIP_XCVR_SETUP_MIN_VALUE;
- pr_info("%s: reset XCVR_SETUP to min value\n",
- __func__);
- }
- } else {
- val = cfg->xcvr_setup;
- }
-
- return (unsigned int)val;
+ clk_put(phy->emc_clk);
+ clk_put(phy->sys_clk);
+ clk_put(phy->ctrlr_clk);
+ clk_disable(phy->pllu_clk);
+ clk_put(phy->pllu_clk);
}
-static int utmi_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
+static int tegra_usb_phy_get_clocks(struct tegra_usb_phy *phy)
{
- unsigned long val;
- void __iomem *base = phy->regs;
- unsigned int xcvr_setup_value;
- struct tegra_utmip_config *config = phy->config;
-
- val = readl(base + USB_SUSP_CTRL);
- val |= UTMIP_RESET;
- writel(val, base + USB_SUSP_CTRL);
-
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- if (phy->instance == 0) {
- val = readl(base + USB1_LEGACY_CTRL);
- val |= USB1_NO_LEGACY_MODE;
- writel(val, base + USB1_LEGACY_CTRL);
- }
-#endif
-
- val = readl(base + UTMIP_TX_CFG0);
- val |= UTMIP_FS_PREABMLE_J;
- writel(val, base + UTMIP_TX_CFG0);
-
- val = readl(base + UTMIP_HSRX_CFG0);
- val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
- val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
- val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
- writel(val, base + UTMIP_HSRX_CFG0);
-
- val = readl(base + UTMIP_HSRX_CFG1);
- val &= ~UTMIP_HS_SYNC_START_DLY(~0);
- val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
- writel(val, base + UTMIP_HSRX_CFG1);
-
- val = readl(base + UTMIP_DEBOUNCE_CFG0);
- val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
- val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
- writel(val, base + UTMIP_DEBOUNCE_CFG0);
-
- val = readl(base + UTMIP_MISC_CFG0);
- val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
- writel(val, base + UTMIP_MISC_CFG0);
-
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- val = readl(base + UTMIP_MISC_CFG1);
- val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
- val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
- UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
- writel(val, base + UTMIP_MISC_CFG1);
-
- val = readl(base + UTMIP_PLL_CFG1);
- val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
- val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
- UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
- writel(val, base + UTMIP_PLL_CFG1);
-#endif
+ int err = 0;
- if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
- val = readl(base + USB_SUSP_CTRL);
- val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
- writel(val, base + USB_SUSP_CTRL);
+ phy->pllu_clk = clk_get_sys(NULL, "pll_u");
+ if (IS_ERR(phy->pllu_clk)) {
+ ERR("inst:[%d] Can't get pllu_clk clock\n", phy->inst);
+ err = PTR_ERR(phy->pllu_clk);
+ goto fail_pll;
}
+ clk_enable(phy->pllu_clk);
- utmip_pad_power_on(phy);
-
- xcvr_setup_value = phy->xcvr_setup_value;
-
- val = readl(base + UTMIP_XCVR_CFG0);
- val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
- UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
- UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
- UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
- val |= UTMIP_XCVR_SETUP(xcvr_setup_value);
- val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(xcvr_setup_value));
- val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
- val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
-#endif
- writel(val, base + UTMIP_XCVR_CFG0);
-
- val = readl(base + UTMIP_XCVR_CFG1);
- val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
- UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
- val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
- writel(val, base + UTMIP_XCVR_CFG1);
-
- val = readl(base + UTMIP_BAT_CHRG_CFG0);
- if (phy->mode == TEGRA_USB_PHY_MODE_HOST)
- val |= UTMIP_PD_CHRG;
- else
- val &= ~UTMIP_PD_CHRG;
- writel(val, base + UTMIP_BAT_CHRG_CFG0);
-
- val = readl(base + UTMIP_BIAS_CFG1);
- val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
- val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
- writel(val, base + UTMIP_BIAS_CFG1);
-
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- val = readl(base + UTMIP_SPARE_CFG0);
- val &= ~FUSE_SETUP_SEL;
- writel(val, base + UTMIP_SPARE_CFG0);
-
- if (phy->instance == 2) {
- val = readl(base + UTMIP_SPARE_CFG0);
- val |= FUSE_SETUP_SEL;
- writel(val, base + UTMIP_SPARE_CFG0);
-
- val = readl(base + USB_SUSP_CTRL);
- val |= UTMIP_PHY_ENABLE;
- writel(val, base + USB_SUSP_CTRL);
+ phy->ctrlr_clk = clk_get(&phy->pdev->dev, NULL);
+ if (IS_ERR(phy->ctrlr_clk)) {
+ dev_err(&phy->pdev->dev, "Can't get controller clock\n");
+ err = PTR_ERR(phy->ctrlr_clk);
+ goto fail_ctrlr_clk;
}
-#else
- val = readl(base + UTMIP_SPARE_CFG0);
- val &= ~FUSE_SETUP_SEL;
- val |= FUSE_ATERM_SEL;
- writel(val, base + UTMIP_SPARE_CFG0);
-
- val = readl(base + USB_SUSP_CTRL);
- val |= UTMIP_PHY_ENABLE;
- writel(val, base + USB_SUSP_CTRL);
-#endif
-
- val = readl(base + USB_SUSP_CTRL);
- val &= ~UTMIP_RESET;
- writel(val, base + USB_SUSP_CTRL);
-
- if (phy->instance == 0) {
- val = readl(base + USB1_LEGACY_CTRL);
- val &= ~USB1_VBUS_SENSE_CTL_MASK;
- val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
- writel(val, base + USB1_LEGACY_CTRL);
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- val = readl(base + USB_SUSP_CTRL);
- val &= ~USB_SUSP_SET;
- writel(val, base + USB_SUSP_CTRL);
-#endif
- }
-
- utmi_phy_clk_enable(phy);
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- if (phy->instance == 2) {
- val = readl(base + USB_PORTSC1);
- val &= ~USB_PORTSC1_PTS(~0);
- writel(val, base + USB_PORTSC1);
- }
-#else
- if (phy->instance == 0)
- utmip_phy_enable_trking_data(phy);
-
- if(phy->instance == 2) {
- writel(0, base + ICUSB_CTRL);
+ phy->sys_clk = clk_get(&phy->pdev->dev, "sclk");
+ if (IS_ERR(phy->sys_clk)) {
+ dev_err(&phy->pdev->dev, "Can't get sclk clock\n");
+ err = PTR_ERR(phy->sys_clk);
+ goto fail_sclk;
}
+ clk_set_rate(phy->sys_clk, 80000000);
- if (phy->mode == TEGRA_USB_PHY_MODE_HOST) {
- val = readl(base + TEGRA_USB_USBMODE_REG_OFFSET);
- writel((val | TEGRA_USB_USBMODE_HOST),
- (base + TEGRA_USB_USBMODE_REG_OFFSET));
+ phy->emc_clk = clk_get(&phy->pdev->dev, "emc");
+ if (IS_ERR(phy->emc_clk)) {
+ dev_err(&phy->pdev->dev, "Can't get emc clock\n");
+ err = PTR_ERR(phy->emc_clk);
+ goto fail_emc;
}
- val = readl(base + HOSTPC1_DEVLC);
- val &= ~HOSTPC1_DEVLC_PTS(~0);
- val |= HOSTPC1_DEVLC_STS;
- writel(val, base + HOSTPC1_DEVLC);
-
- if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE)
- utmip_powerup_pmc_wake_detect(phy);
-#endif
- return 0;
-}
-
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
-static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
-{
- unsigned long val, pmc_pad_cfg_val;
- void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
- unsigned int inst = phy->instance;
- void __iomem *base = phy->regs;
- bool port_connected;
- enum tegra_usb_phy_port_speed port_speed;
-
- /* check for port connect status */
- val = readl(base + USB_PORTSC1);
- port_connected = val & USB_PORTSC1_CCS;
-
- if (!port_connected)
- return;
-
- port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
- HOSTPC1_DEVLC_PSPD_MASK;
- /*Set PMC MASTER bits to do the following
- * a. Take over the UTMI drivers
- * b. set up such that it will take over resume
- * if remote wakeup is detected
- * Prepare PMC to take over suspend-wake detect-drive resume until USB
- * controller ready
- */
-
- /* disable master enable in PMC */
- val = readl(pmc_base + PMC_SLEEP_CFG);
- val &= ~UTMIP_MASTER_ENABLE(inst);
- writel(val, pmc_base + PMC_SLEEP_CFG);
-
- /* UTMIP_PWR_PX=1 for power savings mode */
- val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
- val |= UTMIP_PWR(inst);
- writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
-
- /* config debouncer */
- val = readl(pmc_base + PMC_USB_DEBOUNCE);
- val &= ~UTMIP_LINE_DEB_CNT(~0);
- val |= UTMIP_LINE_DEB_CNT(1);
- writel(val, pmc_base + PMC_USB_DEBOUNCE);
-
- /* Make sure nothing is happening on the line with respect to PMC */
- val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
- val &= ~USBOP_VAL(inst);
- val &= ~USBON_VAL(inst);
- writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
-
- /* Make sure wake value for line is none */
- val = readl(pmc_base + PMC_SLEEPWALK_CFG);
- val &= ~UTMIP_LINEVAL_WALK_EN(inst);
- writel(val, pmc_base + PMC_SLEEPWALK_CFG);
- val = readl(pmc_base + PMC_SLEEP_CFG);
- val &= ~UTMIP_WAKE_VAL(inst, ~0);
- val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
- writel(val, pmc_base + PMC_SLEEP_CFG);
-
- /* turn off pad detectors */
- val = readl(pmc_base + PMC_USB_AO);
- val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
- writel(val, pmc_base + PMC_USB_AO);
-
- /* Remove fake values and make synchronizers work a bit */
- val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
- val &= ~USBOP_VAL(inst);
- val &= ~USBON_VAL(inst);
- writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
-
- /* Enable which type of event can trigger a walk,
- in this case usb_line_wake */
- val = readl(pmc_base + PMC_SLEEPWALK_CFG);
- val |= UTMIP_LINEVAL_WALK_EN(inst);
- writel(val, pmc_base + PMC_SLEEPWALK_CFG);
-
- /* Enable which type of event can trigger a walk,
- * in this case usb_line_wake */
- val = readl(pmc_base + PMC_SLEEPWALK_CFG);
- val |= UTMIP_LINEVAL_WALK_EN(inst);
- writel(val, pmc_base + PMC_SLEEPWALK_CFG);
-
- /* Clear the walk pointers and wake alarm */
- val = readl(pmc_base + PMC_TRIGGERS);
- val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
- writel(val, pmc_base + PMC_TRIGGERS);
-
-
- /* Capture FS/LS pad configurations */
- pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
- val = readl(pmc_base + PMC_TRIGGERS);
- val |= UTMIP_CAP_CFG(inst);
- writel(val, pmc_base + PMC_TRIGGERS);
- udelay(1);
- pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
-
- /* BIAS MASTER_ENABLE=0 */
- val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
- val &= ~BIAS_MASTER_PROG_VAL;
- writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
-
- /* program walk sequence, maintain a J, followed by a driven K
- * to signal a resume once an wake event is detected */
- val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
- val &= ~UTMIP_AP_A;
- val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A| UTMIP_AN_A | UTMIP_HIGHZ_A |
- UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
- UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
- UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
- writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
-
- if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) {
- val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
- val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
- UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
- writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
- } else {
- val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
- val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
- UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
- writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
- }
+ if(phy->pdata->has_hostpc)
+ clk_set_rate(phy->emc_clk, 100000000);
+ else
+ clk_set_rate(phy->emc_clk, 300000000);
- /* turn on pad detectors */
- val = readl(pmc_base + PMC_USB_AO);
- val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
- writel(val, pmc_base + PMC_USB_AO);
+ return err;
- /* Add small delay before usb detectors provide stable line values */
- mdelay(1);
+fail_emc:
+ clk_put(phy->sys_clk);
- /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
- val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
- val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
- writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
+fail_sclk:
+ clk_put(phy->ctrlr_clk);
- phy->remote_wakeup = false;
+fail_ctrlr_clk:
+ clk_disable(phy->pllu_clk);
+ clk_put(phy->pllu_clk);
- /* Turn over pad configuration to PMC for line wake events*/
- val = readl(pmc_base + PMC_SLEEP_CFG);
- val &= ~UTMIP_WAKE_VAL(inst, ~0);
- val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
- val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
- val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
- writel(val, pmc_base + PMC_SLEEP_CFG);
+fail_pll:
- val = readl(base + UTMIP_PMC_WAKEUP0);
- val |= EVENT_INT_ENB;
- writel(val, base + UTMIP_PMC_WAKEUP0);
+ return err;
}
-#endif
-static int utmi_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
+struct tegra_usb_phy *tegra_usb_phy_open(struct platform_device *pdev)
{
- unsigned long val;
- void __iomem *base = phy->regs;
-
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- if (phy->mode == TEGRA_USB_PHY_MODE_HOST)
- utmip_setup_pmc_wake_detect(phy);
- else
- utmip_powerdown_pmc_wake_detect(phy);
-#endif
- if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
- val = readl(base + USB_SUSP_CTRL);
- val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
- val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
- writel(val, base + USB_SUSP_CTRL);
- }
+ struct tegra_usb_phy *phy;
+ struct tegra_usb_platform_data *pdata;
+ struct resource *res;
+ int err;
- if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
- val = readl(base + UTMIP_BAT_CHRG_CFG0);
- val |= UTMIP_PD_CHRG;
- writel(val, base + UTMIP_BAT_CHRG_CFG0);
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, pdev->id);
+ pdata = dev_get_platdata(&pdev->dev);
+ if (!pdata) {
+ dev_err(&pdev->dev, "inst:[%d] Platform data missing\n",
+ pdev->id);
+ return ERR_PTR(-EINVAL);
}
- if (phy->instance != 2) {
- val = readl(base + UTMIP_XCVR_CFG0);
- val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
- UTMIP_FORCE_PDZI_POWERDOWN);
- writel(val, base + UTMIP_XCVR_CFG0);
+ phy = kzalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL);
+ if (!phy) {
+ ERR("inst:[%d] malloc usb phy failed\n", pdev->id);
+ return ERR_PTR(-ENOMEM);
}
- val = readl(base + UTMIP_XCVR_CFG1);
- val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
- UTMIP_FORCE_PDDR_POWERDOWN;
- writel(val, base + UTMIP_XCVR_CFG1);
-
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- val = readl(base + UTMIP_BIAS_CFG1);
- val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
- writel(val, base + UTMIP_BIAS_CFG1);
-#endif
- if (phy->hotplug) {
- val = readl(base + USB_PORTSC1);
- val |= USB_PORTSC1_WKCN;
- writel(val, base + USB_PORTSC1);
- }
- if (phy->instance != 0) {
- val = readl(base + UTMIP_BIAS_CFG0);
- val |= UTMIP_OTGPD;
- writel(val, base + UTMIP_BIAS_CFG0);
+ phy->pdata = kzalloc(sizeof(struct tegra_usb_platform_data), GFP_KERNEL);
+ if (!phy->pdata) {
+ ERR("inst:[%d] malloc usb phy pdata failed\n", pdev->id);
+ kfree(phy);
+ return ERR_PTR(-ENOMEM);
}
- utmi_phy_clk_disable(phy);
-
- utmip_pad_power_off(phy, true);
- return 0;
-}
+ memcpy(phy->pdata, pdata, sizeof(struct tegra_usb_platform_data));
+ phy->pdev = pdev;
+ phy->inst = pdev->id;
-static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
-{
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- unsigned long val;
- void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
- unsigned int inst = phy->instance;
- void __iomem *base = phy->regs;
-
- val = readl(pmc_base + PMC_SLEEP_CFG);
- val &= ~UTMIP_WAKE_VAL(inst, 0x0);
- val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
- writel(val, pmc_base + PMC_SLEEP_CFG);
-
- val = readl(pmc_base + PMC_TRIGGERS);
- val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
- writel(val, pmc_base + PMC_TRIGGERS);
-
- val = readl(base + UTMIP_PMC_WAKEUP0);
- val &= ~EVENT_INT_ENB;
- writel(val, base + UTMIP_PMC_WAKEUP0);
-
- /* Disable PMC master mode by clearing MASTER_EN */
- val = readl(pmc_base + PMC_SLEEP_CFG);
- val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
- UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
- writel(val, pmc_base + PMC_SLEEP_CFG);
-
- val = readl(pmc_base + PMC_TRIGGERS);
- val &= ~UTMIP_CAP_CFG(inst);
- writel(val, pmc_base + PMC_TRIGGERS);
-
- /* turn off pad detectors */
- val = readl(pmc_base + PMC_USB_AO);
- val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
- writel(val, pmc_base + PMC_USB_AO);
-
- phy->remote_wakeup = false;
-#endif
-}
+ print_usb_plat_data_info(phy);
-static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy,
- enum tegra_usb_phy_port_speed port_speed)
-{
- unsigned long val;
- void __iomem *base = phy->regs;
-
- /* (2LS WAR)is not required for LS and FS devices and is only for HS */
- if (port_speed != TEGRA_USB_PHY_PORT_SPEED_HIGH) {
- /* do not enable the OBS bus */
- val = readl(base + UTMIP_MISC_CFG0);
- val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
- writel(val, base + UTMIP_MISC_CFG0);
- return;
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ ERR("inst:[%d] failed to get I/O memory\n", phy->inst);
+ err = -ENXIO;
+ goto fail_io;
}
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- /* Force DP/DM pulldown active for Host mode */
- val = readl(base + UTMIP_MISC_CFG0);
- val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
- COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
- writel(val, base + UTMIP_MISC_CFG0);
-#endif
- val = readl(base + UTMIP_MISC_CFG0);
- val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
- if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
- val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
- else
- val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
- writel(val, base + UTMIP_MISC_CFG0);
- udelay(1);
-
- val = readl(base + UTMIP_MISC_CFG0);
- val |= UTMIP_DPDM_OBSERVE;
- writel(val, base + UTMIP_MISC_CFG0);
- udelay(10);
-}
-static void utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
-{
- unsigned long val;
- void __iomem *base = phy->regs;
-
- /* check if OBS bus is already enabled */
- val = readl(base + UTMIP_MISC_CFG0);
- if (val & UTMIP_DPDM_OBSERVE) {
- /* Change the UTMIP OBS bus to drive SE0 */
- val = readl(base + UTMIP_MISC_CFG0);
- val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
- val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
- writel(val, base + UTMIP_MISC_CFG0);
-
- /* Wait for 3us(2 LS bit times) */
- udelay (3);
-
- /* Release UTMIP OBS bus */
- val = readl(base + UTMIP_MISC_CFG0);
- val &= ~UTMIP_DPDM_OBSERVE;
- writel(val, base + UTMIP_MISC_CFG0);
-
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- /* Release DP/DM pulldown for Host mode */
- val = readl(base + UTMIP_MISC_CFG0);
- val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
- COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
- writel(val, base + UTMIP_MISC_CFG0);
-#endif
+ phy->regs = ioremap(res->start, resource_size(res));
+ if (!phy->regs) {
+ ERR("inst:[%d] Failed to remap I/O memory\n", phy->inst);
+ err = -ENOMEM;
+ goto fail_io;
}
-}
-
-static int utmi_phy_preresume(struct tegra_usb_phy *phy, bool remote_wakeup)
-{
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- unsigned long val;
- void __iomem *base = phy->regs;
- enum tegra_usb_phy_port_speed port_speed;
-
- val = readl(base + UTMIP_TX_CFG0);
- val |= UTMIP_HS_DISCON_DISABLE;
- writel(val, base + UTMIP_TX_CFG0);
-
- port_speed = (readl(base + USB_PORTSC1) >> 26) & 0x3;
- if (remote_wakeup && (port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)) {
- val = readl(base + USB_USBCMD);
- val &= ~USB_USBCMD_RS;
- writel(val, base + USB_USBCMD);
- if (utmi_wait_register(base + USB_USBSTS,
- USB_USBSTS_HCH, USB_USBSTS_HCH) < 0) {
- pr_err("%s: timeout waiting for stopping controller\n", __func__);
- return -ETIMEDOUT;
- }
+ phy->vdd_reg = regulator_get(NULL, "avdd_usb");
+ if (IS_ERR_OR_NULL(phy->vdd_reg)) {
+ ERR("inst:[%d] couldn't get regulator avdd_usb: %ld\n",
+ phy->inst, PTR_ERR(phy->vdd_reg));
+ phy->vdd_reg = NULL;
}
- utmi_phy_enable_obs_bus(phy, port_speed);
-#else
- unsigned long val;
- void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
- unsigned int inst = phy->instance;
- void __iomem *base = phy->regs;
- enum tegra_usb_phy_port_speed port_speed;
-
- val = readl(pmc_base + PMC_SLEEP_CFG);
- if (val & UTMIP_MASTER_ENABLE(inst)) {
- if (!remote_wakeup)
- utmip_phy_disable_pmc_bus_ctrl(phy);
- } else {
- port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
- HOSTPC1_DEVLC_PSPD_MASK;
- utmi_phy_enable_obs_bus(phy, port_speed);
+ err = tegra_usb_phy_get_clocks(phy);
+ if (err) {
+ ERR("inst:[%d] Failed to init clocks\n", phy->inst);
+ goto fail_clk;
}
-#endif
-
- return 0;
-}
-static int utmi_phy_postresume(struct tegra_usb_phy *phy, bool is_dpd)
-{
- unsigned long val;
-#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
- void __iomem *base = phy->regs;
-#else
- void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
-#endif
- unsigned int inst = phy->instance;
-
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- val = readl(pmc_base + PMC_SLEEP_CFG);
- /* if PMC is not disabled by now then disable it */
- if (val & UTMIP_MASTER_ENABLE(inst)) {
- utmip_phy_disable_pmc_bus_ctrl(phy);
- }
- utmi_phy_disable_obs_bus(phy);
-#else
- val = readl(base + USB_USBCMD);
- if (val & USB_USBCMD_RS) {
- val &= ~USB_USBCMD_RS;
- writel(val, base + USB_USBCMD);
- if (utmi_wait_register(base + USB_USBSTS,
- USB_USBSTS_HCH, USB_USBSTS_HCH) < 0) {
- pr_err("%s: timeout waiting for stopping controller\n", __func__);
- return -ETIMEDOUT;
+ if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
+ if (phy->pdata->u_data.dev.vbus_pmu_irq) {
+ err = request_threaded_irq(
+ phy->pdata->u_data.dev.vbus_pmu_irq,
+ NULL, usb_phy_dev_vbus_pmu_irq_thr,
+ IRQF_SHARED, "usb_pmu_vbus_irq", phy);
+ if (err) {
+ ERR("inst:[%d] Failed to register IRQ\n",
+ phy->inst);
+ goto fail_init;
+ }
+ }
+ } else {
+ if (phy->pdata->u_data.host.vbus_reg) {
+ phy->vbus_reg = regulator_get(NULL,
+ phy->pdata->u_data.host.vbus_reg);
+ if (WARN_ON(IS_ERR_OR_NULL(phy->vbus_reg))) {
+ ERR("failed to get regulator vdd_vbus_usb: %ld,\
+ instance : %d\n", PTR_ERR(phy->vbus_reg),
+ phy->inst);
+ err = PTR_ERR(phy->vbus_reg);
+ goto fail_init;
+ }
+ } else {
+ int gpio = phy->pdata->u_data.host.vbus_gpio;
+ if (gpio != -1) {
+ if (gpio_request(gpio, "usb_host_vbus") < 0) {
+ ERR("inst:[%d] host vbus gpio \
+ req failed\n", phy->inst);
+ goto fail_init;
+ }
+ if (gpio < TEGRA_NR_GPIOS)
+ tegra_gpio_enable(gpio);
+ if (gpio_direction_output(gpio, 1) < 0) {
+ ERR("inst:[%d] host vbus gpio \
+ dir failed\n", phy->inst);
+ goto fail_init;
+ }
+ }
}
+ usb_host_vbus_enable(phy, true);
}
- writel(val, base + USB_USBCMD);
- utmi_phy_disable_obs_bus(phy);
- val = readl(base + USB_USBCMD);
- val |= USB_USBCMD_RS;
- writel(val, base + USB_USBCMD);
- val = readl(base + UTMIP_TX_CFG0);
- val &= ~UTMIP_HS_DISCON_DISABLE;
- writel(val, base + UTMIP_TX_CFG0);
-#endif
+ err = tegra_usb_phy_init_ops(phy);
+ if (err) {
+ ERR("inst:[%d] Failed to init ops\n", phy->inst);
+ goto fail_init;
+ }
- return 0;
-}
-
-static int uhsic_phy_postsuspend(struct tegra_usb_phy *phy, bool is_dpd)
-{
- struct tegra_uhsic_config *uhsic_config = phy->config;
-
- if (uhsic_config->postsuspend)
- uhsic_config->postsuspend();
-
- return 0;
-}
-
-static int uhsic_phy_preresume(struct tegra_usb_phy *phy, bool remote_wakeup)
-{
- struct tegra_uhsic_config *uhsic_config = phy->config;
-
- if (uhsic_config->preresume)
- uhsic_config->preresume();
-
- return 0;
-}
-
-static int usb_phy_set_tx_fill_tuning(struct tegra_usb_phy *phy, bool is_dpd)
-{
- unsigned long val;
- void __iomem *base = phy->regs;
+ if (phy->pdata->ops && phy->pdata->ops->open)
+ phy->pdata->ops->open();
- val = readl(base + USB_TXFILLTUNING);
- if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
- val = USB_FIFO_TXFILL_THRES(0x10);
- writel(val, base + USB_TXFILLTUNING);
+ if (phy->ops && phy->ops->open) {
+ err = phy->ops->open(phy);
+ if (err) {
+ ERR("inst:[%d] Failed to open hw ops\n", phy->inst);
+ goto fail_init;
+ }
}
- return 0;
-}
+ if (phy->vdd_reg)
+ regulator_enable(phy->vdd_reg);
-static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
- enum tegra_usb_phy_port_speed port_speed)
-{
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- unsigned long val;
- void __iomem *base = phy->regs;
+ return phy;
- val = readl(base + UTMIP_MISC_CFG0);
- val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
- if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
- val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
- else
- val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
- writel(val, base + UTMIP_MISC_CFG0);
- udelay(1);
-
- val = readl(base + UTMIP_MISC_CFG0);
- val |= UTMIP_DPDM_OBSERVE;
- writel(val, base + UTMIP_MISC_CFG0);
- udelay(10);
-#else
- unsigned long val;
- void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
- int inst = phy->instance;
+fail_init:
+ tegra_usb_phy_release_clocks(phy);
- val = readl(pmc_base + UTMIP_UHSIC_STATUS);
- /* check whether we wake up from the remote resume */
- if (UTMIP_WALK_PTR_VAL(inst) & val) {
- phy->remote_wakeup = true;
+ if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
+ if (phy->pdata->u_data.dev.vbus_pmu_irq)
+ free_irq(phy->pdata->u_data.dev.vbus_pmu_irq, phy);
} else {
- if (!((UTMIP_USBON_VAL(phy->instance) |
- UTMIP_USBOP_VAL(phy->instance)) & val)) {
- utmip_phy_disable_pmc_bus_ctrl(phy);
- }
- }
- utmi_phy_enable_obs_bus(phy, port_speed);
-#endif
-}
-
-static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
-{
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- unsigned long val;
- void __iomem *base = phy->regs;
-
- val = readl(base + UTMIP_MISC_CFG0);
- val &= ~UTMIP_DPDM_OBSERVE;
- writel(val, base + UTMIP_MISC_CFG0);
- udelay(10);
-#else
- unsigned long val;
- void __iomem *base = phy->regs;
- int wait_time_us = 3000; /* FPR should be set by this time */
-
- /* check whether we wake up from the remote resume */
- if (phy->remote_wakeup) {
- /* wait until FPR bit is set automatically on remote resume */
- do {
- val = readl(base + USB_PORTSC1);
- udelay(1);
- if (wait_time_us == 0) {
- utmip_phy_disable_pmc_bus_ctrl(phy);
- tegra_usb_phy_postresume(phy, false);
- return;
+ usb_host_vbus_enable(phy, false);
+
+ if (phy->vbus_reg)
+ regulator_put(phy->vbus_reg);
+ else {
+ int gpio = phy->pdata->u_data.host.vbus_gpio;
+ if (gpio != -1) {
+ gpio_set_value_cansleep(gpio, 0);
+ gpio_free(gpio);
}
- wait_time_us--;
- } while (!(val & USB_PORTSC1_RESUME));
- /* wait for 25 ms to port resume complete */
- msleep(25);
- /* disable PMC master control */
- utmip_phy_disable_pmc_bus_ctrl(phy);
-
- /* Clear PCI and SRI bits to avoid an interrupt upon resume */
- val = readl(base + USB_USBSTS);
- writel(val, base + USB_USBSTS);
- /* wait to avoid SOF if there is any */
- if (utmi_wait_register(base + USB_USBSTS,
- USB_USBSTS_SRI, USB_USBSTS_SRI) < 0) {
- pr_err("%s: timeout waiting for SOF\n", __func__);
}
- tegra_usb_phy_postresume(phy, false);
}
-#endif
-}
-
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-static void ulpi_set_tristate(bool enable)
-{
- int tristate = (enable)? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
-
- tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate);
- tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate);
- tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate);
-}
-#endif
-static void ulpi_phy_reset(void __iomem *base)
-{
- unsigned long val;
-
- val = readl(base + USB_SUSP_CTRL);
- val |= UHSIC_RESET;
- writel(val, base + USB_SUSP_CTRL);
-
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- val = readl(base + USB_SUSP_CTRL);
- val |= UTMIP_RESET;
- writel(val, base + USB_SUSP_CTRL);
-#endif
-}
-
-static void ulpi_set_host(void __iomem *base)
-{
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- unsigned long val;
-
- val = readl(base + TEGRA_USB_USBMODE_REG_OFFSET);
- val |= TEGRA_USB_USBMODE_HOST;
- writel(val, base + TEGRA_USB_USBMODE_REG_OFFSET);
-
- val = readl(base + HOSTPC1_DEVLC);
- val |= HOSTPC1_DEVLC_PTS(2);
- writel(val, base + HOSTPC1_DEVLC);
-#endif
-}
-
-static void ulpi_set_trimmer(void __iomem *base, u8 data, u8 sdn, u8 dir)
-{
- unsigned long val;
-
- val = ULPI_DATA_TRIMMER_SEL(data);
- val |= ULPI_STPDIRNXT_TRIMMER_SEL(sdn);
- val |= ULPI_DIR_TRIMMER_SEL(dir);
- writel(val, base + ULPI_TIMING_CTRL_1);
- udelay(10);
-
- val |= ULPI_DATA_TRIMMER_LOAD;
- val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
- val |= ULPI_DIR_TRIMMER_LOAD;
- writel(val, base + ULPI_TIMING_CTRL_1);
-}
-
-static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, bool enable)
-{
- unsigned long val;
- void __iomem *base = phy->regs;
-
- val = readl(base + ULPI_TIMING_CTRL_0);
-
- if (enable)
- val |= ULPI_OUTPUT_PINMUX_BYP;
- else
- val &= ~ULPI_OUTPUT_PINMUX_BYP;
-
- writel(val, base + ULPI_TIMING_CTRL_0);
-}
-
-static void ulpi_phy_restore_start(struct tegra_usb_phy *phy,
- enum tegra_usb_phy_port_speed port_speed)
-{
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- unsigned long val;
- void __iomem *base = phy->regs;
-
- /*Tristate ulpi interface before USB controller resume*/
- ulpi_set_tristate(true);
+fail_clk:
+ regulator_put(phy->vdd_reg);
+ iounmap(phy->regs);
+fail_io:
+ kfree(phy);
- val = readl(base + ULPI_TIMING_CTRL_0);
- val &= ~ULPI_OUTPUT_PINMUX_BYP;
- writel(val, base + ULPI_TIMING_CTRL_0);
-#endif
+ return ERR_PTR(err);
}
-static void ulpi_phy_restore_end(struct tegra_usb_phy *phy)
-{
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- unsigned long val;
- void __iomem *base = phy->regs;
-
- val = readl(base + ULPI_TIMING_CTRL_0);
- val |= ULPI_OUTPUT_PINMUX_BYP;
- writel(val, base + ULPI_TIMING_CTRL_0);
- ulpi_set_tristate(false);
-#endif
-}
-static int ulpi_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
+void tegra_usb_phy_close(struct tegra_usb_phy *phy)
{
- int ret;
- unsigned long val;
- void __iomem *base = phy->regs;
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- struct tegra_ulpi_config *config = phy->config;
-#endif
-
- if (phy->clk)
- clk_enable(phy->clk);
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
- msleep(1);
-
- if (!phy->initialized) {
- phy->initialized = 1;
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- gpio_direction_output(config->reset_gpio, 0);
- msleep(5);
- gpio_direction_output(config->reset_gpio, 1);
-#endif
+ if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
+ if (phy->pdata->u_data.dev.vbus_pmu_irq)
+ free_irq(phy->pdata->u_data.dev.vbus_pmu_irq, phy);
+ } else {
+ usb_host_vbus_enable(phy, false);
+
+ if (phy->vbus_reg)
+ regulator_put(phy->vbus_reg);
+ else {
+ int gpio = phy->pdata->u_data.host.vbus_gpio;
+ if (gpio != -1) {
+ gpio_set_value_cansleep(gpio, 0);
+ gpio_free(gpio);
+ }
+ }
}
- ulpi_phy_reset(base);
- ulpi_set_host(base);
-
- val = readl(base + ULPI_TIMING_CTRL_0);
- val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
- writel(val, base + ULPI_TIMING_CTRL_0);
-
- val = readl(base + USB_SUSP_CTRL);
- val |= ULPI_PHY_ENABLE;
- writel(val, base + USB_SUSP_CTRL);
-
- val = readl(base + USB_SUSP_CTRL);
- val |= USB_SUSP_CLR;
- writel(val, base + USB_SUSP_CTRL);
-
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
- USB_PHY_CLK_VALID) < 0)
- pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
-
- if (utmi_wait_register(base + USB_SUSP_CTRL, USB_CLKEN, USB_CLKEN) < 0)
- pr_err("%s: timeout waiting for AHB clock\n", __func__);
-#else
- udelay(100);
-#endif
-
- val = readl(base + USB_SUSP_CTRL);
- val &= ~USB_SUSP_CLR;
- writel(val, base + USB_SUSP_CTRL);
-
- val = 0;
- writel(val, base + ULPI_TIMING_CTRL_1);
+ tegra_usb_phy_release_clocks(phy);
- ulpi_set_trimmer(base, 4, 4, 4);
-
- /* Fix VbusInvalid due to floating VBUS */
- ret = otg_io_write(phy->ulpi, 0x40, 0x08);
- if (ret) {
- pr_err("%s: ulpi write failed\n", __func__);
- return ret;
- }
-
- ret = otg_io_write(phy->ulpi, 0x80, 0x0B);
- if (ret) {
- pr_err("%s: ulpi write failed\n", __func__);
- return ret;
+ if (phy->vdd_reg) {
+ regulator_disable(phy->vdd_reg);
+ regulator_put(phy->vdd_reg);
}
- val = readl(base + USB_PORTSC1);
- val |= USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN;
- writel(val, base + USB_PORTSC1);
-
- return 0;
-}
-
-static int ulpi_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
-{
- unsigned long val;
- void __iomem *base = phy->regs;
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- int ret;
-
- /* Disable VbusValid, SessEnd comparators */
- ret = otg_io_write(phy->ulpi, 0x00, 0x0D);
- if (ret)
- pr_err("%s: ulpi write 0x0D failed\n", __func__);
-
- ret = otg_io_write(phy->ulpi, 0x00, 0x10);
- if (ret)
- pr_err("%s: ulpi write 0x10 failed\n", __func__);
-
- /* Disable IdFloat comparator */
- ret = otg_io_write(phy->ulpi, 0x00, 0x19);
- if (ret)
- pr_err("%s: ulpi write 0x19 failed\n", __func__);
-
- ret = otg_io_write(phy->ulpi, 0x00, 0x1D);
- if (ret)
- pr_err("%s: ulpi write 0x1D failed\n", __func__);
-
- /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
- * Controller to immediately bring the ULPI PHY out of low power
- */
- val = readl(base + USB_PORTSC1);
- val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
- writel(val, base + USB_PORTSC1);
-
- /* Put the PHY in the low power mode */
- val = readl(base + USB_PORTSC1);
- val |= USB_PORTSC1_PHCD;
- writel(val, base + USB_PORTSC1);
-
- if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
- pr_err("%s: timeout waiting for phy to stop\n", __func__);
-#else
- val = readl(base + HOSTPC1_DEVLC);
- val &= ~(HOSTPC1_DEVLC_PHCD);
- writel(val, base + HOSTPC1_DEVLC);
-#endif
+ if (phy->ops && phy->ops->close)
+ phy->ops->close(phy);
- if(phy->clk)
- clk_disable(phy->clk);
+ if (phy->pdata->ops && phy->pdata->ops->close)
+ phy->pdata->ops->close();
- return 0;
+ kfree(phy->pdata);
+ kfree(phy);
}
-static inline void null_phy_set_tristate(bool enable)
+irqreturn_t tegra_usb_phy_irq(struct tegra_usb_phy *phy)
{
- int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
-
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate);
- tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate);
- tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate);
-#else
- tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
- tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
- tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
- tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
- tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
- tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
- tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
- tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
- tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
-
- if (enable)
- tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
-#endif
-}
+ irqreturn_t status = IRQ_HANDLED;
-static void null_phy_restore_start(struct tegra_usb_phy *phy,
- enum tegra_usb_phy_port_speed port_speed)
-{
- struct tegra_ulpi_config *config = phy->config;
+ if (phy->ops && phy->ops->irq)
+ status = phy->ops->irq(phy);
- if (config->phy_restore_start)
- config->phy_restore_start();
+ return status;
}
-
-static void null_phy_restore_end(struct tegra_usb_phy *phy)
+int tegra_usb_phy_init(struct tegra_usb_phy *phy)
{
- unsigned long val;
- void __iomem *base = phy->regs;
- struct tegra_ulpi_config *config = phy->config;
+ int status = 0;
- /* disable ULPI pinmux bypass */
- ulpi_pinmux_bypass(phy, false);
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
- /* driving linestate using GPIO */
- gpio_set_value(config->ulpi_d0_gpio, 0);
- gpio_set_value(config->ulpi_d1_gpio, 0);
-
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- /* driving DIR high */
- gpio_set_value(config->ulpi_dir_gpio, 1);
-#endif
+ if (phy->pdata->ops && phy->pdata->ops->init)
+ phy->pdata->ops->init();
- /* remove ULPI tristate */
- null_phy_set_tristate(false);
-
- if (config->phy_restore_end)
- config->phy_restore_end();
-
- if (gpio_is_valid(config->phy_restore_gpio)) {
- int phy_restore_gpio = config->phy_restore_gpio;
- int retry = 20000;
-
- while (retry) {
- /* poll phy_restore_gpio high */
- if (gpio_get_value(phy_restore_gpio))
- break;
- retry--;
- }
+ if (phy->ops && phy->ops->init)
+ status = phy->ops->init(phy);
- if (retry == 0)
- pr_info("phy_restore_gpio timeout\n");
- }
-
- /* enable ULPI CLK output pad */
- val = readl(base + ULPI_TIMING_CTRL_0);
- val |= ULPI_CLK_PADOUT_ENA;
- writel(val, base + ULPI_TIMING_CTRL_0);
-
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- udelay(5); /* wait for CLK stabilize */
-
- /* enable ULPI pinmux bypass */
- ulpi_pinmux_bypass(phy, true);
-#else
- /* enable ULPI pinmux bypass */
- ulpi_pinmux_bypass(phy, true);
- udelay(5);
-
- /* remove DIR tristate */
- tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, TEGRA_TRI_NORMAL);
-#endif
+ return status;
}
-static int null_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
+int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
{
- const struct tegra_ulpi_trimmer default_trimmer = {0, 0, 4, 4};
- unsigned long val;
- void __iomem *base = phy->regs;
- struct tegra_ulpi_config *config = phy->config;
- static bool cold_boot = true;
-
- if (!config->trimmer)
- config->trimmer = &default_trimmer;
-
- ulpi_phy_reset(base);
-
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- /* remove ULPI PADS CLKEN reset */
- val = readl(base + USB_SUSP_CTRL);
- val &= ~ULPI_PADS_CLKEN_RESET;
- writel(val, base + USB_SUSP_CTRL);
- udelay(10);
-#endif
- val = readl(base + ULPI_TIMING_CTRL_0);
- val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
- writel(val, base + ULPI_TIMING_CTRL_0);
-
- if (config->pre_phy_on && config->pre_phy_on())
- return -EAGAIN;
-
- val = readl(base + USB_SUSP_CTRL);
- val |= ULPI_PHY_ENABLE;
- writel(val, base + USB_SUSP_CTRL);
- udelay(10);
-
- /* set timming parameters */
- val = readl(base + ULPI_TIMING_CTRL_0);
- val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- val &= ~ULPI_SHADOW_CLK_SEL;
- val &= ~ULPI_LBK_PAD_EN;
-#else
- val |= ULPI_SHADOW_CLK_SEL;
- val |= ULPI_LBK_PAD_EN;
-#endif
- val |= ULPI_SHADOW_CLK_DELAY(config->trimmer->shadow_clk_delay);
- val |= ULPI_CLOCK_OUT_DELAY(config->trimmer->clock_out_delay);
- val |= ULPI_LBK_PAD_E_INPUT_OR;
- writel(val, base + ULPI_TIMING_CTRL_0);
-
- writel(0, base + ULPI_TIMING_CTRL_1);
- udelay(10);
-
- /* start internal 60MHz clock */
- val = readl(base + ULPIS2S_CTRL);
- val |= ULPIS2S_ENA;
- val |= ULPIS2S_SUPPORT_DISCONNECT;
- val |= ULPIS2S_SPARE((phy->mode == TEGRA_USB_PHY_MODE_HOST) ? 3 : 1);
- val |= ULPIS2S_PLLU_MASTER_BLASTER60;
- writel(val, base + ULPIS2S_CTRL);
-
- /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
- val = readl(base + ULPI_TIMING_CTRL_0);
- val |= ULPI_CORE_CLK_SEL;
- writel(val, base + ULPI_TIMING_CTRL_0);
- udelay(10);
-
- /* enable ULPI null phy clock - can't set the trimmers before this */
- val = readl(base + ULPI_TIMING_CTRL_0);
- val |= ULPI_CLK_OUT_ENA;
- writel(val, base + ULPI_TIMING_CTRL_0);
- udelay(10);
-
- if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
- USB_PHY_CLK_VALID)) {
- pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
- return -ETIMEDOUT;
- }
+ int err = 0;
- /* set ULPI trimmers */
- ulpi_set_trimmer(base, config->trimmer->data_trimmer,
- config->trimmer->stpdirnxt_trimmer, 1);
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
- ulpi_set_host(base);
+ if (!phy->phy_power_on)
+ return err;
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- /* remove slave0 reset */
- val = readl(base + USB_SUSP_CTRL);
- val &= ~ULPIS2S_SLV0_RESET;
- writel(val, base + USB_SUSP_CTRL);
-
- /* remove slave1 and line reset */
- val = readl(base + USB_SUSP_CTRL);
- val &= ~ULPIS2S_SLV1_RESET;
- val &= ~ULPIS2S_LINE_RESET;
-
- /* remove ULPI PADS reset */
- val &= ~ULPI_PADS_RESET;
- writel(val, base + USB_SUSP_CTRL);
-#endif
- if (cold_boot) {
- val = readl(base + ULPI_TIMING_CTRL_0);
- val |= ULPI_CLK_PADOUT_ENA;
- writel(val, base + ULPI_TIMING_CTRL_0);
- cold_boot = false;
+ if (phy->ops && phy->ops->power_off) {
+ if (phy->pdata->ops && phy->pdata->ops->pre_phy_off)
+ phy->pdata->ops->pre_phy_off();
+ err = phy->ops->power_off(phy);
+ if (phy->pdata->ops && phy->pdata->ops->post_phy_off)
+ phy->pdata->ops->post_phy_off();
}
- udelay(10);
-
- if (config->post_phy_on && config->post_phy_on())
- return -EAGAIN;
-
- return 0;
-}
-
-static int null_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
-{
- struct tegra_ulpi_config *config = phy->config;
-
- if (config->pre_phy_off && config->pre_phy_off())
- return -EAGAIN;
-
- null_phy_set_tristate(true);
+ clk_disable(phy->emc_clk);
+ clk_disable(phy->sys_clk);
+ clk_disable(phy->ctrlr_clk);
- if (config->post_phy_off && config->post_phy_off())
- return -EAGAIN;
+ phy->phy_power_on = false;
- return 0;
-}
-
-static int null_phy_pre_usbcmd_reset(struct tegra_usb_phy *phy, bool is_dpd)
-{
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- unsigned long val;
- void __iomem *base = phy->regs;
-
- val = readl(base + ULPIS2S_CTRL);
- val |= ULPIS2S_SLV0_CLAMP_XMIT;
- writel(val, base + ULPIS2S_CTRL);
-
- val = readl(base + USB_SUSP_CTRL);
- val |= ULPIS2S_SLV0_RESET;
- writel(val, base + USB_SUSP_CTRL);
- udelay(10);
-#endif
- return 0;
-}
-
-static int null_phy_post_usbcmd_reset(struct tegra_usb_phy *phy, bool is_dpd)
-{
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- unsigned long val;
- void __iomem *base = phy->regs;
-
- ulpi_set_host(base);
-
- /* remove slave0 reset */
- val = readl(base + USB_SUSP_CTRL);
- val &= ~ULPIS2S_SLV0_RESET;
- writel(val, base + USB_SUSP_CTRL);
-
- val = readl(base + ULPIS2S_CTRL);
- val &= ~ULPIS2S_SLV0_CLAMP_XMIT;
- writel(val, base + ULPIS2S_CTRL);
- udelay(10);
-#endif
- return 0;
+ return err;
}
-static int uhsic_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
+int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
{
- unsigned long val;
- void __iomem *base = phy->regs;
- struct tegra_uhsic_config *uhsic_config = phy->config;
-
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- uhsic_powerup_pmc_wake_detect(phy);
-#endif
-
- if (uhsic_config->enable_gpio != -1) {
- gpio_set_value_cansleep(uhsic_config->enable_gpio, 1);
- /* keep hsic reset asserted for 1 ms */
- udelay(1000);
- }
-
- val = readl(base + UHSIC_PADS_CFG1);
- val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
- UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
- val |= UHSIC_RX_SEL;
- writel(val, base + UHSIC_PADS_CFG1);
- udelay(2);
-
- val = readl(base + USB_SUSP_CTRL);
- val |= UHSIC_RESET;
- writel(val, base + USB_SUSP_CTRL);
- udelay(30);
-
- val = readl(base + USB_SUSP_CTRL);
- val |= UHSIC_PHY_ENABLE;
- writel(val, base + USB_SUSP_CTRL);
-
- val = readl(base + UHSIC_HSRX_CFG0);
- val |= UHSIC_IDLE_WAIT(uhsic_config->idle_wait_delay);
- val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(uhsic_config->elastic_underrun_limit);
- val |= UHSIC_ELASTIC_OVERRUN_LIMIT(uhsic_config->elastic_overrun_limit);
- writel(val, base + UHSIC_HSRX_CFG0);
-
- val = readl(base + UHSIC_HSRX_CFG1);
- val |= UHSIC_HS_SYNC_START_DLY(uhsic_config->sync_start_delay);
- writel(val, base + UHSIC_HSRX_CFG1);
-
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
- /* WAR HSIC TX */
- val = readl(base + UHSIC_TX_CFG0);
- val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
- writel(val, base + UHSIC_TX_CFG0);
-#endif
-
- val = readl(base + UHSIC_MISC_CFG0);
- val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
- /* Disable generic bus reset, to allow AP30 specific bus reset*/
- val |= UHSIC_DISABLE_BUSRESET;
-#endif
- writel(val, base + UHSIC_MISC_CFG0);
-
- val = readl(base + UHSIC_MISC_CFG1);
- val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
- writel(val, base + UHSIC_MISC_CFG1);
-
- val = readl(base + UHSIC_PLL_CFG1);
- val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
- val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
- writel(val, base + UHSIC_PLL_CFG1);
-
- val = readl(base + USB_SUSP_CTRL);
- val &= ~(UHSIC_RESET);
- writel(val, base + USB_SUSP_CTRL);
- udelay(2);
-
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- val = readl(base + USB_PORTSC1);
- val &= ~USB_PORTSC1_PTS(~0);
- writel(val, base + USB_PORTSC1);
-
-#endif
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- val = readl(base + TEGRA_USB_USBMODE_REG_OFFSET);
- val |= TEGRA_USB_USBMODE_HOST;
- writel(val, base + TEGRA_USB_USBMODE_REG_OFFSET);
-
- /* Change the USB controller PHY type to HSIC */
- val = readl(base + HOSTPC1_DEVLC);
- val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
- val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
- val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
- val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
- writel(val, base + HOSTPC1_DEVLC);
-#endif
- usb_phy_set_tx_fill_tuning(phy, is_dpd);
+ int status = 0;
- val = readl(base + USB_PORTSC1);
- val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
- writel(val, base + USB_PORTSC1);
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
- val = readl(base + UHSIC_PADS_CFG0);
- val &= ~(UHSIC_TX_RTUNEN);
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- /* set Rtune impedance to 40 ohm */
- val |= UHSIC_TX_RTUNE(0);
-#else
- /* set Rtune impedance to 50 ohm */
- val |= UHSIC_TX_RTUNE(8);
-#endif
- writel(val, base + UHSIC_PADS_CFG0);
+ if (phy->phy_power_on)
+ return status;
- if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
- USB_PHY_CLK_VALID)) {
- pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
- return -ETIMEDOUT;
- }
-
- return 0;
-}
+ clk_enable(phy->ctrlr_clk);
+ clk_enable(phy->sys_clk);
+ clk_enable(phy->emc_clk);
-static int uhsic_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
-{
- unsigned long val;
- void __iomem *base = phy->regs;
- struct tegra_uhsic_config *uhsic_config = phy->config;
-
- val = readl(base + UHSIC_PADS_CFG1);
- val &= ~UHSIC_RPU_STROBE;
- val |= UHSIC_RPD_STROBE;
- writel(val, base + UHSIC_PADS_CFG1);
-
- val = readl(base + USB_SUSP_CTRL);
- val |= UHSIC_RESET;
- writel(val, base + USB_SUSP_CTRL);
- udelay(30);
-
- if (uhsic_config->enable_gpio != -1) {
- gpio_set_value_cansleep(uhsic_config->enable_gpio, 0);
- /* keep hsic reset de-asserted for 1 ms */
- udelay(1000);
+ if (phy->ops && phy->ops->power_on) {
+ if (phy->pdata->ops && phy->pdata->ops->pre_phy_on)
+ phy->pdata->ops->pre_phy_on();
+ status = phy->ops->power_on(phy);
+ if (phy->pdata->ops && phy->pdata->ops->post_phy_on)
+ phy->pdata->ops->post_phy_on();
}
- if (uhsic_config->post_phy_off && uhsic_config->post_phy_off())
- return -EAGAIN;
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- uhsic_powerdown_pmc_wake_detect(phy);
-#endif
+ phy->phy_power_on = true;
- return 0;
+ return status;
}
-#ifdef CONFIG_USB_TEGRA_OTG
-extern void tegra_otg_check_vbus_detection(void);
-#endif
-
-static irqreturn_t usb_phy_vbus_irq_thr(int irq, void *pdata)
+int tegra_usb_phy_reset(struct tegra_usb_phy *phy)
{
- struct tegra_usb_phy *phy = pdata;
-
- if (phy->reg_vdd && !phy->regulator_on) {
- regulator_enable(phy->reg_vdd);
- phy->regulator_on = 1;
- /*
- * Optimal time to get the regulator turned on
- * before detecting vbus interrupt.
- */
- mdelay(15);
- }
+ int status = 0;
-#ifdef CONFIG_USB_TEGRA_OTG
- tegra_otg_check_vbus_detection();
-#endif
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ if (phy->ops && phy->ops->reset)
+ status = phy->ops->reset(phy);
- return IRQ_HANDLED;
+ return status;
}
-
-struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
- void *config, enum tegra_usb_phy_mode phy_mode,
- enum tegra_usb_phy_type usb_phy_type)
+int tegra_usb_phy_pre_suspend(struct tegra_usb_phy *phy)
{
- struct tegra_usb_phy *phy;
- struct tegra_ulpi_config *ulpi_config;
- unsigned long parent_rate;
- int i;
- int err;
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- struct tegra_uhsic_config *uhsic_config;
- int reset_gpio, enable_gpio;
-#endif
+ int status = 0;
- phy = kzalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL);
- if (!phy)
- return ERR_PTR(-ENOMEM);
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
- phy->instance = instance;
- phy->regs = regs;
- phy->config = config;
- phy->mode = phy_mode;
- phy->usb_phy_type = usb_phy_type;
- phy->initialized = 0;
- phy->regulator_on = 0;
- phy->power_on = 0;
- phy->remote_wakeup = false;
- phy->hotplug = 0;
- phy->xcvr_setup_value = 0;
-
- if (!phy->config) {
- if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_LINK_ULPI ||
- phy->usb_phy_type == TEGRA_USB_PHY_TYPE_NULL_ULPI) {
- pr_err("%s: ulpi phy configuration missing", __func__);
- err = -EINVAL;
- goto err0;
- } else {
- phy->config = &utmip_default[instance];
- }
- }
+ if (phy->pdata->ops && phy->pdata->ops->pre_suspend)
+ phy->pdata->ops->pre_suspend();
- phy->pll_u = clk_get_sys(NULL, "pll_u");
- if (IS_ERR(phy->pll_u)) {
- pr_err("Can't get pll_u clock\n");
- err = PTR_ERR(phy->pll_u);
- goto err0;
- }
- clk_enable(phy->pll_u);
-
- parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
- if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
- for (i = 0; i < ARRAY_SIZE(tegra_uhsic_freq_table); i++) {
- if (tegra_uhsic_freq_table[i].freq == parent_rate) {
- phy->freq = &tegra_uhsic_freq_table[i];
- break;
- }
- }
- } else {
- for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
- if (tegra_freq_table[i].freq == parent_rate) {
- phy->freq = &tegra_freq_table[i];
- break;
- }
- }
- }
- if (!phy->freq) {
- pr_err("invalid pll_u parent rate %ld\n", parent_rate);
- err = -EINVAL;
- goto err1;
- }
+ if (phy->ops && phy->ops->pre_suspend)
+ status = phy->ops->pre_suspend(phy);
- if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
- err = utmip_pad_open(phy);
- phy->xcvr_setup_value = tegra_phy_xcvr_setup_value(phy->config);
- if (err < 0)
- goto err1;
- } else if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_LINK_ULPI) {
- ulpi_config = config;
-
- if (ulpi_config->clk) {
- phy->clk = clk_get_sys(NULL, ulpi_config->clk);
- if (IS_ERR(phy->clk)) {
- pr_err("%s: can't get ulpi clock\n", __func__);
- err = -ENXIO;
- goto err1;
- }
- } else {
- /* Some USB ULPI chips are not driven by Tegra clocks or PLL */
- phy->clk = NULL;
- }
- tegra_gpio_enable(ulpi_config->reset_gpio);
- gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
- gpio_direction_output(ulpi_config->reset_gpio, 0);
- phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
- phy->ulpi->io_priv = regs + ULPI_VIEWPORT;
- }
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- else if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
- uhsic_config = config;
- enable_gpio = gpio_request(uhsic_config->enable_gpio,
- "uhsic_enable");
- reset_gpio = gpio_request(uhsic_config->reset_gpio,
- "uhsic_reset");
- /* hsic enable signal deasserted, hsic reset asserted */
- if (!enable_gpio)
- gpio_direction_output(uhsic_config->enable_gpio,
- 0 /* deasserted */);
- if (!reset_gpio)
- gpio_direction_output(uhsic_config->reset_gpio,
- 0 /* asserted */);
- if (!enable_gpio)
- tegra_gpio_enable(uhsic_config->enable_gpio);
- if (!reset_gpio)
- tegra_gpio_enable(uhsic_config->reset_gpio);
- /* keep hsic reset asserted for 1 ms */
- udelay(1000);
- /* enable (power on) hsic */
- if (!enable_gpio)
- gpio_set_value_cansleep(uhsic_config->enable_gpio, 1);
- udelay(1000);
- /* deassert reset */
- if (!reset_gpio)
- gpio_set_value_cansleep(uhsic_config->reset_gpio, 1);
- }
-#endif
-
- phy->reg_vdd = regulator_get(NULL, "avdd_usb");
- if (IS_ERR_OR_NULL(phy->reg_vdd)) {
- pr_err("couldn't get regulator avdd_usb: %ld \n",
- PTR_ERR(phy->reg_vdd));
- phy->reg_vdd = NULL;
- }
-
- if (instance == 0 && usb_phy_data[0].vbus_irq) {
- err = request_threaded_irq(usb_phy_data[0].vbus_irq, NULL, usb_phy_vbus_irq_thr, IRQF_SHARED,
- "usb_phy_vbus", phy);
- if (err) {
- pr_err("Failed to register IRQ\n");
- goto err1;
- }
- }
-
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- /* Power-up the VBUS detector for UTMIP PHY */
- if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
- unsigned long val;
- void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
-
- /* turn on pad detectors for HSIC*/
- val = readl(pmc_base + PMC_USB_AO);
- val &= ~(TEGRA_PMC_USB_AO_VBUS_WAKEUP_PD_P0 | TEGRA_PMC_USB_AO_ID_PD_P0);
- writel(val, pmc_base + PMC_USB_AO);
-
- utmip_powerup_pmc_wake_detect(phy);
-
- if (usb_phy_data[phy->instance].vbus_reg_supply) {
- phy->reg_vbus = regulator_get(NULL, usb_phy_data[phy->instance].vbus_reg_supply);
- if (WARN_ON(IS_ERR_OR_NULL(phy->reg_vbus))) {
- pr_err("couldn't get regulator vdd_vbus_usb: %ld, instance : %d\n",
- PTR_ERR(phy->reg_vbus), phy->instance);
- err = PTR_ERR(phy->reg_vbus);
- goto err1;
- }
- }
- }
- if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
- uhsic_powerup_pmc_wake_detect(phy);
- }
-
-#endif
- if (((instance == 2) || (instance == 0)) &&
- (phy->mode == TEGRA_USB_PHY_MODE_HOST)) {
- vbus_enable(phy);
- }
- return phy;
-
-err1:
- clk_disable(phy->pll_u);
- clk_put(phy->pll_u);
-err0:
- kfree(phy);
- return ERR_PTR(err);
+ return status;
}
-
-int tegra_usb_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
+int tegra_usb_phy_suspend(struct tegra_usb_phy *phy)
{
- int ret = 0;
-
- const tegra_phy_fp power_on[] = {
- utmi_phy_power_on,
- ulpi_phy_power_on,
- null_phy_power_on,
- uhsic_phy_power_on,
- };
+ int err = 0;
- if (phy->power_on)
- return ret;
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
- if ((phy->instance == 0) && usb_phy_data[0].vbus_irq &&
- (phy->mode == TEGRA_USB_PHY_MODE_DEVICE))
- is_dpd = true;
+ if (phy->ops && phy->ops->suspend)
+ err = phy->ops->suspend(phy);
- if (phy->reg_vdd && !phy->regulator_on) {
- regulator_enable(phy->reg_vdd);
- phy->regulator_on = 1;
+ if (!err && phy->pdata->u_data.host.power_off_on_suspend) {
+ if (phy->pdata->ops && phy->pdata->ops->pre_phy_off)
+ phy->pdata->ops->pre_phy_off();
+ err = phy->ops->power_off(phy);
+ if (phy->pdata->ops && phy->pdata->ops->post_phy_off)
+ phy->pdata->ops->post_phy_off();
}
- if (power_on[phy->usb_phy_type])
- ret = power_on[phy->usb_phy_type](phy, is_dpd);
-
- phy->power_on = true;
- return ret;
+ return err;
}
-
-void tegra_usb_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
+int tegra_usb_phy_post_suspend(struct tegra_usb_phy *phy)
{
- const tegra_phy_fp power_off[] = {
- utmi_phy_power_off,
- ulpi_phy_power_off,
- null_phy_power_off,
- uhsic_phy_power_off,
- };
+ int status = 0;
- if (!phy->power_on)
- return;
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
- if ((phy->instance == 0) && usb_phy_data[0].vbus_irq &&
- (phy->mode == TEGRA_USB_PHY_MODE_DEVICE))
- is_dpd = true;
+ if (phy->ops && phy->ops->post_suspend)
+ status = phy->ops->post_suspend(phy);
- if (power_off[phy->usb_phy_type])
- power_off[phy->usb_phy_type](phy, is_dpd);
+ if (phy->pdata->ops && phy->pdata->ops->post_suspend)
+ phy->pdata->ops->post_suspend();
- if (phy->reg_vdd && phy->regulator_on && is_dpd) {
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- if (tegra_get_revision() >= TEGRA_REVISION_A03)
-#endif
- regulator_disable(phy->reg_vdd);
- phy->regulator_on = 0;
- }
- phy->power_on = false;
+ return status;
}
-
-void tegra_usb_phy_preresume(struct tegra_usb_phy *phy, bool remote_wakeup)
+int tegra_usb_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
{
- const tegra_phy_fp preresume[] = {
- utmi_phy_preresume,
- NULL,
- NULL,
- uhsic_phy_preresume,
- };
+ int status = 0;
- if (preresume[phy->usb_phy_type])
- preresume[phy->usb_phy_type](phy, remote_wakeup);
-}
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
-void tegra_usb_phy_postsuspend(struct tegra_usb_phy *phy, bool is_dpd)
+ if (phy->pdata->ops && phy->pdata->ops->pre_resume)
+ phy->pdata->ops->pre_resume();
-{
- const tegra_phy_fp postsuspend[] = {
- NULL,
- NULL,
- NULL,
- uhsic_phy_postsuspend,
- };
+ if (phy->ops && phy->ops->pre_resume)
+ status = phy->ops->pre_resume(phy, remote_wakeup);
- if (postsuspend[phy->usb_phy_type])
- postsuspend[phy->usb_phy_type](phy, is_dpd);
+ return status;
}
-
-void tegra_usb_phy_postresume(struct tegra_usb_phy *phy, bool is_dpd)
+int tegra_usb_phy_resume(struct tegra_usb_phy *phy)
{
- const tegra_phy_fp postresume[] = {
- utmi_phy_postresume,
- NULL,
- NULL,
- NULL,
- };
+ int err = 0;
- usb_phy_set_tx_fill_tuning(phy, is_dpd);
-
- // If Phy type is utmi, call its post resume
- if (phy->usb_phy_type == 0)
- utmi_phy_postresume(phy, is_dpd);
-}
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
-void tegra_ehci_pre_reset(struct tegra_usb_phy *phy, bool is_dpd)
-{
- const tegra_phy_fp pre_reset[] = {
- NULL,
- NULL,
- null_phy_pre_usbcmd_reset,
- NULL,
- };
+ if (phy->pdata->u_data.host.power_off_on_suspend) {
+ if (phy->pdata->ops && phy->pdata->ops->pre_phy_on)
+ phy->pdata->ops->pre_phy_on();
+ err = phy->ops->power_on(phy);
+ if (phy->pdata->ops && phy->pdata->ops->post_phy_on)
+ phy->pdata->ops->post_phy_on();
+ }
- if (pre_reset[phy->usb_phy_type])
- pre_reset[phy->usb_phy_type](phy, is_dpd);
-}
+ if (!err && phy->ops && phy->ops->resume)
+ err = phy->ops->resume(phy);
-void tegra_ehci_post_reset(struct tegra_usb_phy *phy, bool is_dpd)
-{
- const tegra_phy_fp post_reset[] = {
- NULL,
- NULL,
- null_phy_post_usbcmd_reset,
- NULL,
- };
+ return err;
- if (post_reset[phy->usb_phy_type])
- post_reset[phy->usb_phy_type](phy, is_dpd);
}
-
-void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
- enum tegra_usb_phy_port_speed port_speed)
+int tegra_usb_phy_post_resume(struct tegra_usb_phy *phy)
{
- const tegra_phy_restore_start_fp phy_restore_start[] = {
- utmi_phy_restore_start,
- ulpi_phy_restore_start,
- null_phy_restore_start,
- NULL,
- };
+ int status = 0;
- if (phy_restore_start[phy->usb_phy_type])
- phy_restore_start[phy->usb_phy_type](phy, port_speed);
-}
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
-void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy)
-{
- const tegra_phy_restore_end_fp phy_restore_end[] = {
- utmi_phy_restore_end,
- ulpi_phy_restore_end,
- null_phy_restore_end,
- NULL,
- };
+ if (phy->ops && phy->ops->post_resume)
+ status = phy->ops->post_resume(phy);
- if (phy_restore_end[phy->usb_phy_type])
- phy_restore_end[phy->usb_phy_type](phy);
-}
+ if (phy->pdata->ops && phy->pdata->ops->post_resume)
+ phy->pdata->ops->post_resume();
-void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy)
-{
- if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP)
- utmi_phy_clk_disable(phy);
+ return status;
}
-
-void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
+int tegra_usb_phy_port_power(struct tegra_usb_phy *phy)
{
- if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP)
- utmi_phy_clk_enable(phy);
-}
+ int status = 0;
-void tegra_usb_phy_close(struct tegra_usb_phy *phy)
-{
- if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
- utmip_pad_close(phy);
- utmip_phy_disable_pmc_bus_ctrl(phy);
- }
- else if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_LINK_ULPI && phy->clk)
- clk_put(phy->clk);
- if (phy->mode == TEGRA_USB_PHY_MODE_HOST) {
- vbus_disable(phy);
- }
- clk_disable(phy->pll_u);
- clk_put(phy->pll_u);
- if (phy->reg_vbus)
- regulator_put(phy->reg_vbus);
- if (phy->reg_vdd)
- regulator_put(phy->reg_vdd);
- if (phy->instance == 0 && usb_phy_data[0].vbus_irq)
- free_irq(usb_phy_data[0].vbus_irq, phy);
- kfree(phy);
-}
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
-int tegra_usb_phy_bus_connect(struct tegra_usb_phy *phy)
-{
- unsigned long val;
- void __iomem *base = phy->regs;
- struct tegra_uhsic_config *uhsic_config = phy->config;
-
- if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- val = readl(base + TEGRA_USB_USBMODE_REG_OFFSET);
- val |= TEGRA_USB_USBMODE_HOST;
- writel(val, base + TEGRA_USB_USBMODE_REG_OFFSET);
-
- /* Change the USB controller PHY type to HSIC */
- val = readl(base + HOSTPC1_DEVLC);
- val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
- val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
- val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
- val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
- writel(val, base + HOSTPC1_DEVLC);
-#endif
- val = readl(base + UHSIC_MISC_CFG0);
- val |= UHSIC_DETECT_SHORT_CONNECT;
- writel(val, base + UHSIC_MISC_CFG0);
- udelay(1);
-
- val = readl(base + UHSIC_MISC_CFG0);
- val |= UHSIC_FORCE_XCVR_MODE;
- writel(val, base + UHSIC_MISC_CFG0);
+ if (phy->ops && phy->ops->port_power)
+ status = phy->ops->port_power(phy);
- val = readl(base + UHSIC_PADS_CFG1);
- val &= ~UHSIC_RPD_STROBE;
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- val |= UHSIC_RPU_STROBE;
-#endif
- writel(val, base + UHSIC_PADS_CFG1);
-
- if (uhsic_config->usb_phy_ready &&
- uhsic_config->usb_phy_ready())
- return -EAGAIN;
-
- /* connect detect on T30 requires extra wait */
- if (utmi_wait_register_timeout(base + UHSIC_STAT_CFG0,
- UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT,
- CONNECT_DETECT_TIMEOUT) < 0) {
- pr_err("%s: timeout waiting for hsic connect detect\n", __func__);
- return -ETIMEDOUT;
- }
-
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_LS(2), USB_PORTSC1_LS(2)) < 0) {
- pr_err("%s: timeout waiting for dplus state\n", __func__);
- return -ETIMEDOUT;
- }
-#endif
- }
+ if (phy->pdata->ops && phy->pdata->ops->port_power)
+ phy->pdata->ops->port_power();
- return 0;
+ return status;
}
-
int tegra_usb_phy_bus_reset(struct tegra_usb_phy *phy)
{
- unsigned long val;
- void __iomem *base = phy->regs;
-
- if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- /* Change the USB controller PHY type to HSIC */
- val = readl(base + HOSTPC1_DEVLC);
- val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
- val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
- val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
- val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
- writel(val, base + HOSTPC1_DEVLC);
- /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
- mdelay(5);
-#endif
- val = readl(base + USB_PORTSC1);
- val |= USB_PORTSC1_PTC(5);
- writel(val, base + USB_PORTSC1);
- udelay(2);
-
- val = readl(base + USB_PORTSC1);
- val &= ~USB_PORTSC1_PTC(~0);
- writel(val, base + USB_PORTSC1);
- udelay(2);
-
- if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_LS(0), 0) < 0) {
- pr_err("%s: timeout waiting for SE0\n", __func__);
- return -ETIMEDOUT;
- }
+ int status = 0;
- if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_CCS, USB_PORTSC1_CCS) < 0) {
- pr_err("%s: timeout waiting for connection status\n", __func__);
- return -ETIMEDOUT;
- }
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
-#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
- if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_PSPD(2), USB_PORTSC1_PSPD(2)) < 0) {
- pr_err("%s: timeout waiting hsic high speed configuration\n", __func__);
- return -ETIMEDOUT;
- }
-#elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
- if (utmi_wait_register(base + HOSTPC1_DEVLC,
- HOSTPC1_DEVLC_PSPD(2),
- HOSTPC1_DEVLC_PSPD(2)) < 0) {
- pr_err("%s: timeout waiting hsic high speed configuration\n", __func__);
- return -ETIMEDOUT;
- }
-#endif
- val = readl(base + USB_USBCMD);
- val &= ~USB_USBCMD_RS;
- writel(val, base + USB_USBCMD);
-
- if (utmi_wait_register(base + USB_USBSTS, USB_USBSTS_HCH, USB_USBSTS_HCH) < 0) {
- pr_err("%s: timeout waiting for stopping the controller\n", __func__);
- return -ETIMEDOUT;
- }
-
- val = readl(base + UHSIC_PADS_CFG1);
- val &= ~UHSIC_RPU_STROBE;
- val |= UHSIC_RPD_STROBE;
- writel(val, base + UHSIC_PADS_CFG1);
-
- mdelay(50);
-
- val = readl(base + UHSIC_PADS_CFG1);
- val &= ~UHSIC_RPD_STROBE;
- val |= UHSIC_RPU_STROBE;
- writel(val, base + UHSIC_PADS_CFG1);
-
- val = readl(base + USB_USBCMD);
- val |= USB_USBCMD_RS;
- writel(val, base + USB_USBCMD);
-
- val = readl(base + UHSIC_PADS_CFG1);
- val &= ~UHSIC_RPU_STROBE;
- writel(val, base + UHSIC_PADS_CFG1);
+ if (phy->ops && phy->ops->bus_reset)
+ status = phy->ops->bus_reset(phy);
- if (utmi_wait_register(base + USB_USBCMD, USB_USBCMD_RS, USB_USBCMD_RS) < 0) {
- pr_err("%s: timeout waiting for starting the controller\n", __func__);
- return -ETIMEDOUT;
- }
- }
-
- return 0;
+ return status;
}
-int tegra_usb_phy_bus_idle(struct tegra_usb_phy *phy)
+bool tegra_usb_phy_charger_detected(struct tegra_usb_phy *phy)
{
- unsigned long val;
- void __iomem *base = phy->regs;
- struct tegra_uhsic_config *uhsic_config = phy->config;
-
- if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
-
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- val = readl(base + TEGRA_USB_USBMODE_REG_OFFSET);
- val |= TEGRA_USB_USBMODE_HOST;
- writel(val, base + TEGRA_USB_USBMODE_REG_OFFSET);
-
- /* Change the USB controller PHY type to HSIC */
- val = readl(base + HOSTPC1_DEVLC);
- val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
- val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
- val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
- val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
- writel(val, base + HOSTPC1_DEVLC);
-#endif
- val = readl(base + UHSIC_MISC_CFG0);
- val |= UHSIC_DETECT_SHORT_CONNECT;
- writel(val, base + UHSIC_MISC_CFG0);
- udelay(1);
+ bool status = 0;
- val = readl(base + UHSIC_MISC_CFG0);
- val |= UHSIC_FORCE_XCVR_MODE;
- writel(val, base + UHSIC_MISC_CFG0);
-
- val = readl(base + UHSIC_PADS_CFG1);
- val &= ~UHSIC_RPD_STROBE;
- /* safe to enable RPU on STROBE at all times during idle */
- val |= UHSIC_RPU_STROBE;
- writel(val, base + UHSIC_PADS_CFG1);
-
- val = readl(base + USB_USBCMD);
- val &= ~USB_USBCMD_RS;
- writel(val, base + USB_USBCMD);
-
- if (uhsic_config->usb_phy_ready &&
- uhsic_config->usb_phy_ready())
- return -EAGAIN;
-
- /* connect detect on T30 requires extra wait */
- if (utmi_wait_register_timeout(base + UHSIC_STAT_CFG0,
- UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT,
- CONNECT_DETECT_TIMEOUT) < 0) {
- pr_err("%s: timeout waiting for hsic connect detect\n",
- __func__);
- return -ETIMEDOUT;
- }
- }
- return 0;
+ DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
+ if (phy->ops && phy->ops->charger_detect)
+ status = phy->ops->charger_detect(phy);
+
+ return status;
}
-bool tegra_usb_phy_is_device_connected(struct tegra_usb_phy *phy)
+bool tegra_usb_phy_hw_accessible(struct tegra_usb_phy *phy)
{
- void __iomem *base = phy->regs;
+ if (!phy->hw_accessible)
+ DBG("%s(%d) inst:[%d] Not Accessible\n", __func__,
+ __LINE__, phy->inst);
- if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
- if (utmi_wait_register(base + UHSIC_STAT_CFG0,
- UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT) < 0) {
- pr_err("%s: no hsic connection\n", __func__);
- return false;
- }
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_LS(2), USB_PORTSC1_LS(2)) < 0) {
- pr_err("%s: timeout waiting for dplus state\n", __func__);
- return false;
- }
-#endif
- }
- return true;
+ return phy->hw_accessible;
}
-bool tegra_usb_phy_charger_detect(struct tegra_usb_phy *phy)
+bool tegra_usb_phy_remote_wakeup(struct tegra_usb_phy *phy)
{
- unsigned long val;
- void __iomem *base = phy->regs;
- bool status;
-
- if (phy->usb_phy_type != TEGRA_USB_PHY_TYPE_UTMIP)
- {
- /* Charger detection is not there for ULPI
- * return Charger not available */
- return false;
- }
-
- /* Enable charger detection logic */
- val = readl(base + UTMIP_BAT_CHRG_CFG0);
- val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
- writel(val, base + UTMIP_BAT_CHRG_CFG0);
-
- /* Source should be on for 100 ms as per USB charging spec */
- msleep(TDP_SRC_ON_MS);
-
- val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
- /* If charger is not connected disable the interrupt */
- val &= ~VDAT_DET_INT_EN;
- val |= VDAT_DET_CHG_DET;
- writel(val,base + USB_PHY_VBUS_WAKEUP_ID);
-
- val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
- if (val & VDAT_DET_STS)
- status = true;
- else
- status = false;
-
- /* Disable charger detection logic */
- val = readl(base + UTMIP_BAT_CHRG_CFG0);
- val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
- writel(val, base + UTMIP_BAT_CHRG_CFG0);
-
- /* Delay of 40 ms before we pull the D+ as per battery charger spec */
- msleep(TDPSRC_CON_MS);
-
- return status;
+ return phy->remote_wakeup;
}
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
-void tegra_usb_phy_power_down_pmc(void)
+bool tegra_usb_phy_has_hostpc(struct tegra_usb_phy *phy)
{
- unsigned long val;
- void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
-
- /* power down all 3 UTMIP interfaces */
- val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
- val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
- writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
-
- /* turn on pad detectors */
- writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
-
- /* setup sleep walk fl all 3 usb controllers */
- val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
- UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
- UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
- UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
- writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
- writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
- writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
-
- /* enable pull downs on HSIC PMC */
- val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
- UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
- UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
- writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
-
- /* Turn over pad configuration to PMC */
- val = readl(pmc_base + PMC_SLEEP_CFG);
- val &= ~UTMIP_WAKE_VAL(0, ~0);
- val &= ~UTMIP_WAKE_VAL(1, ~0);
- val &= ~UTMIP_WAKE_VAL(2, ~0);
- val &= ~UHSIC_WAKE_VAL_P0(~0);
- val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
- UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
- UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
- UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
- UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
- UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
- UHSIC_MASTER_ENABLE_P0;
- writel(val, pmc_base + PMC_SLEEP_CFG);
+ return phy->pdata->has_hostpc;
}
-#endif
-int __init tegra_usb_phy_init(struct usb_phy_plat_data *pdata, int size)
+bool tegra_usb_phy_otg_supported(struct tegra_usb_phy *phy)
{
- if (pdata) {
- int i;
-
- for (i = 0; i < size; i++, pdata++) {
- usb_phy_data[pdata->instance].instance = pdata->instance;
- usb_phy_data[pdata->instance].vbus_irq = pdata->vbus_irq;
- usb_phy_data[pdata->instance].vbus_gpio = pdata->vbus_gpio;
- usb_phy_data[pdata->instance].vbus_reg_supply = pdata->vbus_reg_supply;
- }
- }
-
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- tegra_usb_phy_power_down_pmc();
-#endif
-
- return 0;
+ return phy->pdata->port_otg;
}
void tegra_usb_phy_memory_prefetch_on(struct tegra_usb_phy *phy)
@@ -3197,7 +643,7 @@ void tegra_usb_phy_memory_prefetch_on(struct tegra_usb_phy *phy)
void __iomem *ahb_gizmo = IO_ADDRESS(TEGRA_AHB_GIZMO_BASE);
unsigned long val;
- if (phy->instance == 0 && phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
+ if (phy->inst == 0 && phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
val = readl(ahb_gizmo + AHB_MEM_PREFETCH_CFG1);
val |= PREFETCH_ENB;
writel(val, ahb_gizmo + AHB_MEM_PREFETCH_CFG1);
@@ -3212,7 +658,7 @@ void tegra_usb_phy_memory_prefetch_off(struct tegra_usb_phy *phy)
void __iomem *ahb_gizmo = IO_ADDRESS(TEGRA_AHB_GIZMO_BASE);
unsigned long val;
- if (phy->instance == 0 && phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
+ if (phy->inst == 0 && phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
val = readl(ahb_gizmo + AHB_MEM_PREFETCH_CFG1);
val &= ~(PREFETCH_ENB);
writel(val, ahb_gizmo + AHB_MEM_PREFETCH_CFG1);
@@ -3221,38 +667,3 @@ void tegra_usb_phy_memory_prefetch_off(struct tegra_usb_phy *phy)
writel(val, ahb_gizmo + AHB_MEM_PREFETCH_CFG2);
}
}
-
-/* disable walk and wake events after resume from LP0 */
-bool tegra_usb_phy_is_remotewake_detected(struct tegra_usb_phy *phy)
-{
-#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
- void __iomem *base = phy->regs;
- unsigned int inst = phy->instance;
- u32 val;
-
- val = readl(base + UTMIP_PMC_WAKEUP0);
- if (val & EVENT_INT_ENB) {
- val = readl(pmc_base + UTMIP_UHSIC_STATUS);
- if (UTMIP_WAKE_ALARM(inst) & val) {
- val = readl(pmc_base + PMC_SLEEP_CFG);
- val &= ~UTMIP_WAKE_VAL(inst, 0x0);
- val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
- writel(val, pmc_base + PMC_SLEEP_CFG);
-
- val = readl(pmc_base + PMC_TRIGGERS);
- val |= UTMIP_CLR_WAKE_ALARM(inst) |
- UTMIP_CLR_WALK_PTR(inst);
- writel(val, pmc_base + PMC_TRIGGERS);
-
- val = readl(base + UTMIP_PMC_WAKEUP0);
- val &= ~EVENT_INT_ENB;
- writel(val, base + UTMIP_PMC_WAKEUP0);
- phy->remote_wakeup = true;
- return true;
- }
- }
-#endif
- return false;
-}
-
diff --git a/chromeos/config/armel/config.common.armel b/chromeos/config/armel/config.common.armel
new file mode 100644
index 00000000..efc5f4e
--- /dev/null
+++ b/chromeos/config/armel/config.common.armel
@@ -0,0 +1,528 @@
+#
+# Config options generated by splitconfig
+#
+CONFIG_AEABI=y
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_APM_EMULATION is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CNS3XXX is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_EXYNOS4 is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_H720X is not set
+CONFIG_ARCH_HAS_CPUFREQ=y
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_MXS is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_NOMADIK is not set
+CONFIG_ARCH_NR_GPIO=512
+# CONFIG_ARCH_NUC93X is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PRIMA2 is not set
+CONFIG_ARCH_PROVIDES_UDELAY=y
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_REALVIEW is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P64X0 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_TCC_926 is not set
+CONFIG_ARCH_TEGRA=y
+CONFIG_ARCH_TEGRA_HAS_PCIE=y
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_VT8500 is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_ZYNQ is not set
+CONFIG_ARM=y
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+# CONFIG_ARM_ERRATA_720789 is not set
+# CONFIG_ARM_ERRATA_720791 is not set
+CONFIG_ARM_ERRATA_742230=y
+# CONFIG_ARM_ERRATA_742231 is not set
+# CONFIG_ARM_ERRATA_753970 is not set
+# CONFIG_ARM_ERRATA_754327 is not set
+# CONFIG_ARM_ERRATA_764369 is not set
+# CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART is not set
+CONFIG_ARM_GIC=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
+CONFIG_ARM_SAVE_DEBUG_CONTEXT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_UNWIND=y
+# CONFIG_ATA is not set
+# CONFIG_ATH5K is not set
+# CONFIG_ATH5K_PCI is not set
+# CONFIG_ATH6K_LEGACY is not set
+# CONFIG_ATH9K is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1C is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL2 is not set
+# CONFIG_AUTO_ZRELADDR is not set
+# CONFIG_AX88796 is not set
+# CONFIG_B44 is not set
+CONFIG_BACKLIGHT_PWM=y
+# CONFIG_BACKLIGHT_TEGRA_PWM is not set
+CONFIG_BATTERY_BQ20Z75=y
+# CONFIG_BCM4329 is not set
+# CONFIG_BCMDHD is not set
+# CONFIG_BE2ISCSI is not set
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_BRCMDBG is not set
+CONFIG_BRCMFMAC=m
+CONFIG_BRCMUTIL=m
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_BT_ATH3K is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+CONFIG_BT_HCIBTSDIO=m
+CONFIG_BT_HCIUART=m
+# CONFIG_BT_HCIUART_ATH3K is not set
+# CONFIG_BT_HCIUART_BCSP is not set
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CACHE_PL310=y
+CONFIG_CHARGER_GPIO=y
+# CONFIG_CHARGER_ISP1704 is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CMDLINE="mem=448M@0M console=ttyS0,115200n8 earlyprintk init=/bin/ash"
+# CONFIG_CMDLINE_EXTEND is not set
+# CONFIG_CMDLINE_FORCE is not set
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_CPA=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_HAS_PMU=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+# CONFIG_CRASH_DUMP is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_DEV_TEGRA_AES is not set
+# CONFIG_DCC_TTY is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+# CONFIG_DEBUG_ICEDCC is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+# CONFIG_DM9000 is not set
+# CONFIG_DRM is not set
+CONFIG_DTC=y
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_TEGRA=y
+# CONFIG_FCOE is not set
+CONFIG_FIQ=y
+# CONFIG_FIQ_DEBUGGER is not set
+CONFIG_FLATMEM=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_FRAME_WARN=1024
+# CONFIG_FTGMAC100 is not set
+# CONFIG_FTMAC100 is not set
+CONFIG_FUNCTION_GRAPH_TRACER=y
+CONFIG_HARDIRQS_SW_RESEND=y
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+CONFIG_HAVE_AOUT=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_TWD=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_PWM=y
+CONFIG_HAVE_SCHED_CLOCK=y
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_PID is not set
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+# CONFIG_HOSTAP_PCI is not set
+# CONFIG_HOSTAP_PLX is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HVC_DCC is not set
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_HZ=100
+# CONFIG_I2C_DESIGNWARE is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_PIIX4 is not set
+CONFIG_I2C_TEGRA=y
+# CONFIG_IGBVF is not set
+# CONFIG_INPUT_PWM_BEEPER is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+CONFIG_IRQ_DOMAIN=y
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_IWL3945 is not set
+# CONFIG_IWL4965 is not set
+# CONFIG_IWLAGN is not set
+# CONFIG_IWM is not set
+# CONFIG_IWMC3200TOP is not set
+# CONFIG_JME is not set
+CONFIG_KEYBOARD_TEGRA=y
+CONFIG_KTIME_SCALAR=y
+CONFIG_LBDAF=y
+CONFIG_LEDS_PWM=y
+# CONFIG_LEDS_REGULATOR is not set
+# CONFIG_LIBERTAS_THINFIRM_USB is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+CONFIG_LOCAL_TIMERS=y
+# CONFIG_LPC_SCH is not set
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACH_HAS_SND_SOC_TEGRA_WM8903=y
+# CONFIG_MACH_TEGRA_DT is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_MFD_ASIC3 is not set
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_NVEC is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_MG_DISK is not set
+CONFIG_MMC=y
+# CONFIG_MMC_BKOPS is not set
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
+CONFIG_MMC_BLOCK_MINORS=16
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_CLKGATE is not set
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_DW is not set
+# CONFIG_MMC_EMBEDDED_SDIO is not set
+# CONFIG_MMC_PARANOID_SD_INIT is not set
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_SDHCI_PXAV2 is not set
+# CONFIG_MMC_SDHCI_PXAV3 is not set
+CONFIG_MMC_SDHCI_TEGRA=y
+# CONFIG_MMC_TEST is not set
+# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_USHC is not set
+# CONFIG_MMC_VIA_SDMMC is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_PS2 is not set
+CONFIG_NEED_DMA_MAP_STATE=y
+# CONFIG_NET_PCI is not set
+CONFIG_NVMAP_ALLOW_SYSMEM=y
+CONFIG_NVMAP_CARVEOUT_COMPACTOR=y
+# CONFIG_NVMAP_CARVEOUT_KILLER is not set
+# CONFIG_NVMAP_HIGHMEM_ONLY is not set
+CONFIG_NVMAP_PAGE_POOLS=y
+CONFIG_NVMAP_PAGE_POOL_SIZE=0x0
+CONFIG_NVMAP_RECLAIM_UNPINNED_VM=y
+# CONFIG_NVMAP_VPR is not set
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_OC_ETM is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DEVICE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_I2C=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_SPI=y
+CONFIG_OLD_MCOUNT=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PCI_SYSCALL=y
+CONFIG_PERF_USE_VMALLOC=y
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+# CONFIG_PL310_ERRATA_588369 is not set
+# CONFIG_PL310_ERRATA_727915 is not set
+# CONFIG_PL310_ERRATA_769419 is not set
+# CONFIG_PLAT_SPEAR is not set
+CONFIG_PM_CLK=y
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_R8169 is not set
+# CONFIG_RC_CORE is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_AD5398 is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_DUMMY is not set
+# CONFIG_REGULATOR_FAN53555 is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_GPIO is not set
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_TPS6238X0 is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_REGULATOR_TPS6524X is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+CONFIG_RFKILL_GPIO=m
+# CONFIG_RFKILL_REGULATOR is not set
+# CONFIG_RT2500USB is not set
+# CONFIG_RT2800USB is not set
+# CONFIG_RT73USB is not set
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_TEGRA is not set
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTL8192CE is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_3W_SAS is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_SCSI_BFA_FC is not set
+# CONFIG_SCSI_BNX2X_FCOE is not set
+# CONFIG_SCSI_BNX2_ISCSI is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_CXGB3_ISCSI is not set
+# CONFIG_SCSI_CXGB4_ISCSI is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_HPSA is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_IPS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_MPT2SAS is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_PM8001 is not set
+# CONFIG_SCSI_PMCRAID is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SD8797 is not set
+# CONFIG_SDIO_UART is not set
+CONFIG_SENSORS_ISL29018=m
+# CONFIG_SENSORS_LIS3_SPI is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_EXTENDED is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_SERIAL_TEGRA is not set
+# CONFIG_SERIO_PCIPS2 is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SMC911X is not set
+CONFIG_SMC91X=m
+CONFIG_SMP_ON_UP=y
+# CONFIG_SMSC911X is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_HDA_INTEL is not set
+CONFIG_SND_PCM=y
+CONFIG_SND_SOC=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SND_SOC_CACHE_LZO is not set
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SOC_SPDIF=y
+CONFIG_SND_SOC_TEGRA=y
+CONFIG_SND_SOC_TEGRA_WM8903=y
+# CONFIG_SND_SOC_TLV320AIC326X is not set
+CONFIG_SND_SOC_WM8903=y
+CONFIG_SND_TIMER=y
+CONFIG_SOC_CAMERA=m
+# CONFIG_SOC_CAMERA_IMX074 is not set
+# CONFIG_SOC_CAMERA_MT9M001 is not set
+# CONFIG_SOC_CAMERA_MT9M111 is not set
+# CONFIG_SOC_CAMERA_MT9T031 is not set
+# CONFIG_SOC_CAMERA_MT9T112 is not set
+# CONFIG_SOC_CAMERA_MT9V022 is not set
+CONFIG_SOC_CAMERA_OV2640=m
+# CONFIG_SOC_CAMERA_OV5642 is not set
+# CONFIG_SOC_CAMERA_OV6650 is not set
+# CONFIG_SOC_CAMERA_OV772X is not set
+# CONFIG_SOC_CAMERA_OV9640 is not set
+CONFIG_SOC_CAMERA_OV9740=m
+# CONFIG_SOC_CAMERA_PLATFORM is not set
+# CONFIG_SOC_CAMERA_RJ54N1 is not set
+# CONFIG_SOC_CAMERA_TW9910 is not set
+# CONFIG_SPARSE_IRQ is not set
+# CONFIG_SPI_SLAVE_TEGRA is not set
+# CONFIG_SPI_TEGRA is not set
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+CONFIG_SQUASHFS_LZO=y
+# CONFIG_SQUASHFS_XATTR is not set
+# CONFIG_SQUASHFS_XZ is not set
+CONFIG_SQUASHFS_ZLIB=y
+# CONFIG_SSB is not set
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+# CONFIG_TCG_TIS is not set
+# CONFIG_TEGRA_AVP is not set
+# CONFIG_TEGRA_BB_SUPPORT is not set
+# CONFIG_TEGRA_BB_XMM_POWER is not set
+# CONFIG_TEGRA_BB_XMM_POWER2 is not set
+# CONFIG_TEGRA_BPC_MGMT is not set
+CONFIG_TEGRA_CAMERA=y
+CONFIG_TEGRA_CLOCK_DEBUG_WRITE=y
+CONFIG_TEGRA_CORE_DVFS=y
+CONFIG_TEGRA_CPU_DVFS=y
+CONFIG_TEGRA_DC=y
+CONFIG_TEGRA_DC_EXTENSIONS=y
+# CONFIG_TEGRA_DEBUG_UARTC is not set
+# CONFIG_TEGRA_DEBUG_UARTD is not set
+# CONFIG_TEGRA_DEBUG_UARTE is not set
+# CONFIG_TEGRA_DEBUG_UART_NONE is not set
+# CONFIG_TEGRA_DSI is not set
+CONFIG_TEGRA_DTV=y
+CONFIG_TEGRA_EMC_SCALING_ENABLE=y
+# CONFIG_TEGRA_FIQ_DEBUGGER is not set
+# CONFIG_TEGRA_FPGA_PLATFORM is not set
+CONFIG_TEGRA_GRHOST=y
+# CONFIG_TEGRA_HDMI_74MHZ_LIMIT is not set
+# CONFIG_TEGRA_IOMMU_SMMU is not set
+CONFIG_TEGRA_IOVMM=y
+# CONFIG_TEGRA_MC_PROFILE is not set
+# CONFIG_TEGRA_MEDIASERVER is not set
+CONFIG_TEGRA_NVAVP=y
+# CONFIG_TEGRA_NVHDCP is not set
+CONFIG_TEGRA_NVMAP=y
+CONFIG_TEGRA_PWM=y
+CONFIG_TEGRA_RPC=y
+CONFIG_TEGRA_SILICON_PLATFORM=y
+# CONFIG_TEGRA_SIMULATION_PLATFORM is not set
+CONFIG_TEGRA_SYSTEM_DMA=y
+CONFIG_TEGRA_THERMAL_THROTTLE=y
+# CONFIG_TEGRA_USB_MODEM_POWER is not set
+# CONFIG_TEGRA_WDT_RECOVERY is not set
+# CONFIG_THUMB2_KERNEL is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_TORCH_SSL3250A is not set
+# CONFIG_TORCH_TPS61050 is not set
+CONFIG_TOUCHSCREEN_ATMEL_MXT=m
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+CONFIG_USB_EHCI_TEGRA=y
+# CONFIG_USB_NET_DM9601 is not set
+# CONFIG_USB_NET_NET1080 is not set
+# CONFIG_USB_OHCI_HCD is not set
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_TEGRA_OTG is not set
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USE_OF=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF_GEN=m
+# CONFIG_VIDEO_AD5820 is not set
+# CONFIG_VIDEO_AR0832 is not set
+# CONFIG_VIDEO_OV14810 is not set
+# CONFIG_VIDEO_OV2710 is not set
+# CONFIG_VIDEO_OV5640 is not set
+# CONFIG_VIDEO_OV5650 is not set
+# CONFIG_VIDEO_OV9726 is not set
+# CONFIG_VIDEO_SH532U is not set
+# CONFIG_VIDEO_SH_MOBILE_CEU is not set
+# CONFIG_VIDEO_SH_MOBILE_CSI2 is not set
+# CONFIG_VIDEO_SOC380 is not set
+# CONFIG_VIRTIO_PCI is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_XFRM_USER=m
+# CONFIG_XIP_KERNEL is not set
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
+# CONFIG_ZD1211RW is not set
+CONFIG_ZONE_DMA_FLAG=0
diff --git a/chromeos/config/armel/config.flavour.chromeos-tegra3 b/chromeos/config/armel/config.flavour.chromeos-tegra3
new file mode 100644
index 00000000..3d2488f
--- /dev/null
+++ b/chromeos/config/armel/config.flavour.chromeos-tegra3
@@ -0,0 +1,125 @@
+#
+# Config options generated by splitconfig
+#
+# CONFIG_AFS_FS is not set
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+CONFIG_ARCH_SUPPORTS_MSI=y
+CONFIG_ARCH_TEGRA_3x_SOC=y
+CONFIG_ARCH_TEGRA_HAS_DUAL_3D=y
+CONFIG_ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS=y
+CONFIG_ARCH_TEGRA_HAS_SATA=y
+# CONFIG_ARM_ERRATA_716044 is not set
+CONFIG_ARM_ERRATA_743622=y
+CONFIG_ARM_ERRATA_751472=y
+CONFIG_ARM_ERRATA_752520=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_BATTERY_BQ27X00_I2C=y
+CONFIG_BATTERY_BQ27X00_PLATFORM=y
+CONFIG_BATTERY_BQ27x00=y
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CRYPTO_CTS=y
+# CONFIG_CRYPTO_DEV_TEGRA_SE is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DNOTIFY=y
+CONFIG_DNS_RESOLVER=y
+CONFIG_EXPORTFS=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+CONFIG_GIC_SET_MULTIPLE_CPUS=y
+CONFIG_IPV6=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_LZO_COMPRESS=y
+# CONFIG_MACH_ARUBA is not set
+CONFIG_MACH_CARDHU=y
+CONFIG_MACH_HAS_SND_SOC_TEGRA_MAX98095=y
+CONFIG_MACH_HAS_SND_SOC_TEGRA_TLV320AIC326X=y
+# CONFIG_MACH_KAI is not set
+# CONFIG_MACH_P1852 is not set
+# CONFIG_MACH_TEGRA_ENTERPRISE is not set
+# CONFIG_MFD_TPS6586X is not set
+CONFIG_MFD_TPS6591X=y
+# CONFIG_NCP_FS is not set
+CONFIG_NEON=y
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_USE_KERNEL_DNS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+# CONFIG_NFS_USE_NEW_IDMAPPER is not set
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_NR_CPUS=4
+CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM=y
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_PCI_MSI=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGULATOR_TPS62360=y
+CONFIG_REGULATOR_TPS6591X=y
+CONFIG_REPORT_PRESENT_CPUS=y
+CONFIG_ROOT_NFS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+CONFIG_RTC_DRV_TPS6591x=y
+CONFIG_SENSORS_ISL29028=m
+CONFIG_SENSORS_NCT1008=y
+# CONFIG_SENSORS_TEGRA_TSENSOR is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+CONFIG_SND_SOC_MAX98095=y
+CONFIG_SND_SOC_TEGRA30_AHUB=y
+CONFIG_SND_SOC_TEGRA30_DAM=y
+CONFIG_SND_SOC_TEGRA30_I2S=y
+CONFIG_SND_SOC_TEGRA30_SPDIF=y
+CONFIG_SND_SOC_TEGRA_MAX98095=y
+# CONFIG_SND_SOC_TEGRA_TLV320AIC326X is not set
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_SWAP=y
+CONFIG_TASK_SIZE=0x7F000000
+CONFIG_TASK_SIZE_2G_LESS_16M=y
+# CONFIG_TASK_SIZE_2G_LESS_24M is not set
+CONFIG_TEGRA_AUTO_HOTPLUG=y
+CONFIG_TEGRA_AVP_KERNEL_ON_SMMU=y
+# CONFIG_TEGRA_CARDHU_DSI is not set
+CONFIG_TEGRA_CLUSTER_CONTROL=y
+CONFIG_TEGRA_DEBUG_UARTA=y
+# CONFIG_TEGRA_DEBUG_UARTB is not set
+CONFIG_TEGRA_DYNAMIC_PWRDET=y
+CONFIG_TEGRA_EDP_EXACT_FREQ=y
+CONFIG_TEGRA_EDP_LIMITS=y
+CONFIG_TEGRA_EMC_TO_DDR_CLOCK=1
+CONFIG_TEGRA_IOVMM_SMMU=y
+# CONFIG_TEGRA_IOVMM_SMMU_SYSFS is not set
+CONFIG_TEGRA_LP2_ARM_TWD=y
+# CONFIG_TEGRA_MC_EARLY_ACK is not set
+CONFIG_TEGRA_PCI=y
+CONFIG_TEGRA_PLLM_RESTRICTED=y
+CONFIG_TEGRA_PREINIT_CLOCKS=y
+CONFIG_TEGRA_PREPOWER_WIFI=y
+CONFIG_TEGRA_SLOW_CSITE=y
+CONFIG_TEGRA_THERMAL_SYSFS=y
+CONFIG_USB_HOTPLUG=y
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_CDCETHER=y
+CONFIG_USB_NET_CDC_NCM=y
+CONFIG_USB_NET_MCS7830=y
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_SMSC95XX=y
+CONFIG_USB_USBNET=y
+CONFIG_VMSPLIT_2G=y
+# CONFIG_VMSPLIT_3G is not set
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
diff --git a/chromeos/config/armel/config.flavour.chromiumos-arm b/chromeos/config/armel/config.flavour.chromiumos-arm
new file mode 100644
index 00000000..3c5ee02
--- /dev/null
+++ b/chromeos/config/armel/config.flavour.chromiumos-arm
@@ -0,0 +1,86 @@
+#
+# Config options generated by splitconfig
+#
+CONFIG_ANDROID_PARANOID_NETWORK=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_ARCH_TEGRA_2x_SOC=y
+# CONFIG_ARCH_TEGRA_3x_SOC is not set
+CONFIG_ARM_ERRATA_716044=y
+# CONFIG_ARM_ERRATA_743622 is not set
+# CONFIG_ARM_ERRATA_751472 is not set
+# CONFIG_ARM_ERRATA_752520 is not set
+# CONFIG_ARM_ERRATA_754322 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_DNS_RESOLVER is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_GIC_SET_MULTIPLE_CPUS is not set
+CONFIG_IPV6=m
+# CONFIG_IP_PNP is not set
+CONFIG_MACH_HARMONY=y
+CONFIG_MACH_KAEN=y
+# CONFIG_MACH_P852 is not set
+# CONFIG_MACH_PAZ00 is not set
+CONFIG_MACH_SEABOARD=y
+# CONFIG_MACH_TRIMSLICE is not set
+# CONFIG_MACH_VENTANA is not set
+CONFIG_MACH_WARIO=y
+# CONFIG_MACH_WHISTLER is not set
+CONFIG_MFD_TPS6586X=y
+# CONFIG_MFD_TPS6591X is not set
+# CONFIG_NEON is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NR_CPUS=2
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_REGULATOR_TPS62360 is not set
+CONFIG_REGULATOR_TPS6586X=y
+# CONFIG_REPORT_PRESENT_CPUS is not set
+CONFIG_RTC_DRV_TPS6586X=y
+# CONFIG_SENSORS_ISL29028 is not set
+# CONFIG_SENSORS_NCT1008 is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_SND_SOC_TEGRA20_DAS=y
+CONFIG_SND_SOC_TEGRA20_I2S=y
+CONFIG_SND_SOC_TEGRA20_SPDIF=y
+# CONFIG_SWAP is not set
+CONFIG_TASK_SIZE=0xBF000000
+CONFIG_TASK_SIZE_3G_LESS_16M=y
+# CONFIG_TASK_SIZE_3G_LESS_24M is not set
+CONFIG_TEGRA_AVP_KERNEL_ON_MMU=y
+# CONFIG_TEGRA_DEBUG_UARTA is not set
+CONFIG_TEGRA_DEBUG_UARTB=y
+# CONFIG_TEGRA_DYNAMIC_PWRDET is not set
+# CONFIG_TEGRA_EDP_LIMITS is not set
+CONFIG_TEGRA_EMC_TO_DDR_CLOCK=2
+# CONFIG_TEGRA_IOMMU_GART is not set
+CONFIG_TEGRA_IOVMM_GART=y
+# CONFIG_TEGRA_PCI is not set
+# CONFIG_TEGRA_PREINIT_CLOCKS is not set
+# CONFIG_TEGRA_PREPOWER_WIFI is not set
+# CONFIG_TEGRA_SLOW_CSITE is not set
+# CONFIG_TEGRA_STAT_MON is not set
+# CONFIG_TEGRA_THERMAL_SYSFS is not set
+# CONFIG_USB_HOTPLUG is not set
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_USBNET=m
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VMSPLIT_2G is not set
+CONFIG_VMSPLIT_3G=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
diff --git a/chromeos/config/config.common.chromeos b/chromeos/config/config.common.chromeos
new file mode 100644
index 00000000..eaea95f
--- /dev/null
+++ b/chromeos/config/config.common.chromeos
@@ -0,0 +1,2039 @@
+#
+# Config options generated by splitconfig
+#
+# CONFIG_ABX500_CORE is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_ACENIC is not set
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_AD2S120X is not set
+# CONFIG_AD2S1210 is not set
+# CONFIG_AD2S90 is not set
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_AD5446 is not set
+# CONFIG_AD5504 is not set
+# CONFIG_AD5624R_SPI is not set
+# CONFIG_AD5686 is not set
+# CONFIG_AD5791 is not set
+# CONFIG_AD5930 is not set
+# CONFIG_AD7150 is not set
+# CONFIG_AD7152 is not set
+# CONFIG_AD7291 is not set
+# CONFIG_AD7298 is not set
+# CONFIG_AD7314 is not set
+# CONFIG_AD7476 is not set
+# CONFIG_AD7606 is not set
+# CONFIG_AD7745 is not set
+# CONFIG_AD7780 is not set
+# CONFIG_AD7793 is not set
+# CONFIG_AD7816 is not set
+# CONFIG_AD7887 is not set
+# CONFIG_AD799X is not set
+# CONFIG_AD9832 is not set
+# CONFIG_AD9834 is not set
+# CONFIG_AD9850 is not set
+# CONFIG_AD9852 is not set
+# CONFIG_AD9910 is not set
+# CONFIG_AD9951 is not set
+# CONFIG_ADE7753 is not set
+# CONFIG_ADE7754 is not set
+# CONFIG_ADE7758 is not set
+# CONFIG_ADE7759 is not set
+# CONFIG_ADE7854 is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADIS16060 is not set
+# CONFIG_ADIS16080 is not set
+# CONFIG_ADIS16130 is not set
+# CONFIG_ADIS16201 is not set
+# CONFIG_ADIS16203 is not set
+# CONFIG_ADIS16204 is not set
+# CONFIG_ADIS16209 is not set
+# CONFIG_ADIS16220 is not set
+# CONFIG_ADIS16240 is not set
+# CONFIG_ADIS16260 is not set
+# CONFIG_ADIS16400 is not set
+# CONFIG_ADM8211 is not set
+# CONFIG_ADT7310 is not set
+# CONFIG_ADT7316 is not set
+# CONFIG_ADT7410 is not set
+# CONFIG_ADT75 is not set
+# CONFIG_ADXRS450 is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_AIO=y
+# CONFIG_ALTERA_STAPL is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ANDROID is not set
+CONFIG_ANON_INODES=y
+# CONFIG_APANIC is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_APPLICOM is not set
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_ARCNET is not set
+# CONFIG_ARPD is not set
+# CONFIG_ASHMEM is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_AT76C50X_USB is not set
+# CONFIG_ATALK is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_ATH9K_HTC is not set
+CONFIG_ATH_COMMON=m
+CONFIG_ATH_DEBUG=y
+# CONFIG_ATM is not set
+# CONFIG_ATMEL is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_AUDIT is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_AVERAGE=y
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_BACKTRACE_SELF_TEST is not set
+CONFIG_BASE_FULL=y
+CONFIG_BASE_SMALL=0
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_BATTERY_MAX17048 is not set
+# CONFIG_BCM4329_RFKILL is not set
+# CONFIG_BCMA is not set
+CONFIG_BCMA_POSSIBLE=y
+# CONFIG_BCM_WIMAX is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_BINARY_PRINTF=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_BITREVERSE=y
+# CONFIG_BLK_CGROUP is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_CPQ_DA is not set
+CONFIG_BLK_DEV=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_DM=y
+# CONFIG_BLK_DEV_DRBD is not set
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+CONFIG_BLK_DEV_IO_TRACE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_RBD is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_UMEM is not set
+CONFIG_BLOCK=y
+# CONFIG_BMP085 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_BONDING is not set
+# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=1
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1
+# CONFIG_BOOT_PRINTK_DELAY is not set
+CONFIG_BOUNCE=y
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_BRIDGE is not set
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_BT=m
+# CONFIG_BTRFS_FS is not set
+# CONFIG_BT_BLUESLEEP is not set
+CONFIG_BT_HCIBFUSB=m
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_HCIVHCI=m
+# CONFIG_BT_L2CAP is not set
+# CONFIG_BT_MRVL is not set
+# CONFIG_BT_SCO is not set
+# CONFIG_BT_TIBLUESLEEP is not set
+CONFIG_BUG=y
+# CONFIG_C2PORT is not set
+# CONFIG_CAIF is not set
+# CONFIG_CAN is not set
+CONFIG_CAN_PM_TRACE=y
+# CONFIG_CARL9170 is not set
+# CONFIG_CASSINI is not set
+# CONFIG_CB710_CORE is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CC_STACKPROTECTOR=y
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_CEPH_LIB is not set
+CONFIG_CFG80211=m
+# CONFIG_CFG80211_ALLOW_RECONNECT is not set
+CONFIG_CFG80211_DEBUGFS=y
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_CPUACCT is not set
+# CONFIG_CGROUP_DEBUG is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_PERF is not set
+CONFIG_CGROUP_SCHED=y
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_SMB349 is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_CLEANCACHE is not set
+# CONFIG_CNIC is not set
+# CONFIG_COMPACTION is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_CONNECTOR=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+# CONFIG_CORDIC is not set
+# CONFIG_CPUSETS is not set
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_GOV_INTERACTIVE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+# CONFIG_CPU_NOTIFIER_ERROR_INJECT is not set
+CONFIG_CPU_RMAP=y
+# CONFIG_CRAMFS is not set
+CONFIG_CRC16=y
+CONFIG_CRC32=y
+CONFIG_CRC7=m
+# CONFIG_CRC8 is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC_T10DIF=m
+CONFIG_CROSS_COMPILE=""
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CCM is not set
+CONFIG_CRYPTO_CRC32C=m
+# CONFIG_CRYPTO_CTR is not set
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_GHASH is not set
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_PCBC is not set
+CONFIG_CRYPTO_PCOMP2=y
+# CONFIG_CRYPTO_PCRYPT is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_RNG2=y
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SEQIV is not set
+# CONFIG_CRYPTO_SERPENT is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=m
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+# CONFIG_CRYPTO_VMAC is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYSTALHD is not set
+# CONFIG_CUSE is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_DCB is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_DEBUG_DEVRES=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_GPIO=y
+# CONFIG_DEBUG_INFO is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DEBUG_SPINLOCK=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DECNET is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DEFAULT_CFQ=y
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=5
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_DEFAULT_NOOP is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_DEVKMEM is not set
+CONFIG_DEVMEM=y
+CONFIG_DEVPORT=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_DL2K is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_DMA_SHARED_BUFFER is not set
+# CONFIG_DM_CRYPT is not set
+# CONFIG_DM_DEBUG is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_RAID is not set
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DNET is not set
+# CONFIG_DS1682 is not set
+# CONFIG_DUMMY is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_DVB_CORE is not set
+# CONFIG_DX_SEP is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+CONFIG_DYNAMIC_FTRACE=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_EASYCAP is not set
+# CONFIG_ECHO is not set
+# CONFIG_ECONET is not set
+CONFIG_ECRYPT_FS=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_EFS_FS is not set
+CONFIG_ELF_CORE=y
+CONFIG_EMBEDDED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_EPOLL=y
+# CONFIG_EQUALIZER is not set
+# CONFIG_ET131X is not set
+# CONFIG_ETHOC is not set
+CONFIG_EVENTFD=y
+CONFIG_EVENT_POWER_TRACING_DEPRECATED=y
+CONFIG_EVENT_TRACING=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_EXPERT=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EZX_PCAP is not set
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_FANOTIFY is not set
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_FAT_FS=m
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_FB=y
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_FB_CARMINE is not set
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_METRONOME is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_SM7XX is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_TILEBLITTING is not set
+# CONFIG_FB_TMIO is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_WMT_GE_ROPS is not set
+# CONFIG_FB_XGI is not set
+# CONFIG_FDDI is not set
+# CONFIG_FHANDLE is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# CONFIG_FIRMWARE_EDID is not set
+CONFIG_FIRMWARE_IN_KERNEL=y
+# CONFIG_FIXED_PHY is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FREEZER=y
+# CONFIG_FSCACHE is not set
+CONFIG_FSNOTIFY=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_FT1000 is not set
+CONFIG_FTRACE=y
+CONFIG_FTRACE_MCOUNT_RECORD=y
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_FUNCTION_PROFILER is not set
+CONFIG_FUNCTION_TRACER=y
+CONFIG_FUSE_FS=m
+# CONFIG_FUSION is not set
+CONFIG_FUTEX=y
+CONFIG_FW_LOADER=y
+# CONFIG_GAMEPORT is not set
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_GENERIC_ACL=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_TRACER=y
+# CONFIG_GFS2_FS is not set
+CONFIG_GPIOLIB=y
+# CONFIG_GPIO_74X164 is not set
+# CONFIG_GPIO_ADP5588 is not set
+# CONFIG_GPIO_BT8XX is not set
+# CONFIG_GPIO_GENERIC_PLATFORM is not set
+# CONFIG_GPIO_IT8761E is not set
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_ML_IOH is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_RDC321X is not set
+# CONFIG_GPIO_SX150X is not set
+CONFIG_GPIO_SYSFS=y
+# CONFIG_GPIO_VX855 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_HAPPYMEAL is not set
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_WORK=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SPARSE_IRQ=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_HERMES is not set
+CONFIG_HFSPLUS_FS=m
+# CONFIG_HFS_FS is not set
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACRUX is not set
+CONFIG_HID_APPLE=m
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_LCPOWER is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MONTEREY is not set
+CONFIG_HID_MULTITOUCH=m
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_SUNPLUS is not set
+CONFIG_HID_SUPPORT=y
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_HIGH_RES_TIMERS=y
+# CONFIG_HIPPI is not set
+# CONFIG_HMC6352 is not set
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+CONFIG_HOTPLUG=y
+CONFIG_HOTPLUG_CPU=y
+# CONFIG_HP100 is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_HWMON_VID is not set
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+CONFIG_I2C=y
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_COMPAT=y
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_EG20T is not set
+# CONFIG_I2C_GPIO is not set
+CONFIG_I2C_HELPER_AUTO=y
+# CONFIG_I2C_INTEL_MID is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_MUX is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_SLAVE is not set
+CONFIG_I2C_STUB=m
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_XILINX is not set
+# CONFIG_I2O is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_IDE is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_IGB is not set
+CONFIG_IIO=m
+# CONFIG_IIO_RING_BUFFER is not set
+# CONFIG_IIO_TRIGGER is not set
+CONFIG_IKCONFIG=m
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_IMA is not set
+CONFIG_INET=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+# CONFIG_INET6_XFRM_TUNNEL is not set
+CONFIG_INET_AH=m
+# CONFIG_INET_DIAG is not set
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_LRO=y
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_TUNNEL=m
+# CONFIG_INFINIBAND is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INIT_ENV_ARG_LIMIT=32
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_INOTIFY_USER=y
+CONFIG_INPUT=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_ALPS_GPIO_SCROLLWHEEL is not set
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_CAPELLA_CM3217 is not set
+# CONFIG_INPUT_CM109 is not set
+# CONFIG_INPUT_CMA3000 is not set
+# CONFIG_INPUT_EVBUG is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_GPIO is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_JOYSTICK is not set
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_INPUT_KEYCHORD is not set
+# CONFIG_INPUT_KEYRESET is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_MMA8450 is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_MPU3050 is not set
+# CONFIG_INPUT_PCF8574 is not set
+CONFIG_INPUT_POLLDEV=y
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_INPUT_UINPUT is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INTEL_MID_PTI is not set
+CONFIG_INV_SENSORS=y
+CONFIG_INV_SENSORS_ACCELEROMETERS=y
+CONFIG_INV_SENSORS_COMPASS=y
+CONFIG_INV_SENSORS_PRESSURE=y
+CONFIG_IOMMU_SUPPORT=y
+# CONFIG_ION is not set
+CONFIG_IOSCHED_CFQ=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IP1000 is not set
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+# CONFIG_IP6_NF_TARGET_REJECT_SKERR is not set
+CONFIG_IPC_NS=y
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_IPV6_PRIVACY=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_IPX is not set
+CONFIG_IP_ADVANCED_ROUTER=y
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_FIB_TRIE_STATS is not set
+CONFIG_IP_MROUTE=y
+# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_IP_NF_TARGET_REJECT=y
+# CONFIG_IP_NF_TARGET_REJECT_SKERR is not set
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_SCTP is not set
+# CONFIG_IP_SET is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IRDA is not set
+# CONFIG_IRQSOFF_TRACER is not set
+CONFIG_IRQ_WORK=y
+# CONFIG_ISDN is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+CONFIG_ISO9660_FS=m
+CONFIG_JBD=y
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_JFS_FS is not set
+CONFIG_JOLIET=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+# CONFIG_KEXEC is not set
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+# CONFIG_KGDB is not set
+# CONFIG_KPROBES is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_KSM is not set
+# CONFIG_KXSD9 is not set
+# CONFIG_L2TP is not set
+# CONFIG_LAPB is not set
+# CONFIG_LCD_CLASS_DEVICE is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_LEDS_BD2802 is not set
+CONFIG_LEDS_CLASS=y
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_GPIO is not set
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_LT3593 is not set
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_PCA955X is not set
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_LIB80211=m
+CONFIG_LIB80211_CRYPT_CCMP=m
+CONFIG_LIB80211_CRYPT_TKIP=m
+CONFIG_LIB80211_CRYPT_WEP=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_LIBCRC32C=m
+# CONFIG_LIBERTAS is not set
+CONFIG_LIBERTAS_THINFIRM=m
+# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
+# CONFIG_LINE6_USB is not set
+# CONFIG_LIS3L02DQ is not set
+# CONFIG_LKDTM is not set
+# CONFIG_LLC2 is not set
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_LOCKUP_DETECTOR=y
+# CONFIG_LOCK_STAT is not set
+# CONFIG_LOGFS is not set
+# CONFIG_LOGO is not set
+CONFIG_LOG_BUF_SHIFT=18
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_LXT_PHY is not set
+CONFIG_MAC80211=m
+CONFIG_MAC80211_DEBUGFS=y
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_HWSIM=m
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL_HT=y
+# CONFIG_MAC80211_RC_PID is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_MAX1363 is not set
+# CONFIG_MAX517 is not set
+CONFIG_MD=y
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_MEDIA_ATTACH is not set
+# CONFIG_MEDIA_CONTROLLER is not set
+CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC4000=m
+CONFIG_MEDIA_TUNER_XC5000=m
+# CONFIG_MEMSTICK is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_MAX77663 is not set
+# CONFIG_MFD_MAX8907C is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_RC5T583 is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_RICOH583 is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_STMPE is not set
+CONFIG_MFD_SUPPORT=y
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TIMBERDALE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_MFD_TPS80031 is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MICREL_PHY is not set
+CONFIG_MII=y
+# CONFIG_MINIX_FS is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_MISC_FILESYSTEMS=y
+CONFIG_MMU=y
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MPU_SENSORS_AK8963 is not set
+# CONFIG_MPU_SENSORS_AK8972 is not set
+# CONFIG_MPU_SENSORS_AK8975 is not set
+# CONFIG_MPU_SENSORS_AMI306 is not set
+# CONFIG_MPU_SENSORS_AMI30X is not set
+# CONFIG_MPU_SENSORS_BMA085 is not set
+# CONFIG_MPU_SENSORS_HMC5883 is not set
+# CONFIG_MPU_SENSORS_HSCDTD002B is not set
+# CONFIG_MPU_SENSORS_HSCDTD004A is not set
+# CONFIG_MPU_SENSORS_LSM303DLX_M is not set
+# CONFIG_MPU_SENSORS_MMC314X is not set
+# CONFIG_MPU_SENSORS_MMC314XMS is not set
+# CONFIG_MPU_SENSORS_MPU3050 is not set
+# CONFIG_MPU_SENSORS_MPU6050A2 is not set
+# CONFIG_MPU_SENSORS_MPU6050B1 is not set
+# CONFIG_MPU_SENSORS_TIMERIRQ is not set
+# CONFIG_MPU_SENSORS_YAS530 is not set
+# CONFIG_MPU_USERSPACE_DEBUG is not set
+# CONFIG_MSDOS_FS is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_MTD is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+# CONFIG_MWIFIEX is not set
+# CONFIG_MWL8K is not set
+CONFIG_NAMESPACES=y
+# CONFIG_NATIONAL_PHY is not set
+CONFIG_NET=y
+# CONFIG_NETCONSOLE is not set
+CONFIG_NETDEVICES=y
+CONFIG_NETDEV_1000=y
+# CONFIG_NETDEV_10000 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_ADVANCED is not set
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_MARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_SECMARK=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+# CONFIG_NETLABEL is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETWORK_SECMARK=y
+# CONFIG_NET_9P is not set
+CONFIG_NET_ACTIVITY_STATS=y
+# CONFIG_NET_CLS_ACT is not set
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_CGROUP is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_DROP_MONITOR is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_NET_EMATCH is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_NET_FC is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_NET_IPIP is not set
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+# CONFIG_NET_NS is not set
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+CONFIG_NET_SCHED=y
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_CHOKE is not set
+# CONFIG_NET_SCH_DRR is not set
+# CONFIG_NET_SCH_DSMARK is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_MQPRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_QFQ is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFB is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_NET_VENDOR_3COM is not set
+CONFIG_NEW_LEDS=y
+# CONFIG_NFC is not set
+CONFIG_NF_CONNTRACK=y
+# CONFIG_NF_CONNTRACK_FTP is not set
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_IPV6=m
+# CONFIG_NF_CONNTRACK_IRC is not set
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+# CONFIG_NF_CONNTRACK_SECMARK is not set
+# CONFIG_NF_CONNTRACK_SIP is not set
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NF_DEFRAG_IPV4=y
+CONFIG_NF_DEFRAG_IPV6=m
+# CONFIG_NF_NAT is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NL80211_TESTMODE=y
+CONFIG_NLATTR=y
+CONFIG_NLS=y
+CONFIG_NLS_ASCII=m
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+CONFIG_NOP_TRACER=y
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_NOZOMI is not set
+CONFIG_NO_HZ=y
+# CONFIG_NS83820 is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_N_GSM is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_OPROFILE is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_P54_COMMON is not set
+CONFIG_PACKET=y
+CONFIG_PANIC_TIMEOUT=0
+# CONFIG_PARPORT is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_PCCARD is not set
+# CONFIG_PCH_GBE is not set
+# CONFIG_PCH_PHUB is not set
+CONFIG_PCI=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_IOV is not set
+CONFIG_PCI_QUIRKS=y
+# CONFIG_PCI_STUB is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_PERF_EVENTS=y
+# CONFIG_PHANTOM is not set
+# CONFIG_PHONE is not set
+# CONFIG_PHONET is not set
+CONFIG_PHYLIB=y
+CONFIG_PID_NS=y
+CONFIG_PM=y
+# CONFIG_PMBUS is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PM_ADVANCED_DEBUG is not set
+CONFIG_PM_DEBUG=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+# CONFIG_PM_TEST_SUSPEND is not set
+# CONFIG_POHMELFS is not set
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_PPP=m
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOLAC is not set
+# CONFIG_PPPOPNS is not set
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPP_DEFLATE is not set
+# CONFIG_PPP_FILTER is not set
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_SYNC_TTY is not set
+# CONFIG_PPS is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_PRINTK=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_PRISM2_USB is not set
+# CONFIG_PRISM54 is not set
+CONFIG_PROC_EVENTS=y
+CONFIG_PROC_FS=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_SYSCTL=y
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+CONFIG_PROFILING=y
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_PSTORE is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+# CONFIG_R3964 is not set
+# CONFIG_R8187SE is not set
+# CONFIG_R8712U is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_RAMOOPS is not set
+# CONFIG_RAW_DRIVER is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_RCU_FAST_NO_HZ is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_TRACE is not set
+# CONFIG_RDS is not set
+# CONFIG_RD_BZIP2 is not set
+CONFIG_RD_GZIP=y
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_REISERFS_FS is not set
+CONFIG_RELAY=y
+# CONFIG_RESOURCE_COUNTERS is not set
+CONFIG_RFKILL=y
+# CONFIG_RFKILL_INPUT is not set
+CONFIG_RFKILL_LEDS=y
+CONFIG_RFKILL_PM=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RING_BUFFER=y
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_RPS=y
+# CONFIG_RT2400PCI is not set
+# CONFIG_RT2500PCI is not set
+# CONFIG_RT2800PCI is not set
+CONFIG_RT2X00=m
+# CONFIG_RT61PCI is not set
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DEBUG is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_TEST is not set
+# CONFIG_RTC_DRV_V3020 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+CONFIG_RTC_INTF_ALARM=y
+CONFIG_RTC_INTF_ALARM_DEV=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_LIB=y
+# CONFIG_RTL8180 is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_RTL8192CU is not set
+# CONFIG_RTL8192DE is not set
+# CONFIG_RTL8192E is not set
+# CONFIG_RTL8192SE is not set
+# CONFIG_RTL8192U is not set
+# CONFIG_RTS_PSTOR is not set
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_SAMPLES is not set
+CONFIG_SCHEDSTATS=y
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHED_TRACER is not set
+CONFIG_SCSI=y
+# CONFIG_SCSI_DH is not set
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_MOD=y
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_SCSI_PROC_FS=y
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+CONFIG_SCSI_SPI_ATTRS=y
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_TGT is not set
+CONFIG_SCSI_WAIT_SCAN=m
+CONFIG_SECCOMP=y
+CONFIG_SECURITY=y
+CONFIG_SECURITYFS=y
+# CONFIG_SECURITY_APPARMOR is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SECURITY_NETWORK=y
+# CONFIG_SECURITY_NETWORK_XFRM is not set
+# CONFIG_SECURITY_PATH is not set
+# CONFIG_SECURITY_TOMOYO is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADS1015 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7461 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_AK8975 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_GPIO_FAN is not set
+# CONFIG_SENSORS_HMC5843 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_INA219 is not set
+# CONFIG_SENSORS_INA230 is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LIS3LV02D is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_LTR558 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_SCH5636 is not set
+# CONFIG_SENSORS_SCH56XX_COMMON is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+CONFIG_SENSORS_TSL2563=m
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+# CONFIG_SERIAL_MFD_HSU is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_SERIAL_PCH_UART is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+CONFIG_SERIO=y
+# CONFIG_SERIO_ALTERA_PS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_PS2MULT is not set
+CONFIG_SERIO_RAW=y
+CONFIG_SERIO_SERPORT=m
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_SGI_PARTITION is not set
+CONFIG_SHMEM=y
+CONFIG_SIGNALFD=y
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+CONFIG_SLABINFO=y
+CONFIG_SLHC=m
+# CONFIG_SLIP is not set
+# CONFIG_SLOB is not set
+CONFIG_SMP=y
+# CONFIG_SMSC_PHY is not set
+CONFIG_SND=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ALOOP is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5535AUDIO is not set
+# CONFIG_SND_CTXFI is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+CONFIG_SND_HRTIMER=m
+CONFIG_SND_HWDEP=m
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_INDIGODJX is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGOIOX is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+CONFIG_SND_JACK=y
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_LOLA is not set
+# CONFIG_SND_LX6464ES is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_MIXART is not set
+CONFIG_SND_MIXER_OSS=m
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+CONFIG_SND_OSSEMUL=y
+# CONFIG_SND_OXYGEN is not set
+CONFIG_SND_PCI=y
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_PCXHR is not set
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_RAWMIDI_SEQ=m
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+# CONFIG_SND_TRIDENT is not set
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_6FIRE is not set
+CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_SOLO6X10 is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+# CONFIG_SOUND_PRIME is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_SPEAKUP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_ALTERA is not set
+CONFIG_SPI_BITBANG=m
+# CONFIG_SPI_DEBUG is not set
+# CONFIG_SPI_DESIGNWARE is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_MASTER=y
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+CONFIG_SPI_SPIDEV=m
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_SPI_TOPCLIFF_PCH is not set
+# CONFIG_SPI_XILINX is not set
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+CONFIG_SSB_POSSIBLE=y
+CONFIG_STACKTRACE=y
+CONFIG_STACKTRACE_SUPPORT=y
+# CONFIG_STACK_TRACER is not set
+CONFIG_STAGING=y
+CONFIG_STANDALONE=y
+# CONFIG_STE10XP is not set
+# CONFIG_STMMAC_ETH is not set
+CONFIG_STOP_MACHINE=y
+# CONFIG_STRICT_DEVMEM is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_STUB_POULSBO is not set
+# CONFIG_ST_GPS is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_SUN_PARTITION is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_SUSPEND_TIME is not set
+# CONFIG_SWITCH is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_SYSCTL=y
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_SYSFS=y
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_TCG_ATMEL is not set
+# CONFIG_TCG_NSC is not set
+CONFIG_TCG_TPM=y
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
+CONFIG_TCP_CONG_CUBIC=y
+# CONFIG_TCP_CONG_HSTCP is not set
+# CONFIG_TCP_CONG_HTCP is not set
+# CONFIG_TCP_CONG_HYBLA is not set
+# CONFIG_TCP_CONG_ILLINOIS is not set
+# CONFIG_TCP_CONG_LP is not set
+# CONFIG_TCP_CONG_SCALABLE is not set
+# CONFIG_TCP_CONG_VEGAS is not set
+# CONFIG_TCP_CONG_VENO is not set
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_YEAH is not set
+CONFIG_TCP_MD5SIG=y
+# CONFIG_TEGRA_CRYPTO_DEV is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_TEST_POWER is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_TICK_ONESHOT=y
+# CONFIG_TIFM_CORE is not set
+CONFIG_TIMERFD=y
+CONFIG_TIMER_STATS=y
+# CONFIG_TIPC is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_TI_ST is not set
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_BU21013 is not set
+# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MAX11801 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_PANJIT_I2C is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_RM31080A is not set
+# CONFIG_TOUCHSCREEN_ST1232 is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
+# CONFIG_TOUCHSCREEN_SYN_RMI4_SPI is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_TR is not set
+# CONFIG_TRACEDUMP is not set
+# CONFIG_TRACELEVEL is not set
+CONFIG_TRACEPOINTS=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_TRACE_SINK is not set
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_TRANZPORT is not set
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_TRUSTED_FOUNDATIONS is not set
+# CONFIG_TRUSTED_KEYS is not set
+# CONFIG_TSL2583 is not set
+# CONFIG_TTY_PRINTK is not set
+CONFIG_TUN=m
+# CONFIG_TWL4030_CORE is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_UFS_FS is not set
+CONFIG_UID16=y
+# CONFIG_UID_STAT is not set
+# CONFIG_UIO is not set
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_UNIX=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_USB=y
+# CONFIG_USBIP_CORE is not set
+CONFIG_USB_ACM=y
+# CONFIG_USB_ADUTUX is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+# CONFIG_USB_APPLEDISPLAY is not set
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_ONOFF_FEATURE is not set
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_ENESTORAGE is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_EZUSB is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_GSPCA is not set
+CONFIG_USB_HID=y
+CONFIG_USB_HIDDEV=y
+# CONFIG_USB_HSO is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_LEGOTOWER is not set
+CONFIG_USB_LIBUSUAL=y
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_NET_CDC_EEM is not set
+# CONFIG_USB_NET_CDC_SUBSET is not set
+# CONFIG_USB_NET_CX82310_ETH is not set
+# CONFIG_USB_NET_GL620A is not set
+# CONFIG_USB_NET_INT51X1 is not set
+# CONFIG_USB_NET_KALMIA is not set
+# CONFIG_USB_NET_PLUSB is not set
+# CONFIG_USB_NET_RAW_IP is not set
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_USB_NET_SMSC75XX is not set
+# CONFIG_USB_NET_ZAURUS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_S2255 is not set
+CONFIG_USB_SERIAL=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BASEBAND is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_CONSOLE is not set
+# CONFIG_USB_SERIAL_CP210X is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+CONFIG_USB_SERIAL_OPTION=m
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_QCAUX is not set
+CONFIG_USB_SERIAL_QUALCOMM=m
+# CONFIG_USB_SERIAL_QUATECH2 is not set
+# CONFIG_USB_SERIAL_QUATECH_USB2 is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_SSU100 is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+CONFIG_USB_SERIAL_WWAN=m
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_ZIO is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_SIERRA_NET is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_STKWEBCAM is not set
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_SWITCH_FSA9480 is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_TMC is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_UAS is not set
+CONFIG_USB_VIDEO_CLASS=m
+# CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV is not set
+# CONFIG_USB_VL600 is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+# CONFIG_USB_XHCI_HCD is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_ZR364XX is not set
+CONFIG_USER_NS=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_UTS_NS=y
+# CONFIG_UWB is not set
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_VETH=m
+CONFIG_VFAT_FS=m
+# CONFIG_VGASTATE is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_VIDEO_ADV7170 is not set
+# CONFIG_VIDEO_ADV7175 is not set
+# CONFIG_VIDEO_ADV7180 is not set
+# CONFIG_VIDEO_ADV7343 is not set
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_AK881X is not set
+# CONFIG_VIDEO_BT819 is not set
+# CONFIG_VIDEO_BT856 is not set
+# CONFIG_VIDEO_BT866 is not set
+# CONFIG_VIDEO_CAFE_CCIC is not set
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_CS5345 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_CX2341X is not set
+# CONFIG_VIDEO_CX25840 is not set
+CONFIG_VIDEO_DEV=m
+# CONFIG_VIDEO_DT3155 is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+# CONFIG_VIDEO_HEXIUM_GEMINI is not set
+# CONFIG_VIDEO_HEXIUM_ORION is not set
+# CONFIG_VIDEO_KS0127 is not set
+# CONFIG_VIDEO_M52790 is not set
+CONFIG_VIDEO_MEDIA=m
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_MT9V011 is not set
+# CONFIG_VIDEO_MXB is not set
+# CONFIG_VIDEO_NOON010PC30 is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_SAA6588 is not set
+# CONFIG_VIDEO_SAA7110 is not set
+# CONFIG_VIDEO_SAA711X is not set
+# CONFIG_VIDEO_SAA7127 is not set
+# CONFIG_VIDEO_SAA7134 is not set
+# CONFIG_VIDEO_SAA717X is not set
+# CONFIG_VIDEO_SAA7185 is not set
+# CONFIG_VIDEO_SAA7191 is not set
+# CONFIG_VIDEO_SR030PC30 is not set
+# CONFIG_VIDEO_TCM825X is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_THS7303 is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+# CONFIG_VIDEO_TVP7002 is not set
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+# CONFIG_VIDEO_USBVISION is not set
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L2_COMMON=m
+# CONFIG_VIDEO_VP27SMPX is not set
+# CONFIG_VIDEO_VPX3220 is not set
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIRTIO_BALLOON is not set
+# CONFIG_VIRT_DRIVERS is not set
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_VME_BUS is not set
+# CONFIG_VMXNET3 is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+# CONFIG_VT6655 is not set
+# CONFIG_VT6656 is not set
+CONFIG_VT_CONSOLE=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_W1 is not set
+# CONFIG_W35UND is not set
+# CONFIG_WAKELOCK is not set
+# CONFIG_WAN is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PRIV=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
+# CONFIG_WIFI_CONTROL_FUNC is not set
+# CONFIG_WIMAX is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+# CONFIG_WIRELESS_EXT_SYSFS is not set
+# CONFIG_WL1251 is not set
+# CONFIG_WL127X_RFKILL is not set
+# CONFIG_WL12XX_MENU is not set
+CONFIG_WLAN=y
+# CONFIG_X25 is not set
+CONFIG_XFRM=y
+CONFIG_XFRM_IPCOMP=m
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFS_FS is not set
+CONFIG_XPS=y
+# CONFIG_XVMALLOC is not set
+# CONFIG_XZ_DEC is not set
+# CONFIG_XZ_DEC_BCJ is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_ZISOFS=y
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_ZLIB_INFLATE=y
+# CONFIG_ZRAM is not set
diff --git a/chromeos/config/i386/config.common.i386 b/chromeos/config/i386/config.common.i386
new file mode 100644
index 00000000..8eb8362
--- /dev/null
+++ b/chromeos/config/i386/config.common.i386
@@ -0,0 +1,749 @@
+#
+# Config options generated by splitconfig
+#
+# CONFIG_64BIT is not set
+# CONFIG_ACERHDF is not set
+# CONFIG_ACER_WMI is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_AC=y
+# CONFIG_ACPI_APEI is not set
+# CONFIG_ACPI_ASUS is not set
+CONFIG_ACPI_BATTERY=y
+CONFIG_ACPI_BLACKLIST_YEAR=0
+CONFIG_ACPI_BUTTON=y
+# CONFIG_ACPI_CMPC is not set
+CONFIG_ACPI_CONTAINER=y
+# CONFIG_ACPI_CUSTOM_DSDT is not set
+# CONFIG_ACPI_CUSTOM_METHOD is not set
+# CONFIG_ACPI_DEBUG is not set
+CONFIG_ACPI_DOCK=y
+# CONFIG_ACPI_EC_DEBUGFS is not set
+CONFIG_ACPI_FAN=y
+# CONFIG_ACPI_HED is not set
+CONFIG_ACPI_HOTPLUG_CPU=y
+# CONFIG_ACPI_PCI_SLOT is not set
+CONFIG_ACPI_PROCESSOR=y
+# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
+CONFIG_ACPI_PROCFS=y
+CONFIG_ACPI_PROCFS_POWER=y
+CONFIG_ACPI_PROC_EVENT=y
+# CONFIG_ACPI_QUICKSTART is not set
+# CONFIG_ACPI_SBS is not set
+CONFIG_ACPI_SLEEP=y
+CONFIG_ACPI_THERMAL=y
+# CONFIG_ACPI_TOSHIBA is not set
+CONFIG_ACPI_VIDEO=y
+# CONFIG_ADAPTEC_STARFIRE is not set
+CONFIG_AGP=y
+# CONFIG_AGP_ALI is not set
+# CONFIG_AGP_AMD is not set
+# CONFIG_AGP_AMD64 is not set
+# CONFIG_AGP_ATI is not set
+# CONFIG_AGP_EFFICEON is not set
+CONFIG_AGP_INTEL=y
+# CONFIG_AGP_NVIDIA is not set
+# CONFIG_AGP_SIS is not set
+# CONFIG_AGP_SWORKS is not set
+# CONFIG_AGP_VIA is not set
+# CONFIG_AIRO is not set
+CONFIG_AMD_NB=y
+CONFIG_ANDROID_PARANOID_NETWORK=y
+# CONFIG_APM is not set
+CONFIG_ARCH_CPU_PROBE_RELEASE=y
+CONFIG_ARCH_DEFCONFIG="arch/x86/configs/i386_defconfig"
+# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
+CONFIG_ARCH_HAS_CPU_RELAX=y
+CONFIG_ARCH_HAS_DEFAULT_IDLE=y
+CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_HWEIGHT_CFLAGS="-fcall-saved-ecx -fcall-saved-edx"
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_ARCH_SUPPORTS_MSI=y
+CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y
+CONFIG_ARCH_USES_PG_UNCACHED=y
+CONFIG_ARCH_WANT_FRAME_POINTERS=y
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_ASUS_LAPTOP is not set
+# CONFIG_ASUS_WMI is not set
+CONFIG_ATA=y
+CONFIG_ATA_ACPI=y
+CONFIG_ATA_BMDMA=y
+CONFIG_ATA_GENERIC=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_PIIX=y
+CONFIG_ATA_SFF=y
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_ATH5K=m
+# CONFIG_ATH5K_DEBUG is not set
+CONFIG_ATH5K_PCI=y
+# CONFIG_ATH5K_TRACER is not set
+CONFIG_ATH9K=m
+# CONFIG_ATH9K_AHB is not set
+CONFIG_ATH9K_COMMON=m
+CONFIG_ATH9K_DEBUGFS=y
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_PCI=y
+CONFIG_ATH9K_RATE_CONTROL=y
+# CONFIG_AUDIT_ARCH is not set
+# CONFIG_BACKLIGHT_APPLE is not set
+# CONFIG_BACKLIGHT_PROGEAR is not set
+# CONFIG_BACKLIGHT_SAHARA is not set
+# CONFIG_BATTERY_BQ20Z75 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BT_ATH3K=m
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+# CONFIG_BT_HCIUART is not set
+# CONFIG_CHARGER_GPIO is not set
+CONFIG_CHECK_SIGNATURE=y
+CONFIG_CLKBLD_I8253=y
+CONFIG_CLKEVT_I8253=y
+CONFIG_CLKSRC_I8253=y
+CONFIG_CLOCKSOURCE_WATCHDOG=y
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_CMPXCHG_DOUBLE=y
+CONFIG_CMPXCHG_LOCAL=y
+# CONFIG_COMEDI is not set
+# CONFIG_COMPAL_LAPTOP is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_COMPAT_VDSO is not set
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+# CONFIG_CPA_DEBUG is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_SUP_AMD=y
+CONFIG_CPU_SUP_CENTAUR=y
+CONFIG_CPU_SUP_CYRIX_32=y
+CONFIG_CPU_SUP_INTEL=y
+CONFIG_CPU_SUP_TRANSMETA_32=y
+CONFIG_CPU_SUP_UMC_32=y
+CONFIG_CRYPTO_AES_586=y
+CONFIG_CRYPTO_AES_NI_INTEL=m
+# CONFIG_CRYPTO_CRC32C_INTEL is not set
+CONFIG_CRYPTO_CRYPTD=m
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_DEV_GEODE is not set
+# CONFIG_CRYPTO_DEV_PADLOCK is not set
+# CONFIG_CRYPTO_SALSA20_586 is not set
+# CONFIG_CRYPTO_TWOFISH_586 is not set
+# CONFIG_DCDBAS is not set
+CONFIG_DEBUG_BOOT_PARAMS=y
+# CONFIG_DEBUG_NX_TEST is not set
+CONFIG_DEBUG_RODATA=y
+# CONFIG_DEBUG_RODATA_TEST is not set
+# CONFIG_DEBUG_SET_MODULE_RONX is not set
+CONFIG_DEBUG_STACKOVERFLOW=y
+# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set
+# CONFIG_DEBUG_VIRTUAL is not set
+CONFIG_DEFAULT_IO_DELAY_TYPE=0
+# CONFIG_DELL_RBU is not set
+CONFIG_DELL_WMI=m
+# CONFIG_DELL_WMI_AIO is not set
+CONFIG_DMI=y
+CONFIG_DMIID=y
+# CONFIG_DMI_SYSFS is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_DNS_RESOLVER is not set
+CONFIG_DOUBLEFAULT=y
+CONFIG_DRM=y
+# CONFIG_DRM_I2C_CH7006 is not set
+# CONFIG_DRM_I2C_SIL164 is not set
+# CONFIG_DRM_I810 is not set
+CONFIG_DRM_I915=y
+CONFIG_DRM_I915_KMS=y
+CONFIG_DRM_KMS_HELPER=y
+# CONFIG_DRM_MGA is not set
+# CONFIG_DRM_PSB is not set
+# CONFIG_DRM_R128 is not set
+# CONFIG_DRM_SAVAGE is not set
+# CONFIG_DRM_SIS is not set
+# CONFIG_DRM_TDFX is not set
+# CONFIG_DRM_VIA is not set
+# CONFIG_DRM_VMWGFX is not set
+CONFIG_E100=m
+CONFIG_E1000=m
+CONFIG_E1000E=m
+CONFIG_EARLY_PRINTK_DBGP=y
+# CONFIG_EDAC is not set
+# CONFIG_EDD is not set
+# CONFIG_EEEPC_LAPTOP is not set
+CONFIG_EFI=y
+# CONFIG_EFI_VARS is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_FB_ARC is not set
+# CONFIG_FB_EFI is not set
+# CONFIG_FB_GEODE is not set
+# CONFIG_FB_HGA is not set
+# CONFIG_FB_I810 is not set
+# CONFIG_FB_LE80578 is not set
+# CONFIG_FB_N411 is not set
+# CONFIG_FB_VESA is not set
+# CONFIG_FB_VGA16 is not set
+# CONFIG_FB_VIA is not set
+# CONFIG_FEALNX is not set
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_FIX_EARLYCON_MEM=y
+# CONFIG_FLATMEM_MANUAL is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FRAME_WARN=2048
+CONFIG_FTRACE_NMI_ENTER=y
+CONFIG_FTRACE_SYSCALLS=y
+# CONFIG_FUJITSU_LAPTOP is not set
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_PENDING_IRQ=y
+# CONFIG_GENERIC_TIME_VSYSCALL is not set
+# CONFIG_GOOGLE_FIRMWARE is not set
+# CONFIG_GPIO_LANGWELL is not set
+# CONFIG_GPIO_PCH is not set
+# CONFIG_GPIO_SCH is not set
+# CONFIG_HANGCHECK_TIMER is not set
+CONFIG_HARDLOCKUP_DETECTOR=y
+CONFIG_HAVE_AOUT=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KMEMCHECK=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_ATOMIC_IOMAP=y
+# CONFIG_HAVE_CPUMASK_OF_CPU_MAP is not set
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_FTRACE_NMI_ENTER=y
+CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
+CONFIG_HAVE_MMIOTRACE_SUPPORT=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_PCSPKR_PLATFORM=y
+CONFIG_HAVE_PERF_EVENTS_NMI=y
+CONFIG_HAVE_SETUP_PER_CPU_AREA=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_TEXT_POKE_SMP=y
+CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
+CONFIG_HAVE_USER_RETURN_NOTIFIER=y
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_PID=y
+# CONFIG_HIGHMEM4G is not set
+# CONFIG_HIGHMEM64G is not set
+CONFIG_HOSTAP_PCI=m
+CONFIG_HOSTAP_PLX=m
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_ACPI is not set
+# CONFIG_HOTPLUG_PCI_COMPAQ is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_FAKE is not set
+# CONFIG_HOTPLUG_PCI_IBM is not set
+CONFIG_HOTPLUG_PCI_PCIE=y
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+CONFIG_HPET=y
+CONFIG_HPET_EMULATE_RTC=y
+# CONFIG_HPET_MMAP is not set
+CONFIG_HPET_TIMER=y
+# CONFIG_HP_ACCEL is not set
+CONFIG_HP_WMI=m
+CONFIG_HT_IRQ=y
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HW_RANDOM_AMD is not set
+# CONFIG_HW_RANDOM_GEODE is not set
+CONFIG_HW_RANDOM_INTEL=y
+# CONFIG_HW_RANDOM_VIA is not set
+# CONFIG_HW_RANDOM_VIRTIO is not set
+# CONFIG_HYPERV is not set
+CONFIG_HZ=1000
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_1000=y
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_300 is not set
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_I801=m
+CONFIG_I2C_PIIX4=m
+# CONFIG_I2C_SCMI is not set
+# CONFIG_I8K is not set
+# CONFIG_IBM_ASM is not set
+# CONFIG_IBM_RTL is not set
+# CONFIG_IDEAPAD_LAPTOP is not set
+# CONFIG_IDE_PHISON is not set
+CONFIG_IGBVF=m
+CONFIG_ILLEGAL_POINTER_VALUE=0
+# CONFIG_INPUT_APANEL is not set
+# CONFIG_INPUT_ATLAS_BTNS is not set
+CONFIG_INPUT_SPARSEKMAP=m
+# CONFIG_INPUT_WISTRON_BTNS is not set
+CONFIG_INSTRUCTION_DECODER=y
+# CONFIG_INTEL_IDLE is not set
+# CONFIG_INTEL_IOMMU is not set
+# CONFIG_INTEL_IPS is not set
+# CONFIG_INTEL_MEI is not set
+CONFIG_INTEL_MENLOW=m
+# CONFIG_INTEL_OAKTRAIL is not set
+# CONFIG_IOMMU_HELPER is not set
+# CONFIG_IOMMU_STRESS is not set
+CONFIG_IO_DELAY_0X80=y
+# CONFIG_IO_DELAY_0XED is not set
+# CONFIG_IO_DELAY_NONE is not set
+CONFIG_IO_DELAY_TYPE_0X80=0
+CONFIG_IO_DELAY_TYPE_0XED=1
+CONFIG_IO_DELAY_TYPE_NONE=3
+CONFIG_IO_DELAY_TYPE_UDELAY=2
+# CONFIG_IO_DELAY_UDELAY is not set
+CONFIG_IPV6=m
+# CONFIG_IP_PNP is not set
+CONFIG_IRQ_FORCED_THREADING=y
+# CONFIG_IRQ_TIME_ACCOUNTING is not set
+# CONFIG_IR_ENE is not set
+# CONFIG_IR_FINTEK is not set
+# CONFIG_IR_IMON is not set
+# CONFIG_IR_ITE_CIR is not set
+# CONFIG_IR_JVC_DECODER is not set
+# CONFIG_IR_LIRC_CODEC is not set
+# CONFIG_IR_MCEUSB is not set
+CONFIG_IR_MCE_KBD_DECODER=m
+# CONFIG_IR_NEC_DECODER is not set
+# CONFIG_IR_NUVOTON is not set
+# CONFIG_IR_RC5_DECODER is not set
+# CONFIG_IR_RC5_SZ_DECODER is not set
+# CONFIG_IR_RC6_DECODER is not set
+# CONFIG_IR_REDRAT3 is not set
+# CONFIG_IR_SONY_DECODER is not set
+# CONFIG_IR_STREAMZAP is not set
+# CONFIG_IR_WINBOND_CIR is not set
+# CONFIG_ISA is not set
+CONFIG_ISA_DMA_API=y
+# CONFIG_ISCSI_IBFT_FIND is not set
+CONFIG_JME=m
+# CONFIG_JUMP_LABEL is not set
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_XZ is not set
+# CONFIG_KSZ884X_PCI is not set
+CONFIG_KTIME_SCALAR=y
+# CONFIG_KVM is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_LBDAF=y
+# CONFIG_LEDS_ALIX2 is not set
+# CONFIG_LEDS_CLEVO_MAIL is not set
+# CONFIG_LEDS_DELL_NETBOOKS is not set
+# CONFIG_LEDS_INTEL_SS4200 is not set
+# CONFIG_LGUEST is not set
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_LIRC=m
+# CONFIG_LIRC_STAGING is not set
+CONFIG_LPC_SCH=m
+# CONFIG_M386 is not set
+# CONFIG_M486 is not set
+# CONFIG_M586 is not set
+# CONFIG_M586MMX is not set
+# CONFIG_M586TSC is not set
+CONFIG_M686=y
+# CONFIG_MACINTOSH_DRIVERS is not set
+# CONFIG_MATH_EMULATION is not set
+# CONFIG_MATOM is not set
+# CONFIG_MCA is not set
+# CONFIG_MCORE2 is not set
+# CONFIG_MCRUSOE is not set
+# CONFIG_MCYRIXIII is not set
+# CONFIG_MEFFICEON is not set
+# CONFIG_MELAN is not set
+# CONFIG_MEMTEST is not set
+CONFIG_MFD_CORE=m
+# CONFIG_MFD_CS5535 is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS6591X is not set
+# CONFIG_MGEODEGX1 is not set
+# CONFIG_MGEODE_LX is not set
+CONFIG_MICROCODE=y
+CONFIG_MICROCODE_AMD=y
+CONFIG_MICROCODE_INTEL=y
+CONFIG_MICROCODE_OLD_INTERFACE=y
+# CONFIG_MK6 is not set
+# CONFIG_MK7 is not set
+# CONFIG_MK8 is not set
+# CONFIG_MMC is not set
+# CONFIG_MMIOTRACE is not set
+CONFIG_MOUSE_APPLETOUCH=m
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_ELANTECH=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MPENTIUM4 is not set
+# CONFIG_MPENTIUMII is not set
+# CONFIG_MPENTIUMIII is not set
+# CONFIG_MPENTIUMM is not set
+# CONFIG_MSI_LAPTOP is not set
+# CONFIG_MSI_WMI is not set
+CONFIG_MTRR=y
+# CONFIG_MTRR_SANITIZER is not set
+# CONFIG_MVIAC3_2 is not set
+# CONFIG_MVIAC7 is not set
+# CONFIG_MWAVE is not set
+# CONFIG_MWINCHIP3D is not set
+# CONFIG_MWINCHIPC6 is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NEED_DMA_MAP_STATE is not set
+CONFIG_NEED_NODE_MEMMAP_SIZE=y
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NET_PCI=y
+# CONFIG_NET_SB1000 is not set
+CONFIG_NOHIGHMEM=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_NR_CPUS=4
+# CONFIG_NSC_GPIO is not set
+CONFIG_NVRAM=y
+CONFIG_OPTIMIZE_INLINING=y
+CONFIG_OUTPUT_FORMAT="elf32-i386"
+CONFIG_PAGE_OFFSET=0x80000000
+# CONFIG_PANASONIC_LAPTOP is not set
+# CONFIG_PARAVIRT_GUEST is not set
+# CONFIG_PATA_ACPI is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CS5535 is not set
+# CONFIG_PATA_CS5536 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PC8736x_GPIO is not set
+CONFIG_PCIEAER=y
+# CONFIG_PCIEAER_INJECT is not set
+CONFIG_PCIEASPM=y
+# CONFIG_PCIEASPM_DEBUG is not set
+CONFIG_PCIEPORTBUS=y
+# CONFIG_PCIE_ECRC is not set
+CONFIG_PCIE_PME=y
+CONFIG_PCI_BIOS=y
+# CONFIG_PCI_CNB20LE_QUIRK is not set
+CONFIG_PCI_DIRECT=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_GOANY=y
+# CONFIG_PCI_GOBIOS is not set
+# CONFIG_PCI_GODIRECT is not set
+# CONFIG_PCI_GOMMCONFIG is not set
+CONFIG_PCI_IOAPIC=y
+CONFIG_PCI_LABEL=y
+CONFIG_PCI_MMCONFIG=y
+CONFIG_PCI_MSI=y
+# CONFIG_PCSPKR_PLATFORM is not set
+# CONFIG_PDC_ADMA is not set
+CONFIG_PHYSICAL_ALIGN=0x200000
+CONFIG_PHYSICAL_START=0x1000000
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PM_TRACE=y
+CONFIG_PM_TRACE_RTC=y
+CONFIG_PNP=y
+CONFIG_PNPACPI=y
+CONFIG_PNP_DEBUG_MESSAGES=y
+# CONFIG_PROCESSOR_SELECT is not set
+CONFIG_PROC_KCORE=y
+CONFIG_PROVIDE_OHCI1394_DMA_INIT=y
+# CONFIG_R6040 is not set
+# CONFIG_RAPIDIO is not set
+CONFIG_RC_CORE=m
+# CONFIG_RC_LOOPBACK is not set
+CONFIG_RC_MAP=m
+CONFIG_REALTEK_AUTOPM=y
+# CONFIG_REGULATOR is not set
+# CONFIG_RELOCATABLE is not set
+# CONFIG_REPORT_PRESENT_CPUS is not set
+CONFIG_RTC_DRV_CMOS=m
+# CONFIG_RTC_HCTOSYS is not set
+# CONFIG_RWSEM_GENERIC_SPINLOCK is not set
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+# CONFIG_SAMSUNG_LAPTOP is not set
+# CONFIG_SAMSUNG_Q10 is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+CONFIG_SATA_AHCI=y
+# CONFIG_SATA_AHCI_PLATFORM is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_SATA_PMP is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIL24 is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SC92031 is not set
+CONFIG_SCHED_HRTICK=y
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_SCHED_SMT=y
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+# CONFIG_SCx200 is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_ABITUGURU3 is not set
+# CONFIG_SENSORS_ACPI_POWER is not set
+# CONFIG_SENSORS_APPLESMC is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATK0110 is not set
+CONFIG_SENSORS_CORETEMP=y
+# CONFIG_SENSORS_FAM15H_POWER is not set
+# CONFIG_SENSORS_FSCHMD is not set
+# CONFIG_SENSORS_HDAPS is not set
+# CONFIG_SENSORS_ISL29018 is not set
+# CONFIG_SENSORS_ISL29028 is not set
+# CONFIG_SENSORS_K10TEMP is not set
+# CONFIG_SENSORS_K8TEMP is not set
+# CONFIG_SENSORS_NCT1008 is not set
+# CONFIG_SENSORS_VIA_CPUTEMP is not set
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIO_CT82C710=m
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_PCIPS2=m
+# CONFIG_SFI is not set
+# CONFIG_SIGMA is not set
+# CONFIG_SIS900 is not set
+# CONFIG_SLAB is not set
+# CONFIG_SLICOSS is not set
+CONFIG_SLUB=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_SMSC9420 is not set
+# CONFIG_SND_ALS4000 is not set
+# CONFIG_SND_ASIHPI is not set
+# CONFIG_SND_CS5530 is not set
+CONFIG_SND_DMA_SGBUF=y
+CONFIG_SND_HDA_CODEC_ANALOG=y
+CONFIG_SND_HDA_CODEC_CA0110=y
+CONFIG_SND_HDA_CODEC_CA0132=y
+CONFIG_SND_HDA_CODEC_CIRRUS=y
+CONFIG_SND_HDA_CODEC_CMEDIA=y
+CONFIG_SND_HDA_CODEC_CONEXANT=y
+CONFIG_SND_HDA_CODEC_HDMI=y
+CONFIG_SND_HDA_CODEC_REALTEK=y
+CONFIG_SND_HDA_CODEC_SI3054=y
+CONFIG_SND_HDA_CODEC_SIGMATEL=y
+CONFIG_SND_HDA_CODEC_VIA=y
+CONFIG_SND_HDA_ENABLE_REALTEK_QUIRKS=y
+CONFIG_SND_HDA_GENERIC=y
+CONFIG_SND_HDA_HWDEP=y
+# CONFIG_SND_HDA_INPUT_BEEP is not set
+CONFIG_SND_HDA_INPUT_JACK=y
+CONFIG_SND_HDA_INTEL=m
+# CONFIG_SND_HDA_PATCH_LOADER is not set
+# CONFIG_SND_HDA_PLATFORM_DRIVER is not set
+CONFIG_SND_HDA_POWER_SAVE=y
+CONFIG_SND_HDA_POWER_SAVE_DEFAULT=5
+CONFIG_SND_HDA_PREALLOC_SIZE=64
+# CONFIG_SND_HDA_RECONFIG is not set
+CONFIG_SND_PCM=m
+# CONFIG_SND_SIS7019 is not set
+# CONFIG_SND_SOC is not set
+CONFIG_SND_TIMER=m
+# CONFIG_SND_USB_US122L is not set
+# CONFIG_SND_USB_USX2Y is not set
+CONFIG_SND_VMASTER=y
+# CONFIG_SOC_CAMERA is not set
+# CONFIG_SONYPI is not set
+# CONFIG_SONY_LAPTOP is not set
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM_STATIC=y
+CONFIG_SPARSE_IRQ=y
+# CONFIG_SPI_PXA2XX is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_SWAP is not set
+# CONFIG_TC1100_WMI is not set
+# CONFIG_TCG_INFINEON is not set
+CONFIG_TCG_TIS=y
+# CONFIG_TELCLOCK is not set
+# CONFIG_THINKPAD_ACPI is not set
+# CONFIG_TLAN is not set
+# CONFIG_TOPSTAR_LAPTOP is not set
+# CONFIG_TOSHIBA is not set
+# CONFIG_TOSHIBA_BT_RFKILL is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TRANSPARENT_HUGEPAGE is not set
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_SMSC95XX=m
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_STORAGE_REALTEK=y
+CONFIG_USB_UHCI_HCD=y
+CONFIG_USB_USBNET=m
+CONFIG_USER_STACKTRACE_SUPPORT=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+# CONFIG_VGA_ARB is not set
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGA_SWITCHEROO is not set
+# CONFIG_VHOST_NET is not set
+# CONFIG_VIDEO_BT848 is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_CX88 is not set
+# CONFIG_VIDEO_GO7007 is not set
+# CONFIG_VIDEO_IR_I2C is not set
+# CONFIG_VIDEO_IVTV is not set
+# CONFIG_VIDEO_TM6000 is not set
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_ZORAN is not set
+CONFIG_VIRTIO=m
+CONFIG_VIRTIO_BLK=m
+# CONFIG_VIRTIO_CONSOLE is not set
+CONFIG_VIRTIO_NET=m
+CONFIG_VIRTIO_PCI=m
+CONFIG_VIRTIO_RING=m
+CONFIG_VIRTUALIZATION=y
+# CONFIG_VM86 is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_VMSPLIT_2G=y
+# CONFIG_VMSPLIT_3G is not set
+# CONFIG_VMWARE_BALLOON is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_X86=y
+CONFIG_X86_32=y
+# CONFIG_X86_32_IRIS is not set
+# CONFIG_X86_32_NON_STANDARD is not set
+CONFIG_X86_32_SMP=y
+# CONFIG_X86_64 is not set
+CONFIG_X86_ACPI_CPUFREQ=y
+# CONFIG_X86_ANCIENT_MCE is not set
+# CONFIG_X86_BIGSMP is not set
+CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y
+CONFIG_X86_BSWAP=y
+CONFIG_X86_CHECK_BIOS_CORRUPTION=y
+CONFIG_X86_CMOV=y
+CONFIG_X86_CMPXCHG=y
+CONFIG_X86_CMPXCHG64=y
+# CONFIG_X86_CPUFREQ_NFORCE2 is not set
+CONFIG_X86_CPUID=y
+CONFIG_X86_DEBUGCTLMSR=y
+CONFIG_X86_EXTENDED_PLATFORM=y
+# CONFIG_X86_E_POWERSAVER is not set
+# CONFIG_X86_GENERIC is not set
+# CONFIG_X86_GX_SUSPMOD is not set
+CONFIG_X86_HT=y
+# CONFIG_X86_INTEL_MID is not set
+CONFIG_X86_INTERNODE_CACHE_SHIFT=5
+CONFIG_X86_INVLPG=y
+CONFIG_X86_IO_APIC=y
+CONFIG_X86_L1_CACHE_SHIFT=5
+CONFIG_X86_LOCAL_APIC=y
+# CONFIG_X86_LONGHAUL is not set
+# CONFIG_X86_LONGRUN is not set
+CONFIG_X86_MCE=y
+# CONFIG_X86_MCE_AMD is not set
+# CONFIG_X86_MCE_INJECT is not set
+CONFIG_X86_MCE_INTEL=y
+CONFIG_X86_MCE_THRESHOLD=y
+CONFIG_X86_MINIMUM_CPU_FAMILY=5
+CONFIG_X86_MPPARSE=y
+CONFIG_X86_MSR=y
+# CONFIG_X86_P4_CLOCKMOD is not set
+CONFIG_X86_PAE=y
+CONFIG_X86_PAT=y
+# CONFIG_X86_PCC_CPUFREQ is not set
+CONFIG_X86_PLATFORM_DEVICES=y
+CONFIG_X86_PM_TIMER=y
+CONFIG_X86_POPAD_OK=y
+# CONFIG_X86_PPRO_FENCE is not set
+# CONFIG_X86_PTDUMP is not set
+# CONFIG_X86_RDC321X is not set
+# CONFIG_X86_REBOOTFIXUPS is not set
+CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
+CONFIG_X86_RESERVE_LOW=64
+# CONFIG_X86_SPEEDSTEP_CENTRINO is not set
+# CONFIG_X86_SPEEDSTEP_ICH is not set
+# CONFIG_X86_SPEEDSTEP_LIB is not set
+# CONFIG_X86_SPEEDSTEP_SMI is not set
+CONFIG_X86_THERMAL_VECTOR=y
+CONFIG_X86_TSC=y
+CONFIG_X86_USE_PPRO_CHECKSUM=y
+CONFIG_X86_VERBOSE_BOOTUP=y
+CONFIG_X86_WP_WORKS_OK=y
+CONFIG_X86_XADD=y
+CONFIG_XFRM_USER=y
+# CONFIG_XO15_EBOOK is not set
+CONFIG_ZONE_DMA=y
+# CONFIG_ZONE_DMA32 is not set
+CONFIG_ZONE_DMA_FLAG=1
diff --git a/chromeos/config/i386/config.flavour.chromeos-intel-menlow b/chromeos/config/i386/config.flavour.chromeos-intel-menlow
new file mode 120000
index 00000000..c867d1c
--- /dev/null
+++ b/chromeos/config/i386/config.flavour.chromeos-intel-menlow
@@ -0,0 +1 @@
+config.flavour.chromeos-pinetrail-i386 \ No newline at end of file
diff --git a/chromeos/config/i386/config.flavour.chromeos-pinetrail-i386 b/chromeos/config/i386/config.flavour.chromeos-pinetrail-i386
new file mode 100644
index 00000000..9a9d299
--- /dev/null
+++ b/chromeos/config/i386/config.flavour.chromeos-pinetrail-i386
@@ -0,0 +1,41 @@
+#
+# Config options generated by splitconfig
+#
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+CONFIG_ACPI_WMI=m
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1C is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL2 is not set
+# CONFIG_B44 is not set
+# CONFIG_BRCMSMAC is not set
+# CONFIG_BRCMUTIL is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_DRM_NOUVEAU is not set
+# CONFIG_DRM_RADEON is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_IWL3945 is not set
+# CONFIG_IWL4965 is not set
+# CONFIG_IWLAGN is not set
+# CONFIG_MXM_WMI is not set
+# CONFIG_PCNET32 is not set
+# CONFIG_R8169 is not set
+# CONFIG_RT2500USB is not set
+# CONFIG_RT2800USB is not set
+# CONFIG_RT73USB is not set
+CONFIG_RTL8192CE=m
+CONFIG_RTL8192C_COMMON=m
+CONFIG_RTLWIFI=m
+# CONFIG_SKY2 is not set
+# CONFIG_SSB is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_X86_POWERNOW_K6 is not set
+# CONFIG_X86_POWERNOW_K7 is not set
+# CONFIG_X86_POWERNOW_K8 is not set
+# CONFIG_ZD1211RW is not set
diff --git a/chromeos/config/i386/config.flavour.chromiumos-i386 b/chromeos/config/i386/config.flavour.chromiumos-i386
new file mode 100644
index 00000000..244efff
--- /dev/null
+++ b/chromeos/config/i386/config.flavour.chromiumos-i386
@@ -0,0 +1,85 @@
+#
+# Config options generated by splitconfig
+#
+CONFIG_8139CP=m
+CONFIG_8139TOO=m
+# CONFIG_8139TOO_8129 is not set
+CONFIG_8139TOO_PIO=y
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+CONFIG_ACPI_WMI=y
+CONFIG_AMD8111_ETH=m
+CONFIG_ATL1=m
+CONFIG_ATL1C=m
+CONFIG_ATL1E=m
+CONFIG_ATL2=m
+CONFIG_B44=m
+CONFIG_B44_PCI=y
+CONFIG_B44_PCICORE_AUTOSELECT=y
+CONFIG_B44_PCI_AUTOSELECT=y
+# CONFIG_BRCMDBG is not set
+CONFIG_BRCMSMAC=m
+CONFIG_BRCMUTIL=m
+CONFIG_BROADCOM_PHY=y
+CONFIG_DRM_NOUVEAU=y
+CONFIG_DRM_NOUVEAU_BACKLIGHT=y
+# CONFIG_DRM_NOUVEAU_DEBUG is not set
+CONFIG_DRM_RADEON=y
+CONFIG_DRM_RADEON_KMS=y
+CONFIG_DRM_TTM=y
+CONFIG_EXTRA_FIRMWARE="radeon/PALM_me.bin radeon/PALM_pfp.bin radeon/SUMO_rlc.bin"
+CONFIG_EXTRA_FIRMWARE_DIR="firmware"
+CONFIG_FB_BACKLIGHT=y
+CONFIG_FORCEDETH=m
+CONFIG_IWL3945=m
+CONFIG_IWL4965=m
+CONFIG_IWLAGN=m
+# CONFIG_IWLWIFI_DEBUG is not set
+# CONFIG_IWLWIFI_DEBUGFS is not set
+# CONFIG_IWLWIFI_DEVICE_SVTOOL is not set
+# CONFIG_IWLWIFI_DEVICE_TRACING is not set
+CONFIG_IWLWIFI_LEGACY=m
+# CONFIG_IWLWIFI_LEGACY_DEBUG is not set
+# CONFIG_IWLWIFI_LEGACY_DEBUGFS is not set
+# CONFIG_IWLWIFI_LEGACY_DEVICE_TRACING is not set
+# CONFIG_IWL_P2P is not set
+CONFIG_MXM_WMI=y
+CONFIG_PCNET32=m
+CONFIG_R8169=m
+CONFIG_RT2500USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+# CONFIG_RT2800USB_RT53XX is not set
+# CONFIG_RT2800USB_UNKNOWN is not set
+CONFIG_RT2800_LIB=m
+# CONFIG_RT2X00_DEBUG is not set
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_CRYPTO=y
+# CONFIG_RT2X00_LIB_DEBUGFS is not set
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_LEDS=y
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT73USB=m
+# CONFIG_RTL8192CE is not set
+CONFIG_SKY2=m
+# CONFIG_SKY2_DEBUG is not set
+CONFIG_SSB=m
+# CONFIG_SSB_B43_PCI_BRIDGE is not set
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_DRIVER_PCICORE=y
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+# CONFIG_SSB_SILENT is not set
+CONFIG_SSB_SPROM=y
+CONFIG_TIGON3=m
+CONFIG_USB_RTL8150=m
+CONFIG_VIA_RHINE=m
+# CONFIG_VIA_RHINE_MMIO is not set
+CONFIG_X86_POWERNOW_K6=y
+CONFIG_X86_POWERNOW_K7=y
+CONFIG_X86_POWERNOW_K7_ACPI=y
+CONFIG_X86_POWERNOW_K8=y
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
diff --git a/chromeos/config/x86_64/config.common.x86_64 b/chromeos/config/x86_64/config.common.x86_64
new file mode 100644
index 00000000..ab17b2e
--- /dev/null
+++ b/chromeos/config/x86_64/config.common.x86_64
@@ -0,0 +1,740 @@
+#
+# Config options generated by splitconfig
+#
+CONFIG_64BIT=y
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_ACERHDF is not set
+# CONFIG_ACER_WMI is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_AC=y
+# CONFIG_ACPI_APEI is not set
+# CONFIG_ACPI_ASUS is not set
+CONFIG_ACPI_BATTERY=y
+CONFIG_ACPI_BLACKLIST_YEAR=0
+CONFIG_ACPI_BUTTON=y
+# CONFIG_ACPI_CMPC is not set
+CONFIG_ACPI_CONTAINER=y
+# CONFIG_ACPI_CUSTOM_DSDT is not set
+# CONFIG_ACPI_CUSTOM_METHOD is not set
+# CONFIG_ACPI_DEBUG is not set
+CONFIG_ACPI_DOCK=y
+# CONFIG_ACPI_EC_DEBUGFS is not set
+CONFIG_ACPI_FAN=y
+# CONFIG_ACPI_HED is not set
+CONFIG_ACPI_HOTPLUG_CPU=y
+# CONFIG_ACPI_PCI_SLOT is not set
+CONFIG_ACPI_PROCESSOR=y
+# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
+CONFIG_ACPI_PROCFS=y
+CONFIG_ACPI_PROCFS_POWER=y
+CONFIG_ACPI_PROC_EVENT=y
+# CONFIG_ACPI_QUICKSTART is not set
+# CONFIG_ACPI_SBS is not set
+CONFIG_ACPI_SLEEP=y
+CONFIG_ACPI_THERMAL=y
+# CONFIG_ACPI_TOSHIBA is not set
+CONFIG_ACPI_VIDEO=y
+CONFIG_ACPI_WMI=m
+# CONFIG_ADAPTEC_STARFIRE is not set
+CONFIG_AGP=y
+# CONFIG_AGP_AMD64 is not set
+CONFIG_AGP_INTEL=y
+# CONFIG_AGP_SIS is not set
+# CONFIG_AGP_VIA is not set
+# CONFIG_AIRO is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_AMD_IOMMU is not set
+CONFIG_AMD_NB=y
+CONFIG_ANDROID_PARANOID_NETWORK=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_CPU_PROBE_RELEASE=y
+CONFIG_ARCH_DEFCONFIG="arch/x86/configs/x86_64_defconfig"
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
+CONFIG_ARCH_HAS_CPU_RELAX=y
+CONFIG_ARCH_HAS_DEFAULT_IDLE=y
+CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_HWEIGHT_CFLAGS="-fcall-saved-rdi -fcall-saved-rsi -fcall-saved-rdx -fcall-saved-rcx -fcall-saved-r8 -fcall-saved-r9 -fcall-saved-r10 -fcall-saved-r11"
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
+CONFIG_ARCH_SUPPORTS_MSI=y
+CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y
+CONFIG_ARCH_USES_PG_UNCACHED=y
+CONFIG_ARCH_WANT_FRAME_POINTERS=y
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_ASUS_LAPTOP is not set
+# CONFIG_ASUS_WMI is not set
+CONFIG_ATA=y
+CONFIG_ATA_ACPI=y
+CONFIG_ATA_BMDMA=y
+CONFIG_ATA_GENERIC=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_PIIX=y
+CONFIG_ATA_SFF=y
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_ATH5K=m
+# CONFIG_ATH5K_DEBUG is not set
+CONFIG_ATH5K_PCI=y
+# CONFIG_ATH5K_TRACER is not set
+CONFIG_ATH9K=m
+# CONFIG_ATH9K_AHB is not set
+CONFIG_ATH9K_COMMON=m
+CONFIG_ATH9K_DEBUGFS=y
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_PCI=y
+CONFIG_ATH9K_RATE_CONTROL=y
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1C is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL2 is not set
+CONFIG_AUDIT_ARCH=y
+# CONFIG_B44 is not set
+# CONFIG_BACKLIGHT_APPLE is not set
+# CONFIG_BACKLIGHT_PROGEAR is not set
+# CONFIG_BACKLIGHT_SAHARA is not set
+# CONFIG_BATTERY_BQ20Z75 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLOCK_COMPAT=y
+# CONFIG_BPF_JIT is not set
+# CONFIG_BRCMSMAC is not set
+# CONFIG_BRCMUTIL is not set
+# CONFIG_BROADCOM_PHY is not set
+CONFIG_BT_ATH3K=m
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+# CONFIG_BT_HCIUART is not set
+# CONFIG_CALGARY_IOMMU is not set
+# CONFIG_CHARGER_GPIO is not set
+CONFIG_CHECK_SIGNATURE=y
+CONFIG_CLKBLD_I8253=y
+CONFIG_CLKEVT_I8253=y
+CONFIG_CLOCKSOURCE_WATCHDOG=y
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_CMPXCHG_DOUBLE=y
+CONFIG_CMPXCHG_LOCAL=y
+# CONFIG_COMEDI is not set
+# CONFIG_COMPAL_LAPTOP is not set
+CONFIG_COMPAT=y
+CONFIG_COMPAT_BINFMT_ELF=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_COMPAT_FOR_U64_ALIGNMENT=y
+CONFIG_COMPAT_NETLINK_MESSAGES=y
+# CONFIG_COMPAT_VDSO is not set
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+# CONFIG_CPA_DEBUG is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_SUP_AMD=y
+CONFIG_CPU_SUP_CENTAUR=y
+CONFIG_CPU_SUP_INTEL=y
+# CONFIG_CRASH_DUMP is not set
+CONFIG_CRYPTO_AES_NI_INTEL=m
+CONFIG_CRYPTO_AES_X86_64=m
+# CONFIG_CRYPTO_CRC32C_INTEL is not set
+CONFIG_CRYPTO_CRYPTD=m
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_DEV_PADLOCK is not set
+# CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set
+# CONFIG_CRYPTO_SALSA20_X86_64 is not set
+# CONFIG_CRYPTO_TWOFISH_X86_64 is not set
+# CONFIG_DCDBAS is not set
+CONFIG_DEBUG_BOOT_PARAMS=y
+# CONFIG_DEBUG_NX_TEST is not set
+CONFIG_DEBUG_RODATA=y
+# CONFIG_DEBUG_RODATA_TEST is not set
+# CONFIG_DEBUG_SET_MODULE_RONX is not set
+CONFIG_DEBUG_STACKOVERFLOW=y
+# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set
+# CONFIG_DEBUG_VIRTUAL is not set
+CONFIG_DEFAULT_IO_DELAY_TYPE=0
+# CONFIG_DELL_RBU is not set
+CONFIG_DELL_WMI=m
+# CONFIG_DELL_WMI_AIO is not set
+CONFIG_DIRECT_GBPAGES=y
+CONFIG_DMI=y
+CONFIG_DMIID=y
+# CONFIG_DMI_SYSFS is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_DNS_RESOLVER is not set
+CONFIG_DRM=y
+# CONFIG_DRM_I2C_CH7006 is not set
+# CONFIG_DRM_I2C_SIL164 is not set
+# CONFIG_DRM_I810 is not set
+CONFIG_DRM_I915=y
+CONFIG_DRM_I915_KMS=y
+CONFIG_DRM_KMS_HELPER=y
+# CONFIG_DRM_MGA is not set
+# CONFIG_DRM_NOUVEAU is not set
+# CONFIG_DRM_PSB is not set
+# CONFIG_DRM_R128 is not set
+# CONFIG_DRM_RADEON is not set
+# CONFIG_DRM_SAVAGE is not set
+# CONFIG_DRM_SIS is not set
+# CONFIG_DRM_TDFX is not set
+# CONFIG_DRM_VIA is not set
+# CONFIG_DRM_VMWGFX is not set
+CONFIG_E100=m
+CONFIG_E1000=m
+CONFIG_E1000E=m
+CONFIG_EARLY_PRINTK_DBGP=y
+# CONFIG_EDAC is not set
+# CONFIG_EDD is not set
+# CONFIG_EEEPC_LAPTOP is not set
+CONFIG_EFI=y
+# CONFIG_EFI_VARS is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_EPIC100 is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_FB_ARC is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_EFI is not set
+# CONFIG_FB_GEODE is not set
+# CONFIG_FB_HGA is not set
+# CONFIG_FB_LE80578 is not set
+# CONFIG_FB_N411 is not set
+# CONFIG_FB_VESA is not set
+# CONFIG_FB_VGA16 is not set
+# CONFIG_FB_VIA is not set
+# CONFIG_FEALNX is not set
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_FIX_EARLYCON_MEM=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+# CONFIG_FORCEDETH is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FRAME_WARN=2048
+CONFIG_FTRACE_NMI_ENTER=y
+CONFIG_FTRACE_SYSCALLS=y
+# CONFIG_FUJITSU_LAPTOP is not set
+CONFIG_FUNCTION_GRAPH_TRACER=y
+CONFIG_GART_IOMMU=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_PENDING_IRQ=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+# CONFIG_GOOGLE_FIRMWARE is not set
+# CONFIG_GPIO_LANGWELL is not set
+# CONFIG_GPIO_PCH is not set
+# CONFIG_GPIO_SCH is not set
+# CONFIG_HANGCHECK_TIMER is not set
+CONFIG_HARDLOCKUP_DETECTOR=y
+# CONFIG_HAVE_AOUT is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KMEMCHECK=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_BPF_JIT=y
+CONFIG_HAVE_CPUMASK_OF_CPU_MAP=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_FTRACE_NMI_ENTER=y
+CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
+CONFIG_HAVE_MMIOTRACE_SUPPORT=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_PCSPKR_PLATFORM=y
+CONFIG_HAVE_PERF_EVENTS_NMI=y
+CONFIG_HAVE_SETUP_PER_CPU_AREA=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_TEXT_POKE_SMP=y
+CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
+CONFIG_HAVE_USER_RETURN_NOTIFIER=y
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_PID=y
+CONFIG_HOSTAP_PCI=m
+CONFIG_HOSTAP_PLX=m
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_ACPI is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_FAKE is not set
+CONFIG_HOTPLUG_PCI_PCIE=y
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+CONFIG_HPET=y
+CONFIG_HPET_EMULATE_RTC=y
+# CONFIG_HPET_MMAP is not set
+CONFIG_HPET_TIMER=y
+# CONFIG_HP_ACCEL is not set
+CONFIG_HP_WMI=m
+CONFIG_HT_IRQ=y
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HW_RANDOM_AMD is not set
+CONFIG_HW_RANDOM_INTEL=y
+# CONFIG_HW_RANDOM_VIA is not set
+# CONFIG_HW_RANDOM_VIRTIO is not set
+# CONFIG_HYPERV is not set
+CONFIG_HZ=1000
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_1000=y
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_300 is not set
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_I801=m
+CONFIG_I2C_PIIX4=m
+# CONFIG_I2C_SCMI is not set
+# CONFIG_I7300_IDLE is not set
+# CONFIG_I8K is not set
+# CONFIG_IA32_AOUT is not set
+CONFIG_IA32_EMULATION=y
+# CONFIG_IBM_ASM is not set
+# CONFIG_IBM_RTL is not set
+# CONFIG_IDEAPAD_LAPTOP is not set
+# CONFIG_IDE_PHISON is not set
+CONFIG_IGBVF=m
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+# CONFIG_INPUT_APANEL is not set
+# CONFIG_INPUT_ATLAS_BTNS is not set
+CONFIG_INPUT_SPARSEKMAP=m
+CONFIG_INSTRUCTION_DECODER=y
+# CONFIG_INTEL_IDLE is not set
+# CONFIG_INTEL_IOMMU is not set
+# CONFIG_INTEL_IPS is not set
+# CONFIG_INTEL_MEI is not set
+CONFIG_INTEL_MENLOW=m
+# CONFIG_INTEL_OAKTRAIL is not set
+# CONFIG_IOMMU_DEBUG is not set
+CONFIG_IOMMU_HELPER=y
+# CONFIG_IOMMU_STRESS is not set
+CONFIG_IO_DELAY_0X80=y
+# CONFIG_IO_DELAY_0XED is not set
+# CONFIG_IO_DELAY_NONE is not set
+CONFIG_IO_DELAY_TYPE_0X80=0
+CONFIG_IO_DELAY_TYPE_0XED=1
+CONFIG_IO_DELAY_TYPE_NONE=3
+CONFIG_IO_DELAY_TYPE_UDELAY=2
+# CONFIG_IO_DELAY_UDELAY is not set
+CONFIG_IPV6=m
+# CONFIG_IP_PNP is not set
+CONFIG_IRQ_FORCED_THREADING=y
+# CONFIG_IRQ_REMAP is not set
+# CONFIG_IRQ_TIME_ACCOUNTING is not set
+# CONFIG_IR_ENE is not set
+# CONFIG_IR_FINTEK is not set
+# CONFIG_IR_IMON is not set
+# CONFIG_IR_ITE_CIR is not set
+# CONFIG_IR_JVC_DECODER is not set
+# CONFIG_IR_LIRC_CODEC is not set
+# CONFIG_IR_MCEUSB is not set
+CONFIG_IR_MCE_KBD_DECODER=m
+# CONFIG_IR_NEC_DECODER is not set
+# CONFIG_IR_NUVOTON is not set
+# CONFIG_IR_RC5_DECODER is not set
+# CONFIG_IR_RC5_SZ_DECODER is not set
+# CONFIG_IR_RC6_DECODER is not set
+# CONFIG_IR_REDRAT3 is not set
+# CONFIG_IR_SONY_DECODER is not set
+# CONFIG_IR_STREAMZAP is not set
+# CONFIG_IR_WINBOND_CIR is not set
+CONFIG_ISA_DMA_API=y
+# CONFIG_ISCSI_IBFT_FIND is not set
+CONFIG_IWL3945=m
+CONFIG_IWL4965=m
+CONFIG_IWLAGN=m
+# CONFIG_IWLWIFI_DEBUG is not set
+# CONFIG_IWLWIFI_DEBUGFS is not set
+# CONFIG_IWLWIFI_DEVICE_SVTOOL is not set
+# CONFIG_IWLWIFI_DEVICE_TRACING is not set
+CONFIG_IWLWIFI_LEGACY=m
+# CONFIG_IWLWIFI_LEGACY_DEBUG is not set
+# CONFIG_IWLWIFI_LEGACY_DEBUGFS is not set
+# CONFIG_IWLWIFI_LEGACY_DEVICE_TRACING is not set
+# CONFIG_IWL_P2P is not set
+CONFIG_JME=m
+# CONFIG_JUMP_LABEL is not set
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_XZ is not set
+CONFIG_KEYS_COMPAT=y
+# CONFIG_KSZ884X_PCI is not set
+# CONFIG_KTIME_SCALAR is not set
+# CONFIG_KVM is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_LEDS_ALIX2 is not set
+# CONFIG_LEDS_CLEVO_MAIL is not set
+# CONFIG_LEDS_DELL_NETBOOKS is not set
+# CONFIG_LEDS_INTEL_SS4200 is not set
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_LIRC=m
+# CONFIG_LIRC_STAGING is not set
+CONFIG_LPC_SCH=m
+# CONFIG_MACINTOSH_DRIVERS is not set
+# CONFIG_MATOM is not set
+# CONFIG_MAXSMP is not set
+# CONFIG_MCORE2 is not set
+# CONFIG_MEMORY_FAILURE is not set
+# CONFIG_MEMORY_HOTPLUG is not set
+# CONFIG_MEMTEST is not set
+CONFIG_MFD_CORE=m
+# CONFIG_MFD_CS5535 is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS6591X is not set
+CONFIG_MICROCODE=y
+CONFIG_MICROCODE_AMD=y
+CONFIG_MICROCODE_INTEL=y
+CONFIG_MICROCODE_OLD_INTERFACE=y
+# CONFIG_MK8 is not set
+# CONFIG_MMC is not set
+# CONFIG_MMIOTRACE is not set
+CONFIG_MOUSE_APPLETOUCH=m
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_ELANTECH=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MPSC is not set
+# CONFIG_MSI_LAPTOP is not set
+# CONFIG_MSI_WMI is not set
+CONFIG_MTRR=y
+# CONFIG_MTRR_SANITIZER is not set
+# CONFIG_MWAVE is not set
+# CONFIG_MXM_WMI is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NET_PCI=y
+# CONFIG_NET_SB1000 is not set
+CONFIG_NO_BOOTMEM=y
+CONFIG_NR_CPUS=4
+# CONFIG_NUMA is not set
+CONFIG_NVRAM=y
+CONFIG_OPTIMIZE_INLINING=y
+CONFIG_OUTPUT_FORMAT="elf64-x86-64"
+CONFIG_PAGEFLAGS_EXTENDED=y
+# CONFIG_PANASONIC_LAPTOP is not set
+# CONFIG_PARAVIRT_GUEST is not set
+# CONFIG_PATA_ACPI is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CS5536 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+CONFIG_PCIEAER=y
+# CONFIG_PCIEAER_INJECT is not set
+CONFIG_PCIEASPM=y
+# CONFIG_PCIEASPM_DEBUG is not set
+CONFIG_PCIEPORTBUS=y
+# CONFIG_PCIE_ECRC is not set
+CONFIG_PCIE_PME=y
+# CONFIG_PCI_CNB20LE_QUIRK is not set
+CONFIG_PCI_DIRECT=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_IOAPIC=y
+CONFIG_PCI_LABEL=y
+CONFIG_PCI_MMCONFIG=y
+CONFIG_PCI_MSI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_PCSPKR_PLATFORM is not set
+# CONFIG_PDC_ADMA is not set
+CONFIG_PHYSICAL_ALIGN=0x1000000
+CONFIG_PHYSICAL_START=0x1000000
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PM_TRACE=y
+CONFIG_PM_TRACE_RTC=y
+CONFIG_PNP=y
+CONFIG_PNPACPI=y
+CONFIG_PNP_DEBUG_MESSAGES=y
+# CONFIG_PROCESSOR_SELECT is not set
+CONFIG_PROC_KCORE=y
+CONFIG_PROVIDE_OHCI1394_DMA_INIT=y
+# CONFIG_R6040 is not set
+# CONFIG_R8169 is not set
+# CONFIG_RAPIDIO is not set
+CONFIG_RC_CORE=m
+# CONFIG_RC_LOOPBACK is not set
+CONFIG_RC_MAP=m
+CONFIG_REALTEK_AUTOPM=y
+# CONFIG_REGULATOR is not set
+# CONFIG_RELOCATABLE is not set
+# CONFIG_REPORT_PRESENT_CPUS is not set
+# CONFIG_RT2500USB is not set
+# CONFIG_RT2800USB is not set
+# CONFIG_RT73USB is not set
+CONFIG_RTC_DRV_CMOS=m
+# CONFIG_RTC_HCTOSYS is not set
+CONFIG_RTL8192CE=m
+CONFIG_RTL8192C_COMMON=m
+CONFIG_RTLWIFI=m
+# CONFIG_RWSEM_GENERIC_SPINLOCK is not set
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+# CONFIG_SAMSUNG_LAPTOP is not set
+# CONFIG_SAMSUNG_Q10 is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+CONFIG_SATA_AHCI=y
+# CONFIG_SATA_AHCI_PLATFORM is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_SATA_PMP is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIL24 is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SC92031 is not set
+CONFIG_SCHED_HRTICK=y
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_SCHED_SMT=y
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_ABITUGURU3 is not set
+# CONFIG_SENSORS_ACPI_POWER is not set
+# CONFIG_SENSORS_APPLESMC is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATK0110 is not set
+CONFIG_SENSORS_CORETEMP=y
+# CONFIG_SENSORS_FAM15H_POWER is not set
+# CONFIG_SENSORS_FSCHMD is not set
+# CONFIG_SENSORS_HDAPS is not set
+# CONFIG_SENSORS_ISL29018 is not set
+# CONFIG_SENSORS_ISL29028 is not set
+# CONFIG_SENSORS_K10TEMP is not set
+# CONFIG_SENSORS_K8TEMP is not set
+# CONFIG_SENSORS_NCT1008 is not set
+# CONFIG_SENSORS_VIA_CPUTEMP is not set
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIO_CT82C710=m
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_PCIPS2=m
+# CONFIG_SFI is not set
+# CONFIG_SIGMA is not set
+# CONFIG_SIS900 is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SLAB is not set
+# CONFIG_SLICOSS is not set
+CONFIG_SLUB=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_SMSC9420 is not set
+# CONFIG_SND_ALS4000 is not set
+# CONFIG_SND_ASIHPI is not set
+# CONFIG_SND_CS5530 is not set
+CONFIG_SND_DMA_SGBUF=y
+CONFIG_SND_HDA_CODEC_ANALOG=y
+CONFIG_SND_HDA_CODEC_CA0110=y
+CONFIG_SND_HDA_CODEC_CA0132=y
+CONFIG_SND_HDA_CODEC_CIRRUS=y
+CONFIG_SND_HDA_CODEC_CMEDIA=y
+CONFIG_SND_HDA_CODEC_CONEXANT=y
+CONFIG_SND_HDA_CODEC_HDMI=y
+CONFIG_SND_HDA_CODEC_REALTEK=y
+CONFIG_SND_HDA_CODEC_SI3054=y
+CONFIG_SND_HDA_CODEC_SIGMATEL=y
+CONFIG_SND_HDA_CODEC_VIA=y
+CONFIG_SND_HDA_ENABLE_REALTEK_QUIRKS=y
+CONFIG_SND_HDA_GENERIC=y
+CONFIG_SND_HDA_HWDEP=y
+# CONFIG_SND_HDA_INPUT_BEEP is not set
+CONFIG_SND_HDA_INPUT_JACK=y
+CONFIG_SND_HDA_INTEL=m
+# CONFIG_SND_HDA_PATCH_LOADER is not set
+# CONFIG_SND_HDA_PLATFORM_DRIVER is not set
+CONFIG_SND_HDA_POWER_SAVE=y
+CONFIG_SND_HDA_POWER_SAVE_DEFAULT=5
+CONFIG_SND_HDA_PREALLOC_SIZE=64
+# CONFIG_SND_HDA_RECONFIG is not set
+CONFIG_SND_PCM=m
+# CONFIG_SND_SOC is not set
+CONFIG_SND_TIMER=m
+# CONFIG_SND_USB_US122L is not set
+# CONFIG_SND_USB_USX2Y is not set
+CONFIG_SND_VMASTER=y
+# CONFIG_SOC_CAMERA is not set
+# CONFIG_SONY_LAPTOP is not set
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_ALLOC_MEM_MAP_TOGETHER=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_SSB is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_SWAP is not set
+CONFIG_SWIOTLB=y
+CONFIG_SYSVIPC_COMPAT=y
+# CONFIG_TCG_INFINEON is not set
+CONFIG_TCG_TIS=y
+# CONFIG_TELCLOCK is not set
+# CONFIG_THINKPAD_ACPI is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_TLAN is not set
+# CONFIG_TOPSTAR_LAPTOP is not set
+# CONFIG_TOSHIBA_BT_RFKILL is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TRANSPARENT_HUGEPAGE is not set
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_SMSC95XX=m
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_RTL8150 is not set
+CONFIG_USB_STORAGE_REALTEK=y
+CONFIG_USB_UHCI_HCD=y
+CONFIG_USB_USBNET=m
+CONFIG_USER_STACKTRACE_SUPPORT=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+# CONFIG_VGA_ARB is not set
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGA_SWITCHEROO is not set
+# CONFIG_VHOST_NET is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIDEO_BT848 is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_CX88 is not set
+# CONFIG_VIDEO_GO7007 is not set
+# CONFIG_VIDEO_IR_I2C is not set
+# CONFIG_VIDEO_IVTV is not set
+# CONFIG_VIDEO_TM6000 is not set
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_ZORAN is not set
+CONFIG_VIRTIO=m
+CONFIG_VIRTIO_BLK=m
+# CONFIG_VIRTIO_CONSOLE is not set
+CONFIG_VIRTIO_NET=m
+CONFIG_VIRTIO_PCI=m
+CONFIG_VIRTIO_RING=m
+CONFIG_VIRTUALIZATION=y
+# CONFIG_VMWARE_BALLOON is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_X86=y
+# CONFIG_X86_32 is not set
+CONFIG_X86_64=y
+CONFIG_X86_64_SMP=y
+CONFIG_X86_ACPI_CPUFREQ=y
+CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y
+CONFIG_X86_CHECK_BIOS_CORRUPTION=y
+CONFIG_X86_CMOV=y
+CONFIG_X86_CMPXCHG=y
+CONFIG_X86_CMPXCHG64=y
+CONFIG_X86_CPUID=y
+CONFIG_X86_DEBUGCTLMSR=y
+CONFIG_X86_EXTENDED_PLATFORM=y
+CONFIG_X86_HT=y
+CONFIG_X86_INTERNODE_CACHE_SHIFT=6
+CONFIG_X86_IO_APIC=y
+CONFIG_X86_L1_CACHE_SHIFT=6
+CONFIG_X86_LOCAL_APIC=y
+CONFIG_X86_MCE=y
+# CONFIG_X86_MCE_AMD is not set
+# CONFIG_X86_MCE_INJECT is not set
+CONFIG_X86_MCE_INTEL=y
+CONFIG_X86_MCE_THRESHOLD=y
+CONFIG_X86_MINIMUM_CPU_FAMILY=64
+CONFIG_X86_MPPARSE=y
+CONFIG_X86_MSR=y
+# CONFIG_X86_P4_CLOCKMOD is not set
+CONFIG_X86_PAT=y
+# CONFIG_X86_PCC_CPUFREQ is not set
+CONFIG_X86_PLATFORM_DEVICES=y
+CONFIG_X86_PM_TIMER=y
+# CONFIG_X86_POWERNOW_K8 is not set
+# CONFIG_X86_PTDUMP is not set
+CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
+CONFIG_X86_RESERVE_LOW=64
+# CONFIG_X86_SPEEDSTEP_CENTRINO is not set
+# CONFIG_X86_SPEEDSTEP_LIB is not set
+CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y
+CONFIG_X86_THERMAL_VECTOR=y
+CONFIG_X86_TSC=y
+CONFIG_X86_VERBOSE_BOOTUP=y
+# CONFIG_X86_VSMP is not set
+CONFIG_X86_WP_WORKS_OK=y
+CONFIG_X86_XADD=y
+CONFIG_XFRM_USER=y
+# CONFIG_XO15_EBOOK is not set
+# CONFIG_ZD1211RW is not set
+CONFIG_ZONE_DMA=y
+CONFIG_ZONE_DMA32=y
+CONFIG_ZONE_DMA_FLAG=1
diff --git a/chromeos/config/x86_64/config.flavour.chromeos-intel-pineview b/chromeos/config/x86_64/config.flavour.chromeos-intel-pineview
new file mode 100644
index 00000000..fad4bbee
--- /dev/null
+++ b/chromeos/config/x86_64/config.flavour.chromeos-intel-pineview
@@ -0,0 +1,3 @@
+#
+# Config options generated by splitconfig
+#
diff --git a/chromeos/scripts/allconfigs b/chromeos/scripts/allconfigs
new file mode 100755
index 00000000..1643199
--- /dev/null
+++ b/chromeos/scripts/allconfigs
@@ -0,0 +1,28 @@
+#!/bin/bash
+
+bindir="`pwd`/chromeos/scripts"
+confdir="`pwd`/chromeos/config"
+
+get_flavourconfigs() {
+ for file in `find $confdir`; do
+ if echo $file | egrep -q "config\.flavour\..*[^~]$"; then
+ basename $file | awk -F . '{ print $3 }'
+ fi
+ done
+}
+
+get_arch() {
+ if find . -name config.flavour.$1 | grep -q i386; then
+ echo i386
+ else
+ echo arm
+ fi
+}
+
+for flavour in $(get_flavourconfigs); do
+ echo $flavour $(get_arch $flavour)
+ $bindir/prepareconfig $flavour
+ yes "" | make ARCH=$(get_arch $flavour) oldconfig
+ cp .config .config-$flavour
+done
+
diff --git a/chromeos/scripts/kernelconfig b/chromeos/scripts/kernelconfig
new file mode 100755
index 00000000..c056c8c
--- /dev/null
+++ b/chromeos/scripts/kernelconfig
@@ -0,0 +1,123 @@
+#!/bin/bash
+
+# Script to merge all configs and run 'make silentoldconfig' on it to wade out bad juju.
+# Then split the configs into distro-commmon and flavour-specific parts
+
+# We have to be in the top level kernel source directory
+if [ ! -f MAINTAINERS ] || [ ! -f Makefile ]; then
+ echo "This does not appear to be the kernel source directory." 1>&2
+ exit 1
+fi
+
+mode=${1:?"Usage: $0 [oldconfig|editconfig]"}
+case "$mode" in
+ oldconfig) ;; # All is good
+ editconfig) ;; # All is good
+ genconfig) ;; # All is good
+ *) echo "$0 called with invalid mode" 1>&2
+ exit 1 ;;
+esac
+kerneldir="`pwd`"
+confdir="$kerneldir/chromeos/config"
+archs="x86_64 i386 armel"
+family='chromeos'
+bindir="`pwd`/chromeos/scripts"
+common_conf="$confdir/config.common.$family"
+tmpdir=`mktemp -d`
+
+if [ "$mode" = "genconfig" ]; then
+ keep=1
+ mode="oldconfig"
+ test -d CONFIGS || mkdir CONFIGS
+fi
+
+test -d build || mkdir build
+
+for arch in $archs; do
+ # Map debian archs to kernel archs
+ case "$arch" in
+ amd64) kernarch="x86_64" ;;
+ lpia) kernarch="x86" ;;
+ sparc) kernarch="sparc64" ;;
+ armel) kernarch="arm" ;;
+ *) kernarch="$arch" ;;
+ esac
+
+ echo ""
+ echo "***************************************"
+ echo "* Processing $arch ($kernarch) ... "
+ archconfdir=$confdir/$arch
+ flavourconfigs=$(cd $archconfdir && ls config.flavour.*[^~])
+
+ # Merge configs
+ # We merge config.common.ubuntu + config.common.<arch> +
+ # config.flavour.<flavour>
+
+ for config in $flavourconfigs; do
+ fullconf="$tmpdir/$arch-$config-full"
+ case $config in
+ *)
+ : >"$fullconf"
+ if [ -f $common_conf ]; then
+ cat $common_conf >> "$fullconf"
+ fi
+ if [ -f $archconfdir/config.common.$arch ]; then
+ cat $archconfdir/config.common.$arch >> "$fullconf"
+ fi
+ cat "$archconfdir/$config" >>"$fullconf"
+ ;;
+ esac
+ done
+
+ for config in $flavourconfigs; do
+ if [ -f $archconfdir/$config ]; then
+ fullconf="$tmpdir/$arch-$config-full"
+ cat "$fullconf" > build/.config
+ # Call oldconfig or menuconfig
+ case "$mode" in
+ oldconfig)
+ # Weed out incorrect config parameters
+ echo "* Run silentoldconfig on $arch/$config ..."
+ make O=`pwd`/build ARCH=$kernarch silentoldconfig ;;
+ editconfig)
+ # Interactively edit config parameters
+ echo " * Run menuconfig on $arch/$config... Press a key."
+ read
+ make O=`pwd`/build ARCH=$kernarch menuconfig ;;
+ *) # Bad!
+ exit 1 ;;
+ esac
+ cat build/.config > $archconfdir/$config
+ if [ "$keep" = "1" ]; then
+ cat build/.config > CONFIGS/$arch-$config
+ fi
+ else
+ echo "!! Config not found $archconfdir/$config..."
+ fi
+ done
+
+ echo "Running splitconfig for $arch"
+ echo
+
+ # Can we make this more robust by avoiding $tmpdir completely?
+ # This approach was used for now because I didn't want to change
+ # splitconfig
+ (cd $archconfdir; rm config.common.$arch; $bindir/splitconfig; \
+ mv config.common config.common.$arch; \
+ cp config.common.$arch $tmpdir)
+done
+
+rm -f $common_conf
+
+# Now run splitconfig on all the config.common.<arch> copied to
+# $tmpdir
+(cd $tmpdir; $bindir/splitconfig)
+(
+ cd $confdir;
+ rm -f *-full
+ grep -v 'is UNMERGABLE' <$tmpdir/config.common >$common_conf
+ for arch in $archs; do
+ grep -v 'is UNMERGABLE' <$tmpdir/config.common.$arch \
+ >$arch/config.common.$arch
+ done
+)
diff --git a/chromeos/scripts/prepareconfig b/chromeos/scripts/prepareconfig
new file mode 100755
index 00000000..b82cf35
--- /dev/null
+++ b/chromeos/scripts/prepareconfig
@@ -0,0 +1,18 @@
+#!/bin/bash
+
+family=chromeos
+
+flavourconf=$(find ${family} -name config.flavour.$1)
+if [ ! -f "${flavourconf}" ]; then
+ echo "Found no flavour configuration for '$1'." 1>&2
+ exit 1
+fi
+
+outputfile="${2:-.config}"
+
+archconfdir=$(dirname ${flavourconf})
+
+# Generate .config
+cat ${family}/config/config.common.${family} \
+ ${archconfdir}/config.common.* \
+ "${flavourconf}" > "${outputfile}"
diff --git a/chromeos/scripts/splitconfig b/chromeos/scripts/splitconfig
new file mode 100755
index 00000000..262fa20
--- /dev/null
+++ b/chromeos/scripts/splitconfig
@@ -0,0 +1,49 @@
+#!/usr/bin/env python
+
+import os
+import re
+import sys
+
+allconfigs = {}
+
+# Parse config files
+for config in os.listdir("."):
+ # Only config.*
+ if not config.startswith("config."):
+ continue
+ # Ignore emacs backups
+ if config.endswith("~"):
+ continue
+ # Nothing that is disabled, or remnant
+ if re.search("\.(default|disabled|stub)$", config):
+ continue
+
+ allconfigs[config] = set()
+
+ for line in open(config):
+ m = re.match("#*\s*CONFIG_(\w+)[\s=](.*)$", line)
+ if not m:
+ continue
+ option, value = m.groups()
+ allconfigs[config].add((option, value))
+
+# Split out common config options
+common = allconfigs.values()[0].copy()
+for config in allconfigs.keys():
+ common &= allconfigs[config]
+for config in allconfigs.keys():
+ allconfigs[config] -= common
+allconfigs["config.common"] = common
+
+# Generate new splitconfigs
+for config in allconfigs.keys():
+ f = open(config, "w")
+ command = os.path.basename(sys.argv[0])
+ print >>f, "#\n# Config options generated by %s\n#" % command
+ for option, value in sorted(list(allconfigs[config])):
+ if value == "is not set":
+ print >>f, "# CONFIG_%s %s" % (option, value)
+ else:
+ print >>f, "CONFIG_%s=%s" % (option, value)
+
+ f.close()
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 5987e0b..3807e57 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -83,6 +83,23 @@ config SATA_AHCI_PLATFORM
If unsure, say N.
+config SATA_AHCI_TEGRA
+ tristate "TEGRA AHCI SATA support"
+ depends on ARCH_TEGRA_3x_SOC
+ help
+ This option enables support for TEGRA AHCI Serial ATA.
+
+ If unsure, say N.
+
+config TEGRA_SATA_IDLE_POWERGATE
+ bool "TEGRA SATA idle power-gating"
+ depends on SATA_AHCI_TEGRA && PM && PM_RUNTIME
+ help
+ This option enables power-gating during SATA idling.
+ This option should not be enabled if sata clocks are in dvfs_table.
+
+ If unsure, say N.
+
config SATA_FSL
tristate "Freescale 3.0Gbps SATA support"
depends on FSL_SOC
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 9550d69..4245ecf 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_ATA) += libata.o
# non-SFF interface
obj-$(CONFIG_SATA_AHCI) += ahci.o libahci.o
+obj-$(CONFIG_SATA_AHCI_TEGRA) += ahci-tegra.o libahci.o
obj-$(CONFIG_SATA_ACARD_AHCI) += acard-ahci.o libahci.o
obj-$(CONFIG_SATA_AHCI_PLATFORM) += ahci_platform.o libahci.o
obj-$(CONFIG_SATA_FSL) += sata_fsl.o
diff --git a/drivers/ata/ahci-tegra.c b/drivers/ata/ahci-tegra.c
new file mode 100644
index 00000000..5c58da1
--- /dev/null
+++ b/drivers/ata/ahci-tegra.c
@@ -0,0 +1,2154 @@
+/*
+ * ahci-tegra.c - AHCI SATA support for TEGRA AHCI device
+ *
+ * Copyright (c) 2011-2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ *
+ * libata documentation is available via 'make {ps|pdf}docs',
+ * as Documentation/DocBook/libata.*
+ *
+ * AHCI hardware documentation:
+ * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
+ * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/blkdev.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/device.h>
+#include <linux/dmi.h>
+#include <scsi/scsi_host.h>
+#include <scsi/scsi_cmnd.h>
+#include <linux/libata.h>
+#include <linux/regulator/machine.h>
+#include <linux/pm_runtime.h>
+#include "ahci.h"
+
+#include <linux/clk.h>
+#include <mach/clk.h>
+#include <mach/iomap.h>
+#include <mach/io.h>
+#include <mach/powergate.h>
+
+#define DRV_NAME "tegra-sata"
+#define DRV_VERSION "1.0"
+
+#define ENABLE_AHCI_DBG_PRINT 0
+#if ENABLE_AHCI_DBG_PRINT
+#define AHCI_DBG_PRINT(fmt, arg...) printk(KERN_ERR fmt, ## arg)
+#else
+#define AHCI_DBG_PRINT(fmt, arg...) do {} while (0)
+#endif
+
+/* number of AHCI ports */
+#define TEGRA_AHCI_NUM_PORTS 1
+
+/* idle timeout for PM in msec */
+#define TEGRA_AHCI_MIN_IDLE_TIME 1000
+#define TEGRA_AHCI_DEFAULT_IDLE_TIME 2000
+
+#ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
+static u32 tegra_ahci_idle_time = TEGRA_AHCI_DEFAULT_IDLE_TIME;
+#endif
+
+/* Bit 0 (EN_FPCI) to allow FPCI accesses to SATA */
+#define SATA_CONFIGURATION_0_OFFSET 0x180
+#define EN_FPCI (1 << 0)
+
+#define SATA_INTR_MASK_0_OFFSET 0x188
+#define IP_INT_MASK (1 << 16)
+
+/* Need to write 0x00400200 to 0x70020094 */
+#define SATA_FPCI_BAR5_0_OFFSET 0x094
+#define PRI_ICTLR_CPU_IER_SET_0_OFFSET 0x024
+#define CPU_IER_SATA_CTL (1 << 23)
+
+#define AHCI_BAR5_CONFIG_LOCATION 0x24
+#define TEGRA_SATA_BAR5_INIT_PROGRAM 0xFFFFFFFF
+#define TEGRA_SATA_BAR5_FINAL_PROGRAM 0x40020000
+
+#define FUSE_SATA_CALIB_OFFSET 0x224
+#define FUSE_SATA_CALIB_MASK 0x3
+
+#define T_SATA0_CFG_PHY_REG 0x120
+#define PHY_USE_7BIT_ALIGN_DET_FOR_SPD_MASK (1 << 11)
+
+#define T_SATA0_CFG_POWER_GATE 0x4ac
+#define POWER_GATE_SSTS_RESTORED_MASK (1 << 23)
+#define POWER_GATE_SSTS_RESTORED_YES (1 << 23)
+#define POWER_GATE_SSTS_RESTORED_NO (0 << 23)
+
+#define T_SATA0_DBG0_OFFSET 0x550
+
+#define T_SATA0_INDEX_OFFSET 0x680
+#define SATA0_NONE_SELECTED 0
+#define SATA0_CH1_SELECTED (1 << 0)
+
+#define T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET 0x690
+#define SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0
+#define SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK (0xff << 0)
+#define SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT 8
+#define SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK (0xff << 8)
+
+#define T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET 0x694
+#define SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0
+#define SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK (0xff << 0)
+#define SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT 12
+#define SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK (0xff << 12)
+#define SATA0_CHX_PHY_CTRL1_GEN2_RX_EQ_SHIFT 24
+#define SATA0_CHX_PHY_CTRL1_GEN2_RX_EQ_MASK (0xf << 24)
+
+/* AHCI config space defines */
+#define TEGRA_PRIVATE_AHCI_CC_BKDR 0x4a4
+#define TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE 0x54c
+#define TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN (1 << 12)
+#define TEGRA_PRIVATE_AHCI_CC_BKDR_PGM 0x01060100
+
+/* AHCI HBA_CAP */
+#define TEGRA_PRIVATE_AHCI_CAP_BKDR 0xa0
+#define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
+
+#define TEGRA_SATA_IO_SPACE_OFFSET 4
+#define TEGRA_SATA_ENABLE_IO_SPACE (1 << 0)
+#define TEGRA_SATA_ENABLE_MEM_SPACE (1 << 1)
+#define TEGRA_SATA_ENABLE_BUS_MASTER (1 << 2)
+#define TEGRA_SATA_ENABLE_SERR (1 << 8)
+
+#define TEGRA_SATA_CORE_CLOCK_FREQ_HZ (108*1000*1000)
+#define TEGRA_SATA_OOB_CLOCK_FREQ_HZ (216*1000*1000)
+
+#define APB_PMC_SATA_PWRGT_0_REG 0x1ac
+#define CLK_RST_SATA_PLL_CFG0_REG 0x490
+#define CLK_RST_SATA_PLL_CFG1_REG 0x494
+#define SATA_AUX_PAD_PLL_CNTL_1_REG 0x1100
+#define SATA_AUX_MISC_CNTL_1_REG 0x1108
+
+/* for APB_PMC_SATA_PWRGT_0_REG */
+#define PG_INFO_MASK (1 << 6)
+#define PG_INFO_ON (1 << 6)
+#define PG_INFO_OFF (0 << 6)
+#define PLLE_IDDQ_SWCTL_MASK (1 << 4)
+#define PLLE_IDDQ_SWCTL_ON (1 << 4)
+#define PLLE_IDDQ_SWCTL_OFF (0 << 4)
+#define PADPHY_IDDQ_OVERRIDE_VALUE_MASK (1 << 3)
+#define PADPHY_IDDQ_OVERRIDE_VALUE_ON (1 << 3)
+#define PADPHY_IDDQ_OVERRIDE_VALUE_OFF (0 << 3)
+#define PADPHY_IDDQ_SWCTL_MASK (1 << 2)
+#define PADPHY_IDDQ_SWCTL_ON (1 << 2)
+#define PADPHY_IDDQ_SWCTL_OFF (0 << 2)
+#define PADPLL_IDDQ_OVERRIDE_VALUE_MASK (1 << 1)
+#define PADPLL_IDDQ_OVERRIDE_VALUE_ON (1 << 1)
+#define PADPLL_IDDQ_OVERRIDE_VALUE_OFF (0 << 1)
+#define PADPLL_IDDQ_SWCTL_MASK (1 << 0)
+#define PADPLL_IDDQ_SWCTL_ON (1 << 0)
+#define PADPLL_IDDQ_SWCTL_OFF (0 << 0)
+
+/* for CLK_RST_SATA_PLL_CFG0_REG */
+#define PADPLL_RESET_OVERRIDE_VALUE_MASK (1 << 1)
+#define PADPLL_RESET_OVERRIDE_VALUE_ON (1 << 1)
+#define PADPLL_RESET_OVERRIDE_VALUE_OFF (0 << 1)
+#define PADPLL_RESET_SWCTL_MASK (1 << 0)
+#define PADPLL_RESET_SWCTL_ON (1 << 0)
+#define PADPLL_RESET_SWCTL_OFF (0 << 0)
+
+/* for CLK_RST_SATA_PLL_CFG1_REG */
+#define IDDQ2LANE_SLUMBER_DLY_MASK (0xffL << 16)
+#define IDDQ2LANE_SLUMBER_DLY_SHIFT 16
+#define IDDQ2LANE_SLUMBER_DLY_3MS (3 << 16)
+#define IDDQ2LANE_IDDQ_DLY_SHIFT 0
+#define IDDQ2LANE_IDDQ_DLY_MASK (0xffL << 0)
+
+/* for SATA_AUX_PAD_PLL_CNTL_1_REG */
+#define REFCLK_SEL_MASK (3 << 11)
+#define REFCLK_SEL_INT_CML (0 << 11)
+#define LOCKDET_FIELD (1 << 6)
+
+/* for SATA_AUX_MISC_CNTL_1_REG */
+#define NVA2SATA_OOB_ON_POR_MASK (1 << 7)
+#define NVA2SATA_OOB_ON_POR_YES (1 << 7)
+#define NVA2SATA_OOB_ON_POR_NO (0 << 7)
+#define L0_RX_IDLE_T_SAX_SHIFT 5
+#define L0_RX_IDLE_T_SAX_MASK (3 << 5)
+#define L0_RX_IDLE_T_NPG_SHIFT 3
+#define L0_RX_IDLE_T_NPG_MASK (3 << 3)
+#define L0_RX_IDLE_T_MUX_MASK (1 << 2)
+#define L0_RX_IDLE_T_MUX_FROM_APB_MISC (1 << 2)
+#define L0_RX_IDLE_T_MUX_FROM_SATA (0 << 2)
+
+#define SSTAT_IPM_STATE_MASK 0xF00
+#define SSTAT_IPM_SLUMBER_STATE 0x600
+
+enum {
+ AHCI_PCI_BAR = 5,
+};
+
+enum port_idle_status {
+ PORT_IS_NOT_IDLE,
+ PORT_IS_IDLE,
+ PORT_IS_IDLE_NOT_SLUMBER,
+ PORT_IS_SLUMBER,
+};
+
+enum sata_state {
+ SATA_ON,
+ SATA_OFF,
+ SATA_GOING_ON,
+ SATA_GOING_OFF,
+ SATA_ABORT_OFF,
+};
+
+char *sata_power_rails[] = {
+ "avdd_sata",
+ "vdd_sata",
+ "hvdd_sata",
+ "avdd_sata_pll"
+};
+
+#define NUM_SATA_POWER_RAILS ARRAY_SIZE(sata_power_rails)
+
+struct tegra_qc_list {
+ struct list_head list;
+ struct ata_queued_cmd *qc;
+};
+
+/*
+ * tegra_ahci_host_priv is the extension of ahci_host_priv
+ * with extra fields: idle_timer, pg_save, pg_state, etc.
+ */
+struct tegra_ahci_host_priv {
+ struct ahci_host_priv ahci_host_priv;
+ struct regulator *power_rails[NUM_SATA_POWER_RAILS];
+ void __iomem *bars_table[6];
+ struct ata_host *host;
+ struct timer_list idle_timer;
+ struct device *dev;
+ void *pg_save;
+ enum sata_state pg_state;
+ struct list_head qc_list;
+};
+
+static int tegra_ahci_init_one(struct platform_device *pdev);
+static int tegra_ahci_remove_one(struct platform_device *pdev);
+
+#ifdef CONFIG_PM
+static bool tegra_ahci_power_un_gate(struct ata_host *host);
+static bool tegra_ahci_power_gate(struct ata_host *host);
+static void tegra_ahci_abort_power_gate(struct ata_host *host);
+static int tegra_ahci_controller_suspend(struct platform_device *pdev);
+static int tegra_ahci_controller_resume(struct platform_device *pdev);
+static int tegra_ahci_suspend(struct platform_device *pdev, pm_message_t mesg);
+static int tegra_ahci_resume(struct platform_device *pdev);
+static enum port_idle_status tegra_ahci_is_port_idle(struct ata_port *ap);
+static enum port_idle_status tegra_ahci_is_port_slumber(struct ata_port *ap);
+static bool tegra_ahci_are_all_ports_idle(struct ata_host *host);
+static bool tegra_ahci_are_all_ports_slumber(struct ata_host *host);
+#ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
+static unsigned int tegra_ahci_qc_issue(struct ata_queued_cmd *qc);
+static int tegra_ahci_hardreset(struct ata_link *link, unsigned int *class,
+ unsigned long deadline);
+static int tegra_ahci_runtime_suspend(struct device *dev);
+static int tegra_ahci_runtime_resume(struct device *dev);
+static void tegra_ahci_idle_timer(unsigned long arg);
+static int tegra_ahci_queue_one_qc(struct tegra_ahci_host_priv *tegra_hpriv,
+ struct ata_queued_cmd *qc);
+static void tegra_ahci_dequeue_qcs(struct tegra_ahci_host_priv *tegra_hpriv);
+#endif
+#else
+#define tegra_ahci_controller_suspend NULL
+#define tegra_ahci_controller_resume NULL
+#define tegra_ahci_suspend NULL
+#define tegra_ahci_resume NULL
+#endif
+
+static struct scsi_host_template ahci_sht = {
+ AHCI_SHT("tegra-sata"),
+};
+
+static struct ata_port_operations tegra_ahci_ops = {
+ .inherits = &ahci_ops,
+#ifdef CONFIG_PM
+#ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
+ .qc_issue = tegra_ahci_qc_issue,
+ .hardreset = tegra_ahci_hardreset,
+#endif
+#endif
+};
+
+static const struct ata_port_info ahci_port_info = {
+ .flags = AHCI_FLAG_COMMON,
+ .pio_mask = 0x1f, /* pio0-4 */
+ .udma_mask = ATA_UDMA6,
+ .port_ops = &tegra_ahci_ops,
+};
+
+#ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
+static const struct dev_pm_ops tegra_ahci_dev_rt_ops = {
+ .runtime_suspend = tegra_ahci_runtime_suspend,
+ .runtime_resume = tegra_ahci_runtime_resume,
+};
+#endif
+
+static struct platform_driver tegra_platform_ahci_driver = {
+ .probe = tegra_ahci_init_one,
+ .remove = __devexit_p(tegra_ahci_remove_one),
+#ifdef CONFIG_PM
+ .suspend = tegra_ahci_suspend,
+ .resume = tegra_ahci_resume,
+ .driver = {
+ .name = DRV_NAME,
+#ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
+ .pm = &tegra_ahci_dev_rt_ops,
+#endif
+ }
+#else
+ .driver = {
+ .name = DRV_NAME,
+ }
+#endif
+};
+
+struct tegra_ahci_host_priv *g_tegra_hpriv;
+
+static inline u32 pmc_readl(u32 offset)
+{
+ u32 val;
+ val = readl(IO_ADDRESS(TEGRA_PMC_BASE + offset));
+ AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_PMC_BASE+offset, val);
+ return val;
+}
+
+static inline void pmc_writel(u32 val, u32 offset)
+{
+ AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_PMC_BASE+offset, val);
+ writel(val, IO_ADDRESS(TEGRA_PMC_BASE + offset));
+}
+
+static inline u32 clk_readl(u32 offset)
+{
+ u32 val;
+
+ val = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + offset));
+ AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_CLK_RESET_BASE+offset, val);
+ return val;
+}
+
+static inline void clk_writel(u32 val, u32 offset)
+{
+ AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_CLK_RESET_BASE+offset, val);
+ writel(val, IO_ADDRESS(TEGRA_CLK_RESET_BASE + offset));
+}
+
+static inline u32 misc_readl(u32 offset)
+{
+ u32 val;
+
+ val = readl(IO_ADDRESS(TEGRA_APB_MISC_BASE + offset));
+ AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_APB_MISC_BASE+offset, val);
+ return val;
+}
+
+static inline void misc_writel(u32 val, u32 offset)
+{
+ AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_APB_MISC_BASE+offset, val);
+ writel(val, IO_ADDRESS(TEGRA_APB_MISC_BASE + offset));
+}
+
+static inline u32 sata_readl(u32 offset)
+{
+ u32 val;
+
+ val = readl(IO_ADDRESS(TEGRA_SATA_BASE + offset));
+ AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_SATA_BASE+offset, val);
+ return val;
+}
+
+static inline void sata_writel(u32 val, u32 offset)
+{
+ AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_SATA_BASE+offset, val);
+ writel(val, IO_ADDRESS(TEGRA_SATA_BASE + offset));
+}
+
+static inline u32 scfg_readl(u32 offset)
+{
+ u32 val;
+
+ val = readl(IO_ADDRESS(TEGRA_SATA_CONFIG_BASE + offset));
+ AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_SATA_CONFIG_BASE+offset,
+ val);
+ return val;
+}
+
+static inline void scfg_writel(u32 val, u32 offset)
+{
+ AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_SATA_CONFIG_BASE+offset,
+ val);
+ writel(val, IO_ADDRESS(TEGRA_SATA_CONFIG_BASE + offset));
+}
+
+static inline u32 pictlr_readl(u32 offset)
+{
+ u32 val;
+
+ val = readl(IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE + offset));
+ AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_PRIMARY_ICTLR_BASE+offset,
+ val);
+ return val;
+}
+
+static inline void pictlr_writel(u32 val, u32 offset)
+{
+ AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_PRIMARY_ICTLR_BASE+offset,
+ val);
+ writel(val, IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE + offset));
+}
+
+static inline u32 fuse_readl(u32 offset)
+{
+ u32 val;
+
+ val = readl(IO_ADDRESS(TEGRA_FUSE_BASE + offset));
+ AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_FUSE_BASE+offset, val);
+
+ return val;
+}
+
+/* Sata Pad Cntrl Values */
+struct sata_pad_cntrl {
+ u8 gen1_tx_amp;
+ u8 gen1_tx_peak;
+ u8 gen2_tx_amp;
+ u8 gen2_tx_peak;
+};
+
+static const struct sata_pad_cntrl sata_calib_pad_val[] = {
+ { /* SATA_CALIB[1:0] = 00 */
+ 0x0c,
+ 0x04,
+ 0x0e,
+ 0x0a
+ },
+ { /* SATA_CALIB[1:0] = 01 */
+ 0x0e,
+ 0x04,
+ 0x14,
+ 0x0a
+ },
+ { /* SATA_CALIB[1:0] = 10 */
+ 0x0e,
+ 0x07,
+ 0x1a,
+ 0x0e
+ },
+ { /* SATA_CALIB[1:0] = 11 */
+ 0x14,
+ 0x0e,
+ 0x1a,
+ 0x0e
+ }
+};
+
+static void tegra_ahci_set_pad_cntrl_regs(void)
+{
+ int calib_val;
+ int val;
+ int i;
+
+ calib_val = fuse_readl(FUSE_SATA_CALIB_OFFSET) & FUSE_SATA_CALIB_MASK;
+
+ for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
+ scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
+
+ val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);
+ val &= ~SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
+ val |= (sata_calib_pad_val[calib_val].gen1_tx_amp <<
+ SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT);
+ scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);
+
+ val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);
+ val &= ~SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
+ val |= (sata_calib_pad_val[calib_val].gen1_tx_peak <<
+ SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT);
+ scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);
+
+ val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
+ val &= ~SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
+ val |= (sata_calib_pad_val[calib_val].gen2_tx_amp <<
+ SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT);
+ scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
+
+ val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
+ val &= ~SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
+ val |= (sata_calib_pad_val[calib_val].gen2_tx_peak <<
+ SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT);
+ scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
+
+ /* set 2 to SATA0_CHX_PHY_CTRL1_GEN2_RX_EQ field */
+ val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
+ val &= ~SATA0_CHX_PHY_CTRL1_GEN2_RX_EQ_MASK;
+ val |= (2 << SATA0_CHX_PHY_CTRL1_GEN2_RX_EQ_SHIFT);
+ scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
+ }
+ scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
+}
+
+int tegra_ahci_get_rails(struct regulator *regulators[])
+{
+ struct regulator *reg;
+ int i;
+ int ret = 0;
+
+ for (i = 0; i < NUM_SATA_POWER_RAILS; ++i) {
+ reg = regulator_get(NULL, sata_power_rails[i]);
+ if (IS_ERR_OR_NULL(reg)) {
+ pr_err("%s: can't get regulator %s\n",
+ __func__, sata_power_rails[i]);
+ WARN_ON(1);
+ ret = PTR_ERR(reg);
+ goto exit;
+ }
+ regulators[i] = reg;
+ }
+exit:
+ return ret;
+}
+
+void tegra_ahci_put_rails(struct regulator *regulators[])
+{
+ int i;
+
+ for (i = 0; i < NUM_SATA_POWER_RAILS; ++i)
+ regulator_put(regulators[i]);
+}
+
+int tegra_ahci_power_on_rails(struct regulator *regulators[])
+{
+ struct regulator *reg;
+ int i;
+ int ret = 0;
+
+ for (i = 0; i < NUM_SATA_POWER_RAILS; ++i) {
+ reg = regulators[i];
+ ret = regulator_enable(reg);
+ if (ret) {
+ pr_err("%s: can't enable regulator[%d]\n",
+ __func__, i);
+ WARN_ON(1);
+ goto exit;
+ }
+ }
+
+exit:
+ return ret;
+}
+
+int tegra_ahci_power_off_rails(struct regulator *regulators[])
+{
+ struct regulator *reg;
+ int i;
+ int ret = 0;
+
+ for (i = 0; i < NUM_SATA_POWER_RAILS; ++i) {
+ reg = regulators[i];
+ if (!IS_ERR_OR_NULL(reg)) {
+ ret = regulator_disable(reg);
+ if (ret) {
+ pr_err("%s: can't disable regulator[%d]\n",
+ __func__, i);
+ WARN_ON(1);
+ goto exit;
+ }
+ }
+ }
+
+exit:
+ return ret;
+}
+static int tegra_ahci_controller_init(struct tegra_ahci_host_priv *tegra_hpriv)
+{
+ int err;
+ struct clk *clk_sata = NULL;
+ struct clk *clk_sata_oob = NULL;
+ struct clk *clk_sata_cold = NULL;
+ struct clk *clk_pllp = NULL;
+ u32 val;
+ u32 timeout;
+
+ err = tegra_ahci_get_rails(tegra_hpriv->power_rails);
+ if (err) {
+ pr_err("%s: fails to get rails (%d)\n", __func__, err);
+ goto exit;
+ }
+
+ err = tegra_ahci_power_on_rails(tegra_hpriv->power_rails);
+ if (err) {
+ pr_err("%s: fails to power on rails (%d)\n", __func__, err);
+ goto exit;
+ }
+
+ /* pll_p is the parent of tegra_sata and tegra_sata_oob */
+ clk_pllp = clk_get_sys(NULL, "pll_p");
+ if (IS_ERR_OR_NULL(clk_pllp)) {
+ pr_err("%s: unable to get PLL_P clock\n", __func__);
+ err = -ENODEV;
+ goto exit;
+ }
+
+ clk_sata = clk_get_sys("tegra_sata", NULL);
+ if (IS_ERR_OR_NULL(clk_sata)) {
+ pr_err("%s: unable to get SATA clock\n", __func__);
+ err = -ENODEV;
+ goto exit;
+ }
+
+ clk_sata_oob = clk_get_sys("tegra_sata_oob", NULL);
+ if (IS_ERR_OR_NULL(clk_sata_oob)) {
+ pr_err("%s: unable to get SATA OOB clock\n", __func__);
+ err = -ENODEV;
+ goto exit;
+ }
+
+ clk_sata_cold = clk_get_sys("tegra_sata_cold", NULL);
+ if (IS_ERR_OR_NULL(clk_sata_cold)) {
+ pr_err("%s: unable to get SATA COLD clock\n", __func__);
+ err = -ENODEV;
+ goto exit;
+ }
+
+ tegra_periph_reset_assert(clk_sata);
+ tegra_periph_reset_assert(clk_sata_oob);
+ tegra_periph_reset_assert(clk_sata_cold);
+ udelay(10);
+
+ /* need to establish both clocks divisors before setting clk sources */
+ clk_set_rate(clk_sata, clk_get_rate(clk_sata)/10);
+ clk_set_rate(clk_sata_oob, clk_get_rate(clk_sata_oob)/10);
+
+ /* set SATA clk and SATA_OOB clk source */
+ clk_set_parent(clk_sata, clk_pllp);
+ clk_set_parent(clk_sata_oob, clk_pllp);
+
+ /* Configure SATA clocks */
+ /* Core clock runs at 108MHz */
+ if (clk_set_rate(clk_sata, TEGRA_SATA_CORE_CLOCK_FREQ_HZ)) {
+ err = -ENODEV;
+ goto exit;
+ }
+ /* OOB clock runs at 216MHz */
+ if (clk_set_rate(clk_sata_oob, TEGRA_SATA_OOB_CLOCK_FREQ_HZ)) {
+ err = -ENODEV;
+ goto exit;
+ }
+
+ /**** Init the SATA PAD PLL ****/
+ /* SATA_PADPLL_IDDQ_SWCTL=1 and SATA_PADPLL_IDDQ_OVERRIDE_VALUE=1 */
+ val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
+ val &= ~(PADPLL_IDDQ_SWCTL_MASK | PADPLL_IDDQ_OVERRIDE_VALUE_MASK);
+ val |= (PADPLL_IDDQ_SWCTL_ON | PADPLL_IDDQ_OVERRIDE_VALUE_ON);
+ pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
+
+ /* SATA_PADPLL_RESET_OVERRIDE_VALUE=1 and SATA_PADPLL_RESET_SWCTL=1 */
+ val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
+ val &= ~(PADPLL_RESET_OVERRIDE_VALUE_MASK | PADPLL_RESET_SWCTL_MASK);
+ val |= (PADPLL_RESET_OVERRIDE_VALUE_ON | PADPLL_RESET_SWCTL_ON);
+ clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
+
+ /* SATA_PADPHY_IDDQ_OVERRIDE_VALUE and SATA_PADPHY_IDDQ_SWCTL = 1 */
+ val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
+ val &= ~(PADPHY_IDDQ_OVERRIDE_VALUE_MASK | PADPHY_IDDQ_SWCTL_MASK);
+ val |= (PADPHY_IDDQ_OVERRIDE_VALUE_ON | PADPHY_IDDQ_SWCTL_ON);
+ pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
+
+ /* Get SATA pad PLL out of IDDQ mode */
+ val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
+ val &= ~PADPLL_IDDQ_OVERRIDE_VALUE_MASK;
+ val |= PADPLL_IDDQ_OVERRIDE_VALUE_OFF;
+ pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
+ udelay(3);
+
+ /* select internal CML ref clk
+ * select PLLE as input to IO phy */
+ val = misc_readl(SATA_AUX_PAD_PLL_CNTL_1_REG);
+ val &= ~REFCLK_SEL_MASK;
+ val |= REFCLK_SEL_INT_CML;
+ misc_writel(val, SATA_AUX_PAD_PLL_CNTL_1_REG);
+
+ /* wait for SATA_PADPLL_IDDQ2LANE_SLUMBER_DLY = 3 microseconds. */
+ val = clk_readl(CLK_RST_SATA_PLL_CFG1_REG);
+ val &= ~IDDQ2LANE_SLUMBER_DLY_MASK;
+ val |= IDDQ2LANE_SLUMBER_DLY_3MS;
+ clk_writel(val, CLK_RST_SATA_PLL_CFG1_REG);
+ udelay(3);
+
+ /* de-assert IDDQ mode signal going to PHY */
+ val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
+ val &= ~PADPHY_IDDQ_OVERRIDE_VALUE_MASK;
+ val |= PADPHY_IDDQ_OVERRIDE_VALUE_OFF;
+ pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
+
+ err = tegra_unpowergate_partition_with_clk_on(TEGRA_POWERGATE_SATA);
+ if (err) {
+ pr_err("%s: ** failed to turn-on SATA (0x%x) **\n",
+ __func__, err);
+ goto exit;
+ }
+
+ /*
+ * place SATA Pad PLL out of reset by writing
+ * SATA_PADPLL_RST_OVERRIDE_VALUE = 0
+ */
+ val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
+ val &= ~PADPLL_RESET_OVERRIDE_VALUE_MASK;
+ val |= PADPLL_RESET_OVERRIDE_VALUE_OFF;
+ clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
+
+ /*
+ * Wait for SATA_AUX_PAD_PLL_CNTL_1_0_LOCKDET to turn 1 with a timeout
+ * of 15 us.
+ */
+ timeout = 15;
+ while (timeout--) {
+ udelay(1);
+ val = misc_readl(SATA_AUX_PAD_PLL_CNTL_1_REG);
+ if (val & LOCKDET_FIELD)
+ break;
+ }
+ if (timeout == 0)
+ pr_err("%s: AUX_PAD_PLL_CNTL_1 (0x%x) is not locked in 15us.\n",
+ __func__, val);
+
+ /* clear SW control of SATA PADPLL, SATA PHY and PLLE */
+ val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
+ val &= ~(PADPLL_IDDQ_SWCTL_MASK | PADPHY_IDDQ_SWCTL_MASK |
+ PLLE_IDDQ_SWCTL_MASK);
+ val |= (PADPLL_IDDQ_SWCTL_OFF | PADPHY_IDDQ_SWCTL_OFF |
+ PLLE_IDDQ_SWCTL_OFF);
+ pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
+
+ val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
+ val &= ~PADPLL_RESET_SWCTL_MASK;
+ val |= PADPLL_RESET_SWCTL_OFF;
+ clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
+
+ /* clear NVA2SATA_OOB_ON_POR in SATA_AUX_MISC_CNTL_1_REG */
+ val = misc_readl(SATA_AUX_MISC_CNTL_1_REG);
+ val &= ~NVA2SATA_OOB_ON_POR_MASK;
+ misc_writel(val, SATA_AUX_MISC_CNTL_1_REG);
+
+ val = sata_readl(SATA_CONFIGURATION_0_OFFSET);
+ val |= EN_FPCI;
+ sata_writel(val, SATA_CONFIGURATION_0_OFFSET);
+
+ /* program sata pad control based on the fuse */
+ tegra_ahci_set_pad_cntrl_regs();
+
+ /*
+ * clear bit T_SATA0_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD of
+ * T_SATA0_CFG_PHY_0
+ */
+ val = scfg_readl(T_SATA0_CFG_PHY_REG);
+ val &= ~PHY_USE_7BIT_ALIGN_DET_FOR_SPD_MASK;
+ scfg_writel(val, T_SATA0_CFG_PHY_REG);
+
+ /*
+ * WAR: Before enabling SATA PLL shutdown, lockdet needs to be ignored.
+ * To ignore lockdet, T_SATA0_DBG0_OFFSET register bit 10 needs to
+ * be 1, and bit 8 needs to be 0.
+ */
+ val = scfg_readl(T_SATA0_DBG0_OFFSET);
+ val |= (1 << 10);
+ val &= ~(1 << 8);
+ scfg_writel(val, T_SATA0_DBG0_OFFSET);
+
+ /* program class code and programming interface for AHCI */
+ val = scfg_readl(TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
+ val |= TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN;
+ scfg_writel(val, TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
+ scfg_writel(TEGRA_PRIVATE_AHCI_CC_BKDR_PGM, TEGRA_PRIVATE_AHCI_CC_BKDR);
+ val &= ~TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN;
+ scfg_writel(val, TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
+
+ /* Program config space registers: */
+
+ /* Enable BUS_MASTER+MEM+IO space, and SERR */
+ val = scfg_readl(TEGRA_SATA_IO_SPACE_OFFSET);
+ val |= TEGRA_SATA_ENABLE_IO_SPACE | TEGRA_SATA_ENABLE_MEM_SPACE |
+ TEGRA_SATA_ENABLE_BUS_MASTER | TEGRA_SATA_ENABLE_SERR;
+ scfg_writel(val, TEGRA_SATA_IO_SPACE_OFFSET);
+
+ /* program bar5 space, by first writing 1's to bar5 register */
+ scfg_writel(TEGRA_SATA_BAR5_INIT_PROGRAM, AHCI_BAR5_CONFIG_LOCATION);
+ /* flush */
+ val = scfg_readl(AHCI_BAR5_CONFIG_LOCATION);
+
+ /* then, write the BAR5_FINAL_PROGRAM address */
+ scfg_writel(TEGRA_SATA_BAR5_FINAL_PROGRAM, AHCI_BAR5_CONFIG_LOCATION);
+ /* flush */
+ scfg_readl(AHCI_BAR5_CONFIG_LOCATION);
+
+ sata_writel((TEGRA_SATA_BAR5_FINAL_PROGRAM >> 8),
+ SATA_FPCI_BAR5_0_OFFSET);
+
+ val = scfg_readl(T_SATA0_AHCI_HBA_CAP_BKDR);
+ val |= (HOST_CAP_ALPM | HOST_CAP_SSC | HOST_CAP_PART);
+ scfg_writel(val, T_SATA0_AHCI_HBA_CAP_BKDR);
+
+ /* enable Interrupt channel */
+ val = pictlr_readl(PRI_ICTLR_CPU_IER_SET_0_OFFSET);
+ val |= CPU_IER_SATA_CTL;
+ pictlr_writel(val, PRI_ICTLR_CPU_IER_SET_0_OFFSET);
+
+ /* set IP_INT_MASK */
+ val = sata_readl(SATA_INTR_MASK_0_OFFSET);
+ val |= IP_INT_MASK;
+ sata_writel(val, SATA_INTR_MASK_0_OFFSET);
+
+exit:
+ if (!IS_ERR_OR_NULL(clk_pllp))
+ clk_put(clk_pllp);
+ if (!IS_ERR_OR_NULL(clk_sata))
+ clk_put(clk_sata);
+ if (!IS_ERR_OR_NULL(clk_sata_oob))
+ clk_put(clk_sata_oob);
+ if (!IS_ERR_OR_NULL(clk_sata_cold))
+ clk_put(clk_sata_cold);
+
+ if (err) {
+ /* turn off all SATA power rails; ignore returned status */
+ tegra_ahci_power_off_rails(tegra_hpriv->power_rails);
+ /* return regulators to system */
+ tegra_ahci_put_rails(tegra_hpriv->power_rails);
+ }
+
+ return err;
+}
+
+static void tegra_ahci_save_initial_config(struct platform_device *pdev,
+ struct ahci_host_priv *hpriv)
+{
+ ahci_save_initial_config(&pdev->dev, hpriv, 0, 0);
+}
+
+static void tegra_ahci_controller_remove(struct platform_device *pdev)
+{
+ struct ata_host *host = dev_get_drvdata(&pdev->dev);
+ struct tegra_ahci_host_priv *tegra_hpriv;
+ int status;
+
+ tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
+
+#ifdef CONFIG_PM
+ /* call tegra_ahci_controller_suspend() to power-down the SATA */
+ status = tegra_ahci_controller_suspend(pdev);
+ if (status)
+ dev_err(host->dev, "remove: error suspend SATA (0x%x)\n",
+ status);
+#else
+ /* power off the sata */
+ status = tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
+ if (status)
+ dev_err(host->dev, "remove: error turn-off SATA (0x%x)\n",
+ status);
+ tegra_ahci_power_off_rails(tegra_hpriv->power_rails);
+#endif
+
+ /* return system resources */
+ tegra_ahci_put_rails(tegra_hpriv->power_rails);
+}
+
+#ifdef CONFIG_PM
+static int tegra_ahci_controller_suspend(struct platform_device *pdev)
+{
+ struct ata_host *host = dev_get_drvdata(&pdev->dev);
+ struct tegra_ahci_host_priv *tegra_hpriv;
+ unsigned long flags;
+
+ tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
+
+ /* stop the idle timer */
+ if (timer_pending(&tegra_hpriv->idle_timer))
+ del_timer_sync(&tegra_hpriv->idle_timer);
+
+ spin_lock_irqsave(&host->lock, flags);
+ if (tegra_hpriv->pg_state == SATA_OFF)
+ dev_dbg(host->dev, "suspend: SATA already power gated\n");
+ else {
+ bool pg_ok;
+
+ dev_dbg(host->dev, "suspend: power gating SATA...\n");
+ pg_ok = tegra_ahci_power_gate(host);
+ if (pg_ok) {
+ tegra_hpriv->pg_state = SATA_OFF;
+ dev_dbg(host->dev, "suspend: SATA is power gated\n");
+ } else {
+ dev_err(host->dev, "suspend: abort power gating\n");
+ tegra_ahci_abort_power_gate(host);
+ spin_unlock_irqrestore(&host->lock, flags);
+ return -EBUSY;
+ }
+ }
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ return tegra_ahci_power_off_rails(tegra_hpriv->power_rails);
+}
+
+static int tegra_ahci_controller_resume(struct platform_device *pdev)
+{
+ struct ata_host *host = dev_get_drvdata(&pdev->dev);
+ struct tegra_ahci_host_priv *tegra_hpriv;
+ unsigned long flags;
+ int err;
+
+ tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
+
+ err = tegra_ahci_power_on_rails(tegra_hpriv->power_rails);
+ if (err) {
+ pr_err("%s: fails to power on rails (%d)\n", __func__, err);
+ return err;
+ }
+
+ spin_lock_irqsave(&host->lock, flags);
+ if (!tegra_hpriv->pg_state == SATA_ON) {
+ dev_dbg(host->dev, "resume: SATA already powered on\n");
+ } else {
+ dev_dbg(host->dev, "resume: powering on SATA...\n");
+ tegra_ahci_power_un_gate(host);
+ tegra_hpriv->pg_state = SATA_ON;
+ }
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ return 0;
+}
+
+static int tegra_ahci_suspend(struct platform_device *pdev, pm_message_t mesg)
+{
+ struct ata_host *host = dev_get_drvdata(&pdev->dev);
+ void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
+ u32 ctl;
+ int rc;
+
+ dev_dbg(host->dev, "** entering %s: **\n", __func__);
+ if (mesg.event & PM_EVENT_SLEEP) {
+ /*
+ * AHCI spec rev1.1 section 8.3.3:
+ * Software must disable interrupts prior to requesting a
+ * transition of the HBA to D3 state.
+ */
+ ctl = readl(mmio + HOST_CTL);
+ ctl &= ~HOST_IRQ_EN;
+ writel(ctl, mmio + HOST_CTL);
+ readl(mmio + HOST_CTL); /* flush */
+ }
+
+ rc = ata_host_suspend(host, mesg);
+ if (rc)
+ return rc;
+
+ return tegra_ahci_controller_suspend(pdev);
+}
+
+static int tegra_ahci_resume(struct platform_device *pdev)
+{
+ struct ata_host *host = dev_get_drvdata(&pdev->dev);
+ int rc;
+
+ dev_dbg(host->dev, "** entering %s: **\n", __func__);
+ rc = tegra_ahci_controller_resume(pdev);
+ if (rc)
+ return rc;
+
+ if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
+ rc = ahci_reset_controller(host);
+ if (rc)
+ return rc;
+
+ ahci_init_controller(host);
+ }
+
+ ata_host_resume(host);
+ return 0;
+}
+
+#ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
+static int tegra_ahci_runtime_suspend(struct device *dev)
+{
+ struct ata_host *host;
+ struct tegra_ahci_host_priv *tegra_hpriv;
+ bool pg_ok;
+ unsigned long flags;
+ int err = 0;
+
+ host = dev_get_drvdata(dev);
+ tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ switch (tegra_hpriv->pg_state) {
+ case SATA_OFF:
+ dev_dbg(dev, "** rt-suspend: already power gated **\n");
+ break;
+
+ case SATA_ABORT_OFF:
+ dev_dbg(dev, "** rt-suspend: abort suspend **\n");
+ pm_runtime_get_noresume(dev);
+ tegra_hpriv->pg_state = SATA_ON;
+ tegra_ahci_dequeue_qcs(tegra_hpriv);
+ err = -EBUSY;
+ break;
+
+ case SATA_ON:
+ case SATA_GOING_OFF:
+ if (tegra_ahci_are_all_ports_idle(host)) {
+ /* if all ports are in idle, do power-gate */
+ dev_dbg(dev, "** rt-suspend: power-down sata (%u) **\n",
+ tegra_hpriv->pg_state);
+ pg_ok = tegra_ahci_power_gate(host);
+ dev_dbg(dev, "** rt-suspend: done **\n");
+ if (pg_ok) {
+ tegra_hpriv->pg_state = SATA_OFF;
+ } else {
+ dev_err(dev, "** rt-suspend: abort pg **\n");
+ tegra_ahci_abort_power_gate(host);
+ tegra_hpriv->pg_state = SATA_ON;
+ err = -EBUSY;
+ }
+ } else {
+ dev_dbg(dev, "** rt-suspend: port not idle (%u) **\n",
+ tegra_hpriv->pg_state);
+ err = -EBUSY;
+ }
+ break;
+
+ case SATA_GOING_ON:
+ default:
+ dev_err(dev, "** rt-suspend: bad state (%u) **\n",
+ tegra_hpriv->pg_state);
+ WARN_ON(1);
+ err = -EBUSY;
+ break;
+
+ }
+
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ return err;
+}
+
+static int tegra_ahci_runtime_resume(struct device *dev)
+{
+ struct ata_host *host;
+ struct tegra_ahci_host_priv *tegra_hpriv;
+ unsigned long flags;
+ int err = 0;
+
+ host = dev_get_drvdata(dev);
+ tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ if (tegra_hpriv->pg_state == SATA_ON) {
+ dev_dbg(dev, "** rt-resume: already power ungated **\n");
+ goto exit;
+ }
+
+ if ((tegra_hpriv->pg_state == SATA_OFF) ||
+ (tegra_hpriv->pg_state == SATA_GOING_ON)) {
+ dev_dbg(dev, "** rt-resume: power-up sata (%u) **\n",
+ tegra_hpriv->pg_state);
+ tegra_ahci_power_un_gate(host);
+ dev_dbg(dev, "** rt-resume: done **\n");
+ tegra_hpriv->pg_state = SATA_ON;
+
+ /* now qc_issue all qcs in the qc_list */
+ tegra_ahci_dequeue_qcs(tegra_hpriv);
+ } else {
+ dev_err(dev, "** rt-resume: bad state (%u) **\n",
+ tegra_hpriv->pg_state);
+ WARN_ON(1);
+ err = -EBUSY;
+ }
+
+exit:
+ spin_unlock_irqrestore(&host->lock, flags);
+ return err;
+}
+#endif
+
+static u16 pg_save_bar5_registers[] = {
+ 0x018, /* T_AHCI_HBA_CCC_PORTS */
+ 0x004, /* T_AHCI_HBA_GHC */
+ 0x014, /* T_AHCI_HBA_CCC_CTL - OP (optional) */
+ 0x01C, /* T_AHCI_HBA_EM_LOC */
+ 0x020 /* T_AHCI_HBA_EM_CTL - OP */
+};
+
+static u16 pg_save_bar5_port_registers[] = {
+ 0x100, /* T_AHCI_PORT_PXCLB */
+ 0x104, /* T_AHCI_PORT_PXCLBU */
+ 0x108, /* T_AHCI_PORT_PXFB */
+ 0x10C, /* T_AHCI_PORT_PXFBU */
+ 0x114, /* T_AHCI_PORT_PXIE */
+ 0x118, /* T_AHCI_PORT_PXCMD */
+ 0x12C /* T_AHCI_PORT_PXSCTL */
+};
+
+/*
+ * pg_save_bar5_bkdr_registers:
+ * These registers in BAR5 are read only.
+ * To restore back those register values, write the saved value
+ * to the registers specified in pg_restore_bar5_bkdr_registers[].
+ * These pg_restore_bar5_bkdr_registers[] are in SATA_CONFIG space.
+ */
+static u16 pg_save_bar5_bkdr_registers[] = {
+ /* Save and restore via bkdr writes */
+ 0x000, /* T_AHCI_HBA_CAP */
+ 0x00C, /* T_AHCI_HBA_PI */
+ 0x024 /* T_AHCI_HBA_CAP2 */
+};
+
+static u16 pg_restore_bar5_bkdr_registers[] = {
+ /* Save and restore via bkdr writes */
+ 0x300, /* BKDR of T_AHCI_HBA_CAP */
+ 0x33c, /* BKDR of T_AHCI_HBA_PI */
+ 0x330 /* BKDR of T_AHCI_HBA_CAP2 */
+};
+
+/* These registers are saved for each port */
+static u16 pg_save_bar5_bkdr_port_registers[] = {
+ 0x120, /* NV_PROJ__SATA0_CHX_AHCI_PORT_PXTFD */
+ 0x124, /* NV_PROJ__SATA0_CHX_AHCI_PORT_PXSIG */
+ 0x128 /* NV_PROJ__SATA0_CHX_AHCI_PORT_PXSSTS */
+};
+
+static u16 pg_restore_bar5_bkdr_port_registers[] = {
+ /* Save and restore via bkdr writes */
+ 0x790, /* BKDR of NV_PROJ__SATA0_CHX_AHCI_PORT_PXTFD */
+ 0x794, /* BKDR of NV_PROJ__SATA0_CHX_AHCI_PORT_PXSIG */
+ 0x798 /* BKDR of NV_PROJ__SATA0_CHX_AHCI_PORT_PXSSTS */
+};
+
+static u16 pg_save_config_registers[] = {
+ 0x004, /* T_SATA0_CFG_1 */
+ 0x00C, /* T_SATA0_CFG_3 */
+ 0x024, /* T_SATA0_CFG_9 */
+ 0x028, /* T_SATA0_CFG_10 */
+ 0x030, /* T_SATA0_CFG_12 */
+ 0x034, /* T_SATA0_CFG_13 */
+ 0x038, /* T_SATA0_CFG_14 */
+ 0x03C, /* T_SATA0_CFG_15 */
+ 0x040, /* T_SATA0_CFG_16 */
+ 0x044, /* T_SATA0_CFG_17 */
+ 0x048, /* T_SATA0_CFG_18 */
+ 0x0B0, /* T_SATA0_MSI_CTRL */
+ 0x0B4, /* T_SATA0_MSI_ADDR1 */
+ 0x0B8, /* T_SATA0_MSI_ADDR2 */
+ 0x0BC, /* T_SATA0_MSI_DATA */
+ 0x0C0, /* T_SATA0_MSI_QUEUE */
+ 0x0EC, /* T_SATA0_MSI_MAP */
+ 0x124, /* T_SATA0_CFG_PHY_POWER */
+ 0x128, /* T_SATA0_CFG_PHY_POWER_1 */
+ 0x12C, /* T_SATA0_CFG_PHY_1 */
+ 0x174, /* T_SATA0_CFG_LINK_0 */
+ 0x178, /* T_SATA0_CFG_LINK_1 */
+ 0x1D0, /* MCP_SATA0_CFG_TRANS_0 */
+ 0x238, /* T_SATA0_ALPM_CTRL */
+ 0x30C, /* T_SATA0_AHCI_HBA_CYA_0 */
+ 0x320, /* T_SATA0_AHCI_HBA_SPARE_1 */
+ 0x324, /* T_SATA0_AHCI_HBA_SPARE_2 */
+ 0x328, /* T_SATA0_AHCI_HBA_DYN_CLK_CLAMP */
+ 0x32C, /* T_SATA0_AHCI_CFG_ERR_CTRL */
+ 0x338, /* T_SATA0_AHCI_HBA_CYA_1 */
+ 0x340, /* T_SATA0_AHCI_HBA_PRE_STAGING_CONTROL */
+ 0x430, /* T_SATA0_CFG_FPCI_0 */
+ 0x494, /* T_SATA0_CFG_ESATA_CTRL */
+ 0x4A0, /* T_SATA0_CYA1 */
+ 0x4B0, /* T_SATA0_CFG_GLUE */
+ 0x534, /* T_SATA0_PHY_CTRL */
+ 0x540, /* T_SATA0_CTRL */
+ 0x550, /* T_SATA0_DBG0 */
+ 0x554 /* T_SATA0_LOW_POWER_COUNT */
+};
+
+static u16 pg_save_config_port_registers[] = {
+ /* Save and restore per port */
+ /* need to have port selected */
+ 0x530, /* T_SATA0_CHXCFG1 */
+ 0x684, /* T_SATA0_CHX_MISC */
+ 0x700, /* T_SATA0_CHXCFG3 */
+ 0x704, /* T_SATA0_CHXCFG4_CHX */
+ 0x690, /* T_SATA0_CHX_PHY_CTRL1_GEN1 */
+ 0x694, /* T_SATA0_CHX_PHY_CTRL1_GEN2 */
+ 0x698, /* T_SATA0_CHX_PHY_CTRL1_GEN3 */
+ 0x69C, /* T_SATA0_CHX_PHY_CTRL_2 */
+ 0x6B0, /* T_SATA0_CHX_PHY_CTRL_3 */
+ 0x6B4, /* T_SATA0_CHX_PHY_CTRL_4 */
+ 0x6B8, /* T_SATA0_CHX_PHY_CTRL_5 */
+ 0x6BC, /* T_SATA0_CHX_PHY_CTRL_6 */
+ 0x714, /* T_SATA0_PRBS_CHX - OP */
+ 0x750, /* T_SATA0_CHX_LINK0 */
+ 0x7F0 /* T_SATA0_CHX_GLUE */
+};
+
+static u16 pg_save_ipfs_registers[] = {
+ 0x094, /* SATA_FPCI_BAR5_0 */
+ 0x0C0, /* SATA_MSI_BAR_SZ_0 */
+ 0x0C4, /* SATA_MSI_AXI_BAR_ST_0 */
+ 0x0C8, /* SATA_MSI_FPCI_BAR_ST_0 */
+ 0x140, /* SATA_MSI_EN_VEC0_0 */
+ 0x144, /* SATA_MSI_EN_VEC1_0 */
+ 0x148, /* SATA_MSI_EN_VEC2_0 */
+ 0x14C, /* SATA_MSI_EN_VEC3_0 */
+ 0x150, /* SATA_MSI_EN_VEC4_0 */
+ 0x154, /* SATA_MSI_EN_VEC5_0 */
+ 0x158, /* SATA_MSI_EN_VEC6_0 */
+ 0x15C, /* SATA_MSI_EN_VEC7_0 */
+ 0x180, /* SATA_CONFIGURATION_0 */
+ 0x184, /* SATA_FPCI_ERROR_MASKS_0 */
+ 0x188, /* SATA_INTR_MASK_0 */
+ 0x1A0, /* SATA_CFG_REVID_0 */
+ 0x198, /* SATA_IPFS_INTR_ENABLE_0 */
+ 0x1BC, /* SATA_CLKGATE_HYSTERSIS_0 */
+ 0x1DC /* SATA_SATA_MCCIF_FIFOCTRL_0 */
+};
+
+static void tegra_ahci_save_regs(u32 **save_addr,
+ u32 reg_base,
+ u16 reg_array[],
+ u32 regs)
+{
+ u32 i;
+ u32 *dest = (u32 *)*save_addr;
+ u32 base = (u32)IO_ADDRESS(reg_base);
+
+ for (i = 0; i < regs; ++i, ++dest) {
+ *dest = readl(base + (u32)reg_array[i]);
+ AHCI_DBG_PRINT("save: [0x%x]=0x%08x\n",
+ (reg_base+(u32)reg_array[i]), *dest);
+ }
+ *save_addr = dest;
+}
+
+static void tegra_ahci_restore_regs(void **save_addr,
+ u32 reg_base,
+ u16 reg_array[],
+ u32 regs)
+{
+ u32 i;
+ u32 *src = (u32 *)*save_addr;
+ u32 base = (u32)IO_ADDRESS(reg_base);
+
+ for (i = 0; i < regs; ++i, ++src) {
+ writel(*src, base + (u32)reg_array[i]);
+ AHCI_DBG_PRINT("restore: [0x%x]=0x%08x\n",
+ (reg_base+(u32)reg_array[i]), *src);
+ }
+ *save_addr = src;
+}
+
+static void tegra_ahci_pg_save_registers(struct ata_host *host)
+{
+ struct tegra_ahci_host_priv *tegra_hpriv;
+ u32 *pg_save;
+ u32 regs;
+ int i;
+
+ tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
+ pg_save = tegra_hpriv->pg_save;
+
+ /*
+ * Driver should save/restore the registers in the order of
+ * IPFS, CFG, Ext CFG, BAR5.
+ */
+
+ /* save IPFS registers */
+ regs = ARRAY_SIZE(pg_save_ipfs_registers);
+ tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BASE,
+ pg_save_ipfs_registers, regs);
+ /* after the call, pg_save should point to the next address to save */
+
+ /* save CONFIG registers */
+ regs = ARRAY_SIZE(pg_save_config_registers);
+ tegra_ahci_save_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
+ pg_save_config_registers, regs);
+
+ /* save CONFIG per port registers */
+ for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
+ scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
+ regs = ARRAY_SIZE(pg_save_config_port_registers);
+ tegra_ahci_save_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
+ pg_save_config_port_registers, regs);
+ }
+ scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
+
+ /* save BAR5 registers */
+ regs = ARRAY_SIZE(pg_save_bar5_registers);
+ tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BAR5_BASE,
+ pg_save_bar5_registers, regs);
+
+ /* save BAR5 port_registers */
+ regs = ARRAY_SIZE(pg_save_bar5_port_registers);
+ for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i)
+ tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BAR5_BASE + (0x80*i),
+ pg_save_bar5_port_registers, regs);
+
+ /* save bkdr registers */
+ regs = ARRAY_SIZE(pg_save_bar5_bkdr_registers);
+ tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BAR5_BASE,
+ pg_save_bar5_bkdr_registers, regs);
+
+ /* and save bkdr per_port registers */
+ for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
+ scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
+ regs = ARRAY_SIZE(pg_save_bar5_bkdr_port_registers);
+ tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BAR5_BASE + (0x80*i),
+ pg_save_bar5_bkdr_port_registers,
+ regs);
+ }
+ scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
+}
+
+static void tegra_ahci_pg_restore_registers(struct ata_host *host)
+{
+ struct tegra_ahci_host_priv *tegra_hpriv;
+ void *pg_save;
+ u32 regs, val;
+ int i;
+
+ tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
+ pg_save = tegra_hpriv->pg_save;
+
+ /*
+ * Driver should restore the registers in the order of
+ * IPFS, CFG, Ext CFG, BAR5.
+ */
+
+ /* restore IPFS registers */
+ regs = ARRAY_SIZE(pg_save_ipfs_registers);
+ tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_BASE,
+ pg_save_ipfs_registers, regs);
+ /* after the call, pg_save should point to the next addr to restore */
+
+ /* restore CONFIG registers */
+ regs = ARRAY_SIZE(pg_save_config_registers);
+ tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
+ pg_save_config_registers, regs);
+
+ /* restore CONFIG per port registers */
+ for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
+ scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
+ regs = ARRAY_SIZE(pg_save_config_port_registers);
+ tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
+ pg_save_config_port_registers,
+ regs);
+ }
+ scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
+
+ /* restore BAR5 registers */
+ regs = ARRAY_SIZE(pg_save_bar5_registers);
+ tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_BAR5_BASE,
+ pg_save_bar5_registers, regs);
+
+ /* restore BAR5 port_registers */
+ regs = ARRAY_SIZE(pg_save_bar5_port_registers);
+ for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i)
+ tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_BAR5_BASE+(0x80*i),
+ pg_save_bar5_port_registers, regs);
+
+ /* restore bkdr registers */
+ regs = ARRAY_SIZE(pg_restore_bar5_bkdr_registers);
+ tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
+ pg_restore_bar5_bkdr_registers, regs);
+
+ /* and restore BAR5 bkdr per_port registers */
+ for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
+ scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
+ regs = ARRAY_SIZE(pg_restore_bar5_bkdr_port_registers);
+ tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
+ pg_restore_bar5_bkdr_port_registers,
+ regs);
+ }
+ scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
+
+ /* program class code and programming interface for AHCI */
+ val = scfg_readl(TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
+ val |= TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN;
+ scfg_writel(val, TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
+ scfg_writel(TEGRA_PRIVATE_AHCI_CC_BKDR_PGM, TEGRA_PRIVATE_AHCI_CC_BKDR);
+ val &= ~TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN;
+ scfg_writel(val, TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
+}
+
+static u32 tegra_ahci_port_error(struct ata_port *ap)
+{
+ void __iomem *port_mmio = ahci_port_base(ap);
+ u32 err_status;
+
+ err_status = readl(port_mmio + PORT_IRQ_STAT);
+ /* excludes PhyRdy and Connect Change status */
+ err_status &= (PORT_IRQ_ERROR & (~(PORT_IRQ_PHYRDY|PORT_IRQ_CONNECT)));
+ return err_status;
+}
+
+static bool tegra_ahci_check_errors(struct ata_host *host)
+{ int i;
+ struct ata_port *ap;
+ u32 err;
+
+ for (i = 0; i < host->n_ports; i++) {
+ ap = host->ports[i];
+ err = tegra_ahci_port_error(ap);
+ if (err) {
+ dev_err(host->dev,
+ "pg-chk-err = 0x%08x on port %d\n", err, i);
+ return true;
+ }
+ }
+ return false;
+}
+
+static void tegra_ahci_abort_power_gate(struct ata_host *host)
+{
+ u32 val;
+
+ val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
+ val &= ~PG_INFO_MASK;
+ val |= PG_INFO_OFF;
+ pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
+}
+
+static bool tegra_ahci_power_gate(struct ata_host *host)
+{
+ u32 val;
+ u32 dat;
+ struct tegra_ahci_host_priv *tegra_hpriv;
+ int status;
+
+ tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
+
+ val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
+ val &= ~PG_INFO_MASK;
+ val |= PG_INFO_ON;
+ pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
+
+ tegra_ahci_pg_save_registers(host);
+
+ /*
+ * Read SATA_AUX_MISC_CNTL_1_0 register L0_RX_IDLE_T_SAX field and
+ * write that value into same register L0_RX_IDLE_T_NPG field.
+ * And write 1 to L0_RX_IDLE_T_MUX field.
+ */
+ val = misc_readl(SATA_AUX_MISC_CNTL_1_REG);
+ dat = val;
+ dat &= L0_RX_IDLE_T_SAX_MASK;
+ dat >>= L0_RX_IDLE_T_SAX_SHIFT;
+ dat <<= L0_RX_IDLE_T_NPG_SHIFT;
+ val &= ~L0_RX_IDLE_T_NPG_MASK;
+ val |= dat;
+ val &= ~L0_RX_IDLE_T_MUX_MASK;
+ val |= L0_RX_IDLE_T_MUX_FROM_APB_MISC;
+ misc_writel(val, SATA_AUX_MISC_CNTL_1_REG);
+
+ /* abort PG if there are errors occurred */
+ if (tegra_ahci_check_errors(host)) {
+ dev_err(host->dev, "** pg: errors; abort power gating **\n");
+ return false;
+ }
+ /* make sure all ports have no outstanding commands and are idle. */
+ if (!tegra_ahci_are_all_ports_idle(host)) {
+ dev_err(host->dev, "** pg: cmds; abort power gating **\n");
+ return false;
+ }
+
+ /*
+ * Hw wake up is not needed:
+ * Driver/RM shall place the SATA PHY and SATA PADPLL in IDDQ.
+ * SATA_PADPLL_RESET_SWCTL =1
+ * SATA_PADPLL_RESET_OVERRIDE_VALUE=1
+ * SATA_PADPHY_IDDQ_SWCTL=1
+ * SATA_PADPHY_IDDQ_OVERRIDE_VALUE=1
+ */
+ val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
+ val &= ~(PADPLL_RESET_SWCTL_MASK | PADPLL_RESET_OVERRIDE_VALUE_MASK);
+ val |= (PADPLL_RESET_SWCTL_ON | PADPLL_RESET_OVERRIDE_VALUE_ON);
+ clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
+ val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
+ val &= ~(PADPHY_IDDQ_OVERRIDE_VALUE_MASK | PADPHY_IDDQ_SWCTL_MASK);
+ val |= (PADPHY_IDDQ_SWCTL_ON | PADPHY_IDDQ_OVERRIDE_VALUE_ON);
+ pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
+
+ /* Wait for time specified in SATA_LANE_IDDQ2_PADPLL_IDDQ */
+ val = clk_readl(CLK_RST_SATA_PLL_CFG1_REG);
+ dat = (val & IDDQ2LANE_IDDQ_DLY_MASK) >> IDDQ2LANE_IDDQ_DLY_SHIFT;
+ udelay(dat);
+
+ /* SATA_PADPLL_IDDQ_SWCTL=1 & SATA_PADPLL_IDDQ_OVERRIDE_VALUE=1 */
+ val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
+ val &= ~(PADPLL_IDDQ_OVERRIDE_VALUE_MASK | PADPLL_IDDQ_SWCTL_MASK);
+ val |= (PADPLL_IDDQ_SWCTL_ON | PADPLL_IDDQ_OVERRIDE_VALUE_ON);
+ pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
+
+ /* power off the sata */
+ status = tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
+ if (status)
+ dev_err(host->dev, "** failed to turn-off SATA (0x%x) **\n",
+ status);
+
+ return true;
+}
+
+static bool tegra_ahci_power_un_gate(struct ata_host *host)
+{
+ u32 val;
+ u32 dat;
+ u32 timeout;
+ struct tegra_ahci_host_priv *tegra_hpriv;
+ int status;
+
+ tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
+
+ /* get sata phy and pll out of iddq: */
+ val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
+ val &= ~PADPLL_IDDQ_OVERRIDE_VALUE_MASK;
+ val |= PADPLL_IDDQ_OVERRIDE_VALUE_OFF;
+ pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
+ /* wait for delay of IDDQ2LAND_SLUMBER_DLY */
+ val = clk_readl(CLK_RST_SATA_PLL_CFG1_REG);
+ dat = (val & IDDQ2LANE_SLUMBER_DLY_MASK) >> IDDQ2LANE_SLUMBER_DLY_SHIFT;
+ udelay(dat);
+ val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
+ val &= ~PADPHY_IDDQ_OVERRIDE_VALUE_MASK;
+ val |= PADPHY_IDDQ_OVERRIDE_VALUE_OFF;
+ pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
+
+ status = tegra_unpowergate_partition_with_clk_on(TEGRA_POWERGATE_SATA);
+ if (status)
+ dev_err(host->dev, "** failed to turn-on SATA (0x%x) **\n",
+ status);
+
+ /* deasset PADPLL and wait until it locks. */
+ val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
+ val &= ~PADPLL_RESET_OVERRIDE_VALUE_MASK;
+ val |= PADPLL_RESET_OVERRIDE_VALUE_OFF;
+ clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
+
+ /*
+ * Wait for SATA_AUX_PAD_PLL_CNTL_1_0_LOCKDET to turn 1 with a timeout
+ * of 15 us.
+ */
+ timeout = 15;
+ while (timeout--) {
+ udelay(1);
+ val = misc_readl(SATA_AUX_PAD_PLL_CNTL_1_REG);
+ if (val & LOCKDET_FIELD)
+ break;
+ }
+ if (timeout == 0)
+ pr_err("%s: SATA_PAD_PLL is not locked in 15us.\n", __func__);
+
+ /* restore registers */
+ tegra_ahci_pg_restore_registers(host);
+
+ /*
+ * During the restoration of the registers, the driver would now need to
+ * restore the register T_SATA0_CFG_POWER_GATE_SSTS_RESTORED after the
+ * ssts_det, ssts_spd are restored. This register is used to tell the
+ * controller whether a drive existed earlier or not and move the PHY
+ * state machines into either HR_slumber or not.
+ */
+ val = scfg_readl(T_SATA0_CFG_POWER_GATE);
+ val &= ~POWER_GATE_SSTS_RESTORED_MASK;
+ val |= POWER_GATE_SSTS_RESTORED_YES;
+ scfg_writel(val, T_SATA0_CFG_POWER_GATE);
+
+ /*
+ * Driver needs to switch the rx_idle_t driven source back to from
+ * Sata controller after SAX is power-ungated.
+ */
+ val = misc_readl(SATA_AUX_MISC_CNTL_1_REG);
+ val &= ~L0_RX_IDLE_T_MUX_MASK;
+ val |= L0_RX_IDLE_T_MUX_FROM_SATA;
+ misc_writel(val, SATA_AUX_MISC_CNTL_1_REG);
+
+ /*
+ * Driver can start to use main SATA interrupt instead of the
+ * rx_stat_t interrupt.
+ */
+ val = pictlr_readl(PRI_ICTLR_CPU_IER_SET_0_OFFSET);
+ val |= CPU_IER_SATA_CTL;
+ pictlr_writel(val, PRI_ICTLR_CPU_IER_SET_0_OFFSET);
+
+ /* Set the bits in the CAR to allow HW based low power sequencing. */
+ val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
+ val &= ~PADPLL_RESET_SWCTL_MASK;
+ val |= PADPLL_RESET_SWCTL_OFF;
+ clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
+
+ /*
+ * power un-gating process is complete by clearing
+ * APBDEV_PMC_SATA_PWRGT_0.Pmc2sata_pg_info = 0
+ */
+ val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
+ val &= ~PG_INFO_MASK;
+ val |= PG_INFO_OFF;
+ pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
+
+ return true;
+}
+
+static enum port_idle_status tegra_ahci_is_port_idle(struct ata_port *ap)
+{
+ void __iomem *port_mmio = ahci_port_base(ap);
+
+ if (readl(port_mmio + PORT_CMD_ISSUE) ||
+ readl(port_mmio + PORT_SCR_ACT))
+ return PORT_IS_NOT_IDLE;
+ return PORT_IS_IDLE;
+}
+
+static enum port_idle_status tegra_ahci_is_port_slumber(struct ata_port *ap)
+{
+ void __iomem *port_mmio = ahci_port_base(ap);
+ u32 sstat;
+
+ if (tegra_ahci_is_port_idle(ap) == PORT_IS_NOT_IDLE)
+ return PORT_IS_NOT_IDLE;
+
+ /* return 1 if PORT_SCR_STAT is in IPM_SLUMBER_STATE */
+ sstat = readl(port_mmio + PORT_SCR_STAT);
+ if ((sstat & SSTAT_IPM_STATE_MASK) == SSTAT_IPM_SLUMBER_STATE)
+ return PORT_IS_SLUMBER;
+ return PORT_IS_IDLE_NOT_SLUMBER;
+}
+
+/* check if all supported ports are idle (no outstanding commands) */
+static bool tegra_ahci_are_all_ports_idle(struct ata_host *host)
+{ int i;
+ struct ata_port *ap;
+
+ for (i = 0; i < host->n_ports; i++) {
+ ap = host->ports[i];
+ if (ap && (tegra_ahci_is_port_idle(ap) == PORT_IS_NOT_IDLE))
+ return false;
+ }
+ return true;
+}
+
+/* check if all supported ports are in slumber */
+static bool tegra_ahci_are_all_ports_slumber(struct ata_host *host)
+{ int i;
+ struct ata_port *ap;
+
+ for (i = 0; i < host->n_ports; i++) {
+ ap = host->ports[i];
+ if (ap && (tegra_ahci_is_port_slumber(ap) != PORT_IS_SLUMBER))
+ return false;
+ }
+ return true;
+}
+
+#ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
+static void tegra_ahci_to_add_idle_timer(struct ata_host *host)
+{
+ struct tegra_ahci_host_priv *tegra_hpriv;
+
+ tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
+
+ /* note: the routine is called from interrupt context */
+ spin_lock(&host->lock);
+ /* start idle-timer if all ports have no outstanding commands */
+ if (tegra_ahci_are_all_ports_idle(host)) {
+ /* adjust tegra_ahci_idle_time to minimum if it is too small */
+ tegra_ahci_idle_time = max((u32)TEGRA_AHCI_MIN_IDLE_TIME,
+ tegra_ahci_idle_time);
+ tegra_hpriv->idle_timer.expires =
+ ata_deadline(jiffies, tegra_ahci_idle_time);
+ mod_timer(&tegra_hpriv->idle_timer,
+ tegra_hpriv->idle_timer.expires);
+ }
+ spin_unlock(&host->lock);
+}
+
+static void tegra_ahci_idle_timer(unsigned long arg)
+{
+ struct ata_host *host = (void *)arg;
+ struct tegra_ahci_host_priv *tegra_hpriv;
+ unsigned long flags;
+
+ tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
+
+ spin_lock_irqsave(&host->lock, flags);
+ if (tegra_hpriv->pg_state == SATA_ON)
+ tegra_hpriv->pg_state = SATA_GOING_OFF;
+ else {
+ dev_err(host->dev, "idle_timer: bad state (%u)\n",
+ tegra_hpriv->pg_state);
+ WARN_ON(1);
+ spin_unlock_irqrestore(&host->lock, flags);
+ return;
+ }
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ pm_runtime_put(tegra_hpriv->dev);
+}
+
+static int tegra_ahci_queue_one_qc(struct tegra_ahci_host_priv *tegra_hpriv,
+ struct ata_queued_cmd *qc)
+{
+ struct tegra_qc_list *qc_list;
+
+ qc_list = kmalloc(sizeof(struct tegra_qc_list), GFP_ATOMIC);
+ if (!qc_list) {
+ dev_err(tegra_hpriv->dev, "failed to alloc qc_list\n");
+ return AC_ERR_SYSTEM;
+ }
+ qc_list->qc = qc;
+ list_add_tail(&(qc_list->list), &(tegra_hpriv->qc_list));
+ dev_dbg(tegra_hpriv->dev, "queuing qc=%x\n", (unsigned int)qc);
+ return 0;
+}
+
+static void tegra_ahci_dequeue_qcs(struct tegra_ahci_host_priv *tegra_hpriv)
+{
+ struct list_head *list, *next;
+ struct tegra_qc_list *qc_list;
+ struct ata_queued_cmd *qc;
+
+ /* now qc_issue all qcs in the qc_list */
+ list_for_each_safe(list, next, &tegra_hpriv->qc_list) {
+ qc_list = list_entry(list, struct tegra_qc_list, list);
+ qc = qc_list->qc;
+ dev_dbg(tegra_hpriv->dev, "dequeue qc=%x\n", (unsigned int)qc);
+ ahci_ops.qc_issue(qc);
+ list_del(list);
+ kfree(qc_list);
+ }
+}
+
+static unsigned int tegra_ahci_qc_issue(struct ata_queued_cmd *qc)
+{
+ struct ata_port *ap = qc->ap;
+ struct ata_host *host = ap->host;
+ struct tegra_ahci_host_priv *tegra_hpriv = host->private_data;
+ int rc;
+
+ /* stop the idle timer */
+ if (timer_pending(&tegra_hpriv->idle_timer))
+ del_timer_sync(&tegra_hpriv->idle_timer);
+
+ /* note: host->lock is locked */
+ switch (tegra_hpriv->pg_state) {
+ case SATA_ON:
+ /* normal case, issue the qc */
+ return ahci_ops.qc_issue(qc);
+ case SATA_GOING_OFF:
+ case SATA_ABORT_OFF:
+ /* SATA is going OFF, let's abort the suspend */
+ dev_dbg(host->dev, "** qc_issue: going OFF **\n");
+ tegra_hpriv->pg_state = SATA_ABORT_OFF;
+ return tegra_ahci_queue_one_qc(tegra_hpriv, qc);
+ case SATA_OFF:
+ dev_dbg(host->dev, "** qc_issue: request power-up sata **\n");
+ rc = pm_runtime_get(tegra_hpriv->dev);
+ /* rc == 0 means the request has been queued successfully */
+ if (rc) {
+ dev_err(host->dev, "** qc_issue: rt_get()=%d **\n",
+ rc);
+ WARN_ON(1);
+ return AC_ERR_SYSTEM;
+ }
+ tegra_hpriv->pg_state = SATA_GOING_ON;
+ /* continue with the following code to queue the qc */
+ case SATA_GOING_ON:
+ return tegra_ahci_queue_one_qc(tegra_hpriv, qc);
+ default:
+ dev_err(host->dev, "** qc_issue: bad state (%u) **\n",
+ tegra_hpriv->pg_state);
+ WARN_ON(1);
+ return AC_ERR_SYSTEM;
+ }
+}
+
+static int tegra_ahci_hardreset(struct ata_link *link, unsigned int *class,
+ unsigned long deadline)
+{
+ struct ata_port *ap = link->ap;
+ struct ata_host *host = ap->host;
+ struct tegra_ahci_host_priv *tegra_hpriv = host->private_data;
+ int rc;
+
+ if (tegra_hpriv->pg_state == SATA_OFF) {
+ dev_dbg(host->dev, "** hreset: request power-up sata **\n");
+ rc = pm_runtime_get_sync(tegra_hpriv->dev);
+ /* rc == 0 means the request has been run successfully */
+ if (rc) {
+ dev_err(host->dev, "** hreset: rt_get()=%d **\n", rc);
+ WARN_ON(1);
+ return AC_ERR_SYSTEM;
+ }
+ tegra_hpriv->pg_state = SATA_ON;
+ }
+
+ return ahci_ops.hardreset(link, class, deadline);
+}
+
+static irqreturn_t tegra_ahci_interrupt(int irq, void *dev_instance)
+{
+ irqreturn_t irq_retval;
+
+ irq_retval = ahci_interrupt(irq, dev_instance);
+ if (irq_retval == IRQ_NONE)
+ return IRQ_NONE;
+
+#ifdef CONFIG_PM
+ tegra_ahci_to_add_idle_timer((struct ata_host *)dev_instance);
+#endif
+
+ return irq_retval;
+}
+#endif
+#endif
+
+static int __devexit tegra_ahci_remove_one(struct platform_device *pdev)
+{
+ struct ata_host *host = dev_get_drvdata(&pdev->dev);
+ struct ahci_host_priv *hpriv;
+
+ BUG_ON(host == NULL);
+ BUG_ON(host->iomap[AHCI_PCI_BAR] == NULL);
+ hpriv = host->private_data;
+
+ tegra_ahci_controller_remove(pdev);
+
+ devm_iounmap(&pdev->dev, host->iomap[AHCI_PCI_BAR]);
+ devres_free(host);
+
+#ifdef CONFIG_PM
+ /* Free PG save/restore area */
+ devm_kfree(&pdev->dev, ((struct tegra_ahci_host_priv *)hpriv)->pg_save);
+
+#ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
+ pm_runtime_disable(&pdev->dev);
+#endif
+#endif
+
+ devm_kfree(&pdev->dev, hpriv);
+
+ return 0;
+}
+
+static int __devinit tegra_ahci_init_one(struct platform_device *pdev)
+{
+ struct ata_port_info pi = ahci_port_info;
+ const struct ata_port_info *ppi[] = { &pi, NULL };
+ struct device *dev = &pdev->dev;
+ struct ahci_host_priv *hpriv = NULL;
+ struct tegra_ahci_host_priv *tegra_hpriv;
+ struct ata_host *host = NULL;
+ int n_ports, i, rc;
+ struct resource *res, *irq_res;
+ void __iomem *mmio;
+ u32 save_size;
+ irq_handler_t irq_handler = ahci_interrupt;
+
+ VPRINTK("ENTER\n");
+
+ WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
+
+ ata_print_version_once(&pdev->dev, DRV_VERSION);
+
+ /* Simple resource validation */
+ if (pdev->num_resources != 3) {
+ dev_err(dev, "invalid number of resources\n");
+ dev_err(dev, "not enough SATA resources\n");
+ return -EINVAL;
+ }
+
+ /* acquire bar resources */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res == NULL)
+ return -EINVAL;
+
+ /* acquire IRQ resource */
+ irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (irq_res == NULL)
+ return -EINVAL;
+ if (irq_res->start <= 0)
+ return -EINVAL;
+
+ /* allocate sizeof tegra_ahci_host_priv, which contains extra fields */
+ hpriv = devm_kzalloc(dev, sizeof(struct tegra_ahci_host_priv),
+ GFP_KERNEL);
+ if (!hpriv) {
+ rc = -ENOMEM;
+ goto fail;
+ }
+ hpriv->flags |= (unsigned long)pi.private_data;
+ tegra_hpriv = (struct tegra_ahci_host_priv *)hpriv;
+ g_tegra_hpriv = tegra_hpriv;
+
+ /* Call tegra init routine */
+ rc = tegra_ahci_controller_init(tegra_hpriv);
+ if (rc != 0) {
+ dev_err(dev, "TEGRA SATA init failed\n");
+ goto fail;
+ }
+
+ /*
+ * We reserve a table of 6 BARs in tegra_hpriv to store BARs.
+ * Save the mapped AHCI_PCI_BAR address to the table.
+ */
+ mmio = devm_ioremap(dev, res->start, (res->end-res->start+1));
+ tegra_hpriv->bars_table[AHCI_PCI_BAR] = mmio;
+ hpriv->mmio = mmio;
+
+ /* save initial config */
+ tegra_ahci_save_initial_config(pdev, hpriv);
+ dev_dbg(dev, "past save init config\n");
+
+ /* prepare host */
+ if (hpriv->cap & HOST_CAP_NCQ) {
+ pi.flags |= ATA_FLAG_NCQ;
+ pi.flags |= ATA_FLAG_FPDMA_AA;
+ }
+
+ /*
+ * CAP.NP sometimes indicate the index of the last enabled
+ * port, at other times, that of the last possible port, so
+ * determining the maximum port number requires looking at
+ * both CAP.NP and port_map.
+ */
+ n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
+ host = ata_host_alloc_pinfo(dev, ppi, n_ports);
+ if (!host) {
+ rc = -ENOMEM;
+ goto fail;
+ }
+ host->private_data = hpriv;
+ tegra_hpriv->host = host;
+ tegra_hpriv->dev = dev;
+ host->iomap = tegra_hpriv->bars_table;
+
+ if (!(hpriv->cap & HOST_CAP_SSS))
+ host->flags |= ATA_HOST_PARALLEL_SCAN;
+ else
+ printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
+
+ for (i = 0; i < host->n_ports; i++) {
+ struct ata_port *ap = host->ports[i];
+
+ /* set initial link pm policy */
+ ap->target_lpm_policy = ATA_LPM_UNKNOWN;
+
+ /* disabled/not-implemented port */
+ if (!(hpriv->port_map & (1 << i)))
+ ap->ops = &ata_dummy_port_ops;
+ else
+ ap->target_lpm_policy = ATA_LPM_MIN_POWER;
+ }
+
+ rc = ahci_reset_controller(host);
+ if (rc) {
+ dev_err(dev, "Reset controller failed! (rc=%d)\n", rc);
+ goto fail;
+ }
+
+ ahci_init_controller(host);
+ ahci_print_info(host, "TEGRA-SATA");
+ dev_dbg(dev, "controller init okay\n");
+
+#ifdef CONFIG_PM
+ /* Setup PG save/restore area: */
+
+ /* calculate the size */
+ save_size = ARRAY_SIZE(pg_save_ipfs_registers) +
+ ARRAY_SIZE(pg_save_config_registers) +
+ ARRAY_SIZE(pg_save_bar5_registers) +
+ ARRAY_SIZE(pg_save_bar5_bkdr_registers);
+
+ /* and add save port_registers for all the ports */
+ save_size += TEGRA_AHCI_NUM_PORTS *
+ (ARRAY_SIZE(pg_save_config_port_registers) +
+ ARRAY_SIZE(pg_save_bar5_port_registers) +
+ ARRAY_SIZE(pg_save_bar5_bkdr_port_registers));
+
+ /*
+ * save_size is number of registers times number of bytes per
+ * register to get total save size.
+ */
+ save_size *= sizeof(u32);
+ tegra_hpriv->pg_save = devm_kzalloc(dev, save_size, GFP_KERNEL);
+ if (!tegra_hpriv->pg_save) {
+ rc = -ENOMEM;
+ goto fail;
+ }
+
+#ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
+ pm_runtime_set_active(dev);
+ pm_suspend_ignore_children(dev, true);
+ pm_runtime_enable(dev);
+
+ tegra_hpriv->pg_state = SATA_ON;
+
+ /* setup sata idle timer */
+ init_timer_deferrable(&tegra_hpriv->idle_timer);
+ tegra_hpriv->idle_timer.function = tegra_ahci_idle_timer;
+ tegra_hpriv->idle_timer.data = (unsigned long)host;
+
+ INIT_LIST_HEAD(&tegra_hpriv->qc_list);
+
+ /* use our own irq handler */
+ irq_handler = tegra_ahci_interrupt;
+#endif
+
+#endif
+
+ rc = ata_host_activate(host, irq_res->start, irq_handler, 0, &ahci_sht);
+ if (rc == 0)
+ return 0;
+
+ /* Free PG save/restore area */
+ devm_kfree(dev, tegra_hpriv->pg_save);
+
+#ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
+ pm_runtime_put(dev);
+ pm_runtime_enable(dev);
+#endif
+
+fail:
+ if (host) {
+ if (host->iomap[AHCI_PCI_BAR])
+ devm_iounmap(dev, host->iomap[AHCI_PCI_BAR]);
+ devres_free(host);
+ }
+ if (hpriv)
+ devm_kfree(dev, hpriv);
+
+ return rc;
+}
+
+static int __init ahci_init(void)
+{
+ return platform_driver_register(&tegra_platform_ahci_driver);
+}
+
+static void __exit ahci_exit(void)
+{
+ platform_driver_unregister(&tegra_platform_ahci_driver);
+}
+
+
+#ifdef CONFIG_DEBUG_FS
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+static void dbg_ahci_dump_regs(struct seq_file *s, u32 *ptr, u32 base, u32 regs)
+{
+#define REGS_PER_LINE 4
+
+ u32 i, j;
+ u32 lines = regs / REGS_PER_LINE;
+
+ for (i = 0; i < lines; i++) {
+ seq_printf(s, "0x%08x: ", base+(i*16));
+ for (j = 0; j < REGS_PER_LINE; ++j) {
+ seq_printf(s, "0x%08x ", readl(ptr));
+ ++ptr;
+ }
+ seq_printf(s, "\n");
+ }
+#undef REGS_PER_LINE
+}
+
+static int dbg_ahci_dump_show(struct seq_file *s, void *unused)
+{
+ u32 base;
+ u32 *ptr;
+ u32 i;
+
+ base = TEGRA_SATA_CONFIG_BASE;
+ ptr = (u32 *)IO_TO_VIRT(base);
+ seq_printf(s, "SATA CONFIG Registers:\n");
+ seq_printf(s, "----------------------\n");
+ dbg_ahci_dump_regs(s, ptr, base, 0x200);
+
+ base = TEGRA_SATA_BAR5_BASE;
+ ptr = (u32 *)IO_TO_VIRT(base);
+ seq_printf(s, "\nAHCI HBA Registers:\n");
+ seq_printf(s, "-------------------\n");
+ dbg_ahci_dump_regs(s, ptr, base, 64);
+
+ for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
+ base = TEGRA_SATA_BAR5_BASE + 0x100 + (0x80*i);
+ ptr = (u32 *)IO_TO_VIRT(base);
+ seq_printf(s, "\nPort %u Registers:\n", i);
+ seq_printf(s, "---------------\n");
+ dbg_ahci_dump_regs(s, ptr, base, 16);
+ }
+
+#ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
+ /* adjust tegra_ahci_idle_time to minimum if it is too small */
+ tegra_ahci_idle_time = max((u32)TEGRA_AHCI_MIN_IDLE_TIME,
+ tegra_ahci_idle_time);
+ seq_printf(s, "\nIdle Timeout = %u milli-seconds.\n",
+ tegra_ahci_idle_time);
+#endif
+
+ if (tegra_powergate_is_powered(TEGRA_POWERGATE_SATA))
+ seq_printf(s, "\n=== SATA controller is powered on ===\n\n");
+ else
+ seq_printf(s, "\n=== SATA controller is powered off ===\n\n");
+
+ return 0;
+}
+
+static int dbg_ahci_dump_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, dbg_ahci_dump_show, &inode->i_private);
+}
+
+static const struct file_operations debug_fops = {
+ .open = dbg_ahci_dump_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+static int __init tegra_ahci_dump_debuginit(void)
+{
+ (void) debugfs_create_file("tegra_ahci", S_IRUGO,
+ NULL, NULL, &debug_fops);
+#ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
+ (void) debugfs_create_u32("tegra_ahci_idle_ms", S_IRWXUGO,
+ NULL, &tegra_ahci_idle_time);
+#endif
+ return 0;
+}
+late_initcall(tegra_ahci_dump_debuginit);
+#endif
+
+MODULE_AUTHOR("NVIDIA");
+MODULE_DESCRIPTION("Tegra AHCI SATA low-level driver");
+MODULE_LICENSE("GPL v2");
+MODULE_VERSION(DRV_VERSION);
+
+module_init(ahci_init);
+module_exit(ahci_exit);
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/bus