diff options
| author | Kirill Artamonov <kartamonov@nvidia.com> | 2012-08-21 15:02:22 +0300 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-08-28 12:37:49 -0700 |
| commit | a4e44614a5bae9e714ac99c43a6085194edb3c21 (patch) | |
| tree | a85f1e2b65db93a2859c263f29f01021a71ba94f | |
| parent | 794066c1c027693fa4ae96b51fa9aa4f9a9ba002 (diff) | |
ARM: cache-l2x0: fix L2 maintenance for R3P1_50
Do flush and clear by set/way instead of by-way by enabling
errata 727915 for pl310 revision R3P1_50.
By-way maintenance doesn't work with enabled lp2_in_idle on
Tegra3 platform using R3P1_50 revision of pl310.
Debug register access causes hang when
CONFIG_TRUSTED_FOUNDATIONS is defined. Don't access those
regeisters if CONFIG_TRUSTED_FOUNDATIONS is defined.
bug 983964
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Change-Id: I76a3a9ef9dbcf86140ee26752202bf25542144e6
Reviewed-on: http://git-master/r/125153
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Tested-by: Antti Miettinen <amiettinen@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| -rw-r--r-- | arch/arm/include/asm/hardware/cache-l2x0.h | 1 | ||||
| -rw-r--r-- | arch/arm/mm/cache-l2x0.c | 7 |
2 files changed, 5 insertions, 3 deletions
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index fd04f24055fd..22ec488494da 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -79,6 +79,7 @@ #define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30 #define REV_PL310_R2P0 4 +#define REV_PL310_R3P1_50 7 #ifndef __ASSEMBLY__ extern void l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 0336d47c5dd4..972c7bd08a83 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -83,7 +83,8 @@ static inline void l2x0_inv_line(unsigned long addr) writel_relaxed(addr, base + L2X0_INV_LINE_PA); } -#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) +#if !defined(CONFIG_TRUSTED_FOUNDATIONS) && \ + (defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)) #define debug_writel(val) outer_cache.set_debug(val) @@ -161,7 +162,7 @@ static void l2x0_flush_all(void) unsigned long flags; #ifdef CONFIG_PL310_ERRATA_727915 - if (is_pl310_rev(REV_PL310_R2P0)) { + if (is_pl310_rev(REV_PL310_R2P0) || is_pl310_rev(REV_PL310_R3P1_50)) { l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_INV_LINE_IDX); return; } @@ -178,7 +179,7 @@ static void l2x0_clean_all(void) unsigned long flags; #ifdef CONFIG_PL310_ERRATA_727915 - if (is_pl310_rev(REV_PL310_R2P0)) { + if (is_pl310_rev(REV_PL310_R2P0) || is_pl310_rev(REV_PL310_R3P1_50)) { l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_LINE_IDX); return; } |