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authorPradeep Goudagunta <pgoudagunta@nvidia.com>2011-12-23 14:23:02 +0530
committerVarun Wadekar <vwadekar@nvidia.com>2012-01-04 11:45:06 +0530
commita724ce54039cdef7c34ba969b87f075d659e4475 (patch)
treec34c3d3c221ead9a7ef6ddf3e0d78a407bc56a90
parentf24c4131ebf2a59e7d6c81fb338a856b36432691 (diff)
ARM: tegra: pinmux: Support for setting pin io
-Added support for setting a pin io state to INPUT/OUTPUT. -Exported tegra_pinmux _get_pingroup/_set_io to make them available to loadable kernel modules. Bug 845065 Change-Id: I7d9500f590b804d1d222dfd7e42d1dbfc6686611 Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-on: http://git-master/r/71975 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux.h2
-rw-r--r--arch/arm/mach-tegra/pinmux.c21
2 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
index 5d50d798cb9b..f485d0bb0729 100644
--- a/arch/arm/mach-tegra/include/mach/pinmux.h
+++ b/arch/arm/mach-tegra/include/mach/pinmux.h
@@ -351,6 +351,8 @@ extern const int gpio_to_pingroup[];
int tegra_pinmux_get_func(enum tegra_pingroup pg);
int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
enum tegra_tristate tristate);
+int tegra_pinmux_set_io(enum tegra_pingroup pg,
+ enum tegra_pin_io input);
int tegra_pinmux_get_pingroup(int gpio_nr);
int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
enum tegra_pullupdown pupd);
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
index 5f4782b286a0..bf8627fb2c94 100644
--- a/arch/arm/mach-tegra/pinmux.c
+++ b/arch/arm/mach-tegra/pinmux.c
@@ -194,6 +194,7 @@ int tegra_pinmux_get_pingroup(int gpio_nr)
{
return gpio_to_pingroups_map[gpio_nr];
}
+EXPORT_SYMBOL_GPL(tegra_pinmux_get_pingroup);
static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
{
@@ -320,6 +321,26 @@ int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
return 0;
}
+int tegra_pinmux_set_io(enum tegra_pingroup pg,
+ enum tegra_pin_io input)
+{
+#if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
+ unsigned long io;
+
+ if (pg < 0 || pg >= TEGRA_MAX_PINGROUP)
+ return -ERANGE;
+
+ io = pg_readl(pingroups[pg].mux_reg);
+ if (input)
+ io |= 0x20;
+ else
+ io &= ~(1 << 5);
+ pg_writel(io, pingroups[pg].mux_reg);
+#endif
+ return 0;
+}
+EXPORT_SYMBOL_GPL(tegra_pinmux_set_io);
+
#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
static int tegra_pinmux_set_lock(enum tegra_pingroup pg,
enum tegra_pin_lock lock)