diff options
author | Jon Mayo <jmayo@nvidia.com> | 2011-07-07 18:59:38 -0700 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:47:42 -0800 |
commit | c0511f2e7eca7efbbfc9036fdd0d8765721578e1 (patch) | |
tree | 902a689ef38fbfec171d25581fd00afe72c297be | |
parent | 42138dfbc2b47f803928f82c1841395c68c80270 (diff) |
video: tegra: dc: remove emc clock worker
remove the support to delay changing emc clock.
Bug 850852
Original-Change-Id: Ibc125e7789ad96059c53c82eb51091afd7b880fc
Reviewed-on: http://git-master/r/40133
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rc136721574d4337ce8538abcf852d4d64857cdbf
-rw-r--r-- | arch/arm/mach-tegra/include/mach/dc.h | 2 | ||||
-rw-r--r-- | drivers/video/tegra/dc/dc.c | 68 | ||||
-rw-r--r-- | drivers/video/tegra/dc/dc_priv.h | 3 | ||||
-rw-r--r-- | drivers/video/tegra/dc/overlay.c | 6 | ||||
-rw-r--r-- | drivers/video/tegra/fb.c | 8 |
5 files changed, 3 insertions, 84 deletions
diff --git a/arch/arm/mach-tegra/include/mach/dc.h b/arch/arm/mach-tegra/include/mach/dc.h index 7c96dc89cc54..501b04b5c25d 100644 --- a/arch/arm/mach-tegra/include/mach/dc.h +++ b/arch/arm/mach-tegra/include/mach/dc.h @@ -437,8 +437,6 @@ u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc); u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc); void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, u32 val); -int tegra_dc_set_default_emc(struct tegra_dc *dc); - /* tegra_dc_update_windows and tegra_dc_sync_windows do not support windows * with differenct dcs in one call */ diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c index 10768ac60aac..564aeb9a2902 100644 --- a/drivers/video/tegra/dc/dc.c +++ b/drivers/video/tegra/dc/dc.c @@ -56,12 +56,6 @@ static int use_dynamic_emc = 1; module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR); -/* set default windows idle time as 2000ms for power saving purpose */ -static int windows_idle_detection_time = 2000; - -module_param_named(windows_idle_detection_time, windows_idle_detection_time, - int, S_IRUGO | S_IWUSR); - struct tegra_dc *tegra_dcs[TEGRA_MAX_DC]; DEFINE_MUTEX(tegra_dc_lock); @@ -717,25 +711,6 @@ static void tegra_dc_change_emc(struct tegra_dc *dc) } } -static void tegra_dc_reduce_emc_worker(struct work_struct *work) -{ - struct tegra_dc *dc; - - dc = container_of(to_delayed_work(work), struct tegra_dc, - reduce_emc_clk_work); - - mutex_lock(&dc->lock); - - if (!dc->enabled) { - mutex_unlock(&dc->lock); - return; - } - - tegra_dc_change_emc(dc); - - mutex_unlock(&dc->lock); -} - static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n) { unsigned long new_rate; @@ -751,45 +726,6 @@ static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n) dc->new_emc_clk_rate = new_rate; - /* - * If we don't need set EMC immediately after a frame POST, we schedule - * a work_queue to reduce EMC in the future. This work_queue task will - * not be executed if the another POST comes before the idle time - * expired. - */ - if (NEED_UPDATE_EMC_ON_EVERY_FRAME) - tegra_dc_change_emc(dc); - else - schedule_delayed_work(&dc->reduce_emc_clk_work, - msecs_to_jiffies(windows_idle_detection_time)); - - return 0; -} - -int tegra_dc_set_default_emc(struct tegra_dc *dc) -{ - /* - * POST happens whenever this function is called, we first delete any - * reduce_emc_clk_work, then we always set the DC EMC clock to default - * value. - */ - cancel_delayed_work_sync(&dc->reduce_emc_clk_work); - - if (NEED_UPDATE_EMC_ON_EVERY_FRAME) - return 0; - - mutex_lock(&dc->lock); - - if (!dc->enabled) { - mutex_unlock(&dc->lock); - return -EFAULT; - } - - dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc); - tegra_dc_change_emc(dc); - - mutex_unlock(&dc->lock); - return 0; } @@ -1600,6 +1536,9 @@ static void tegra_dc_vblank(struct work_struct *work) mutex_lock(&dc->lock); + /* update EMC clock if calculated bandwidth has changed */ + tegra_dc_change_emc(dc); + /* Update the SD brightness */ nvsd_updated = nvsd_update_brightness(dc); @@ -2168,7 +2107,6 @@ static int tegra_dc_probe(struct nvhost_device *ndev) dc->clk = clk; dc->emc_clk = emc_clk; - INIT_DELAYED_WORK(&dc->reduce_emc_clk_work, tegra_dc_reduce_emc_worker); dc->base_res = base_res; dc->base = base; diff --git a/drivers/video/tegra/dc/dc_priv.h b/drivers/video/tegra/dc/dc_priv.h index 1e9b17fe1769..dffb1bce44e3 100644 --- a/drivers/video/tegra/dc/dc_priv.h +++ b/drivers/video/tegra/dc/dc_priv.h @@ -31,8 +31,6 @@ #define WIN_USE_V_FILTER(win) ((win)->flags & TEGRA_WIN_FLAG_V_FILTER) #define WIN_USE_H_FILTER(win) ((win)->flags & TEGRA_WIN_FLAG_H_FILTER) -#define NEED_UPDATE_EMC_ON_EVERY_FRAME (windows_idle_detection_time == 0) - /* DDR: 8 bytes transfer per clock */ #define DDR_BW_TO_FREQ(bw) ((bw) / 8) @@ -121,7 +119,6 @@ struct tegra_dc { unsigned long underflow_mask; struct work_struct reset_work; - struct delayed_work reduce_emc_clk_work; struct completion vblank_complete; diff --git a/drivers/video/tegra/dc/overlay.c b/drivers/video/tegra/dc/overlay.c index fc4b02a3a92d..19e04a2df92c 100644 --- a/drivers/video/tegra/dc/overlay.c +++ b/drivers/video/tegra/dc/overlay.c @@ -380,12 +380,6 @@ static int tegra_overlay_flip(struct tegra_overlay_info *overlay, queue_work(overlay->flip_wq, &data->work); - /* - * Before the queued flip_wq get scheduled, we set the EMC clock to the - * default value in order to do FLIP without glitch. - */ - tegra_dc_set_default_emc(overlay->dc); - args->post_syncpt_val = syncpt_max; args->post_syncpt_id = tegra_dc_get_syncpt_id(overlay->dc); mutex_unlock(&tegra_flip_lock); diff --git a/drivers/video/tegra/fb.c b/drivers/video/tegra/fb.c index 0fdf6e0453bc..14e505b14739 100644 --- a/drivers/video/tegra/fb.c +++ b/drivers/video/tegra/fb.c @@ -288,7 +288,6 @@ static int tegra_fb_pan_display(struct fb_var_screeninfo *var, tegra_fb->win->phys_addr = addr; /* TODO: update virt_addr */ - tegra_dc_set_default_emc(tegra_fb->win->dc); tegra_dc_update_windows(&tegra_fb->win, 1); tegra_dc_sync_windows(&tegra_fb->win, 1); } @@ -556,12 +555,6 @@ static int tegra_fb_flip(struct tegra_fb_info *tegra_fb, queue_work(tegra_fb->flip_wq, &data->work); - /* - * Before the queued flip_wq get scheduled, we set the EMC clock to the - * default value in order to do FLIP without glitch. - */ - tegra_dc_set_default_emc(tegra_fb->win->dc); - args->post_syncpt_val = syncpt_max; args->post_syncpt_id = tegra_dc_get_syncpt_id(tegra_fb->win->dc); @@ -858,7 +851,6 @@ struct tegra_fb_info *tegra_fb_register(struct nvhost_device *ndev, dev_info(&ndev->dev, "probed\n"); if (fb_data->flags & TEGRA_FB_FLIP_ON_PROBE) { - tegra_dc_set_default_emc(tegra_fb->win->dc); tegra_dc_update_windows(&tegra_fb->win, 1); tegra_dc_sync_windows(&tegra_fb->win, 1); } |