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| author | Scott Williams <scwilliams@nvidia.com> | 2011-08-03 21:56:02 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:48:01 -0800 |
| commit | c6d7455f7146a1b6f2dd462c0d187edc017c43cd (patch) | |
| tree | 87e4c0e96f697d3bc3324a54d787c33eb5a0ecc1 | |
| parent | a2432fbaa7dc489770c0e489b56689744c473928 (diff) | |
ARM: tegra: Disable PL310 double line fill feature
Bug 854424
Original-Change-Id: I53a86b023920978cee0e6804985dd35d1f286de5
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/44930
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: R0c3899291fd85be56c6e93c02d072fd9cd6dd116
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index f864e99ee7c2..6a0e178f5540 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -198,9 +198,6 @@ void tegra_init_cache(void) writel(0x770, p + L2X0_TAG_LATENCY_CTRL); writel(0x770, p + L2X0_DATA_LATENCY_CTRL); #endif - - /* Enable PL310 double line fill feature. */ - writel(((1<<30) | 0), p + L2X0_PREFETCH_CTRL); #endif aux_ctrl = readl(p + L2X0_CACHE_TYPE); aux_ctrl = (aux_ctrl & 0x700) << (17-8); |