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authorMohit Kataria <mkataria@nvidia.com>2012-05-07 12:28:34 +0530
committerSimone Willett <swillett@nvidia.com>2012-05-10 17:18:12 -0700
commitd66d93e1a5e1e8296d0de445ad904f208f96e385 (patch)
tree9bedc794b27b572321c8a0eac5317fd101881801
parenta36c5139fa58482ea0a9ae3f3af9aa61b23b4f7c (diff)
Arm: tegra: p1852: Changed sclk to run at max.
Sclk frequecy changes depending on the clocks derived from sclk. Changed it to run at max POR frequecy. Bug 971061 Change-Id: I357e1acd8d049bf233ff79b942c911db123865f6 Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/100859 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/board-p1852.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-p1852.c b/arch/arm/mach-tegra/board-p1852.c
index 020671a7513b..fe7d9d5b13bb 100644
--- a/arch/arm/mach-tegra/board-p1852.c
+++ b/arch/arm/mach-tegra/board-p1852.c
@@ -141,6 +141,7 @@ static __initdata struct tegra_clk_init_table p1852_clk_init_table[] = {
{ "i2c4", "pll_p", 3200000, true},
{ "i2c5", "pll_p", 3200000, true},
{ "sdmmc2", "pll_p", 104000000, false},
+ {"wake.sclk", NULL, 334000000, true },
{ NULL, NULL, 0, 0},
};