diff options
| author | Jon Mayo <jmayo@nvidia.com> | 2011-05-13 11:55:16 -0700 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-04-24 07:55:16 -0700 |
| commit | fbfd93a5d14f4eda665f56b748da037b8194b1d3 (patch) | |
| tree | e6b889c37c65921e24ba4f35b312d32cafe5adf6 | |
| parent | 678749c92c46fc8f3d4041f1ca0324a2e6742c69 (diff) | |
ARM: tegra: dc: support YUV422 format
Change-Id: I8aa25b03fe6801882b65209cb1a6e125ef27ac2c
Signed-off-by: Michael I. Gold <gold@nvidia.com>
Reviewed-on: http://git-master/r/98319
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
| -rw-r--r-- | drivers/video/tegra/dc/dc.c | 29 |
1 files changed, 24 insertions, 5 deletions
diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c index 5f44b373fc11..228cbf1ae575 100644 --- a/drivers/video/tegra/dc/dc.c +++ b/drivers/video/tegra/dc/dc.c @@ -138,14 +138,32 @@ static inline int tegra_dc_fmt_bpp(int fmt) case TEGRA_WIN_FMT_YUV422RA: return 8; + /* YUYV packed into 32-bits */ case TEGRA_WIN_FMT_YCbCr422: case TEGRA_WIN_FMT_YUV422: - /* FIXME: need to know the bpp of these formats */ - return 0; + return 16; } return 0; } +static inline bool tegra_dc_is_yuv(int fmt) +{ + switch (fmt) { + case TEGRA_WIN_FMT_YUV420P: + case TEGRA_WIN_FMT_YCbCr420P: + case TEGRA_WIN_FMT_YCbCr422P: + case TEGRA_WIN_FMT_YUV422P: + case TEGRA_WIN_FMT_YCbCr422: + case TEGRA_WIN_FMT_YUV422: + case TEGRA_WIN_FMT_YCbCr422R: + case TEGRA_WIN_FMT_YUV422R: + case TEGRA_WIN_FMT_YCbCr422RA: + case TEGRA_WIN_FMT_YUV422RA: + return true; + } + return false; +} + static inline bool tegra_dc_is_yuv_planar(int fmt) { switch (fmt) { @@ -1161,6 +1179,7 @@ int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n) fixed20_12 h_offset, v_offset; bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0; bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0; + bool yuv = tegra_dc_is_yuv(win->fmt); bool yuvp = tegra_dc_is_yuv_planar(win->fmt); unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8; /* Bytes per pixel of bandwidth, used for dda_inc calculation */ @@ -1190,8 +1209,8 @@ int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n) continue; } - tegra_dc_writel(dc, win->fmt, DC_WIN_COLOR_DEPTH); - tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP); + tegra_dc_writel(dc, win->fmt & 0x1f, DC_WIN_COLOR_DEPTH); + tegra_dc_writel(dc, win->fmt >> 6, DC_WIN_BYTE_SWAP); tegra_dc_writel(dc, V_POSITION(win->out_y) | H_POSITION(win->out_x), @@ -1261,7 +1280,7 @@ int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n) DC_WIN_BUFFER_ADDR_MODE); val = WIN_ENABLE; - if (yuvp) + if (yuv) val |= CSC_ENABLE; else if (tegra_dc_fmt_bpp(win->fmt) < 24) val |= COLOR_EXPAND; |