diff options
| author | Dan Willemsen <dwillemsen@nvidia.com> | 2012-02-21 18:18:30 -0800 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-03-09 06:04:40 -0800 |
| commit | fc4fdec65cdd3d9ccf1abdbd153f3475cfe99cb8 (patch) | |
| tree | 0ff8e71037cfdcec0de8eaa66561d5f6df20d620 | |
| parent | 9be29bd1c5f03b5f6e428feee22d2a2c4fa1165c (diff) | |
cache-v7: Fix typo
Change 6dfe0d880a was backported from upstream, but differed from the
upstream patch with a typo - CONFIG_PREEMP vs CONFIG_PREEMPT
Change-Id: Ib8dea88cfc4d85bc6a3873acd4152bc628c03bb0
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/85059
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index ac0925bc4fa7..ea33896449b3 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -61,7 +61,7 @@ ENDPROC(v7_flush_icache_all) mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr isb @ isb to sych the new cssr&csidr mrc p15, 1, r1, c0, c0, 0 @ read the new csidr -#ifdef CONFIG_PREEMP +#ifdef CONFIG_PREEMPT restore_irqs_notrace r9 #endif and r2, r1, #7 @ extract the length of the cache lines |