video: tegra: dsi: Refactor code in tegra_dsi_hw_init()

Change-Id: I57f9ca25b4313be276c6b8fff677944f6b07e2cc
Reviewed-on: http://git-master/r/54824
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Tested-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

1 files changed, 31 insertions, 25 deletions

diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c
index c1a59c8e736b..6dcd386d8d98 100644
--- a/drivers/video/tegra/dc/dsi.c
+++ b/drivers/video/tegra/dc/dsi.c
@@ -1080,38 +1080,15 @@ static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
 	tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
 }
 
-static int tegra_dsi_init_hw(struct tegra_dc *dc,
-						struct tegra_dc_dsi_data *dsi)
+static void tegra_dsi_pad_caliberation(struct tegra_dc_dsi_data *dsi)
 {
 	u32 val;
-	u32 i;
-
-	val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
-	tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
-
-	tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
-	if (dsi->info.dsi_instance) {
-		/* TODO:Set the misc register*/
-	}
-
-	/* TODO: only need to change the timing for bta */
-	tegra_dsi_set_phy_timing(dsi);
-
-	if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
-		tegra_dsi_stop_dc_stream(dc, dsi);
 
-	/* Initializing DSI registers */
-	for (i = 0; i < ARRAY_SIZE(init_reg); i++)
-		tegra_dsi_writel(dsi, 0, init_reg[i]);
-
-	tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
-	/* Initialize DSI_PAD_CONTROL register. */
 	val =	DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
 		DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
 		DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
 		DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
 		DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
-
 	if (!dsi->ulpm) {
 		val |=	DSI_PAD_CONTROL_PAD_PDIO(0) |
 			DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
@@ -1134,6 +1111,35 @@ static int tegra_dsi_init_hw(struct tegra_dc *dc,
 
 	val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
 	tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
+}
+
+static int tegra_dsi_init_hw(struct tegra_dc *dc,
+						struct tegra_dc_dsi_data *dsi)
+{
+	u32 val;
+	u32 i;
+
+	val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
+	tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
+
+	tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
+	if (dsi->info.dsi_instance) {
+		/* TODO:Set the misc register*/
+	}
+
+	/* TODO: only need to change the timing for bta */
+	tegra_dsi_set_phy_timing(dsi);
+
+	if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
+		tegra_dsi_stop_dc_stream(dc, dsi);
+
+	/* Initializing DSI registers */
+	for (i = 0; i < ARRAY_SIZE(init_reg); i++)
+		tegra_dsi_writel(dsi, 0, init_reg[i]);
+
+	tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
+
+	tegra_dsi_pad_caliberation(dsi);
 
 	val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE);
 	tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
@@ -1542,7 +1548,7 @@ int tegra_dsi_read_data(struct tegra_dc *dc,
 
 	if ((dsi->status.init != DSI_MODULE_INIT) ||
 		(dsi->status.lphs == DSI_LPHS_NOT_INIT) ||
-		(dsi->status.driven == DSI_DRIVEN_MODE_NOT_INIT)||
+		(dsi->status.driven == DSI_DRIVEN_MODE_NOT_INIT) ||
 		(dsi->status.lp_op == DSI_LP_OP_NOT_INIT)) {
 		err = -EPERM;
 		goto fail;