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authorAlex Frid <afrid@nvidia.com>2011-08-24 16:50:57 -0700
committerRohan Somvanshi <rsomvanshi@nvidia.com>2011-08-29 08:27:55 -0700
commit0fead6561bf945f5669915b04050850573547cf6 (patch)
tree620ed49ce14dc8574e6e884150d49b6cadb8730b
parent407a3631a15f22735a9301ebf9dd85920814dce8 (diff)
ARM: tegra: power: Fix LP2/LP3 states accounting
Made sure LP3 state is reported as last entered state to cpuidle governor in case when LP3 is entered as a fall back from LP2 path; skipped LP2 stats in this case as well. Change-Id: Ib2d0dd1b7c673b0b8c346a07372505d2345fe1ca Reviewed-on: http://git-master/r/49109 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/cpuidle.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index 64eff725300d..252bc123f808 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -86,6 +86,9 @@ void tegra_flow_wfi(struct cpuidle_device *dev)
dsb();
start_critical_timings();
+
+ /* can fall back here from LP2 path - tell cpuidle governor */
+ dev->last_state = &dev->states[0];
}
static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
@@ -143,6 +146,10 @@ static int tegra_idle_enter_lp2(struct cpuidle_device *dev,
hrtimer_peek_ahead_timers();
smp_rmb();
+
+ if (state != dev->last_state)
+ return (int)us; /* skip lp2 stats if we've been in lp3 */
+
state->exit_latency = tegra_lp2_exit_latency;
state->target_residency = tegra_lp2_exit_latency +
tegra_lp2_power_off_time;