diff options
author | kdivvela <kdivvela@nvidia.com> | 2011-08-19 15:11:36 +0530 |
---|---|---|
committer | Varun Colbert <vcolbert@nvidia.com> | 2011-08-26 15:17:13 -0700 |
commit | b612eeee2ec4df9e00c8c5576585083a5254a389 (patch) | |
tree | 7fc6a098c910fede540c9d38f684b6a28833f0d0 | |
parent | ed69630837778717dca8b9863d7501de06c7b7cd (diff) |
media: video: tegra: ov5650: QVGA 120fps sensor support
Add new sensor mode for OV5650 sensor
with QVGA and 120fps.
Bug 860670
Change-Id: I2f4dbdd5ebf771359f73d89787d88c50ec333e0f
Reviewed-on: http://git-master/r/48065
Tested-by: Krupal Divvela <kdivvela@nvidia.com>
Reviewed-by: Prayas Mohanty <pmohanty@nvidia.com>
Reviewed-by: Ravikumar Boddeti <rboddeti@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
-rw-r--r-- | drivers/media/video/tegra/ov5650.c | 152 |
1 files changed, 150 insertions, 2 deletions
diff --git a/drivers/media/video/tegra/ov5650.c b/drivers/media/video/tegra/ov5650.c index 9ebd4c1b1a8a..b667d13ea4b3 100644 --- a/drivers/media/video/tegra/ov5650.c +++ b/drivers/media/video/tegra/ov5650.c @@ -565,6 +565,150 @@ static struct ov5650_reg mode_1264x704[] = { {OV5650_TABLE_END, 0x0000} }; +static struct ov5650_reg mode_320x240[] = { + {0x3103, 0x93}, + {0x3b07, 0x0c}, + {0x3017, 0xff}, + {0x3018, 0xfc}, + {0x3706, 0x41}, + {0x3613, 0xc4}, + {0x370d, 0x42}, + {0x3703, 0x9a}, + {0x3630, 0x22}, + {0x3605, 0x04}, + {0x3606, 0x3f}, + {0x3712, 0x13}, + {0x370e, 0x00}, + {0x370b, 0x40}, + {0x3600, 0x54}, + {0x3601, 0x05}, + {0x3713, 0x22}, + {0x3714, 0x27}, + {0x3631, 0x22}, + {0x3612, 0x1a}, + {0x3604, 0x40}, + {0x3705, 0xdc}, + {0x370a, 0x83}, + {0x370c, 0xc8}, + {0x3710, 0x28}, + {0x3702, 0x3a}, + {0x3704, 0x18}, + {0x3a18, 0x00}, + {0x3a19, 0xf8}, + {0x3a00, 0x38}, + {0x3800, 0x02}, + {0x3801, 0x54}, + {0x3803, 0x0c}, + {0x380c, 0x0c}, + {0x380d, 0xb4}, + {0x380e, 0x07}, + {0x380f, 0xb0}, + {0x3830, 0x50}, + {0x3a08, 0x12}, + {0x3a09, 0x70}, + {0x3a0a, 0x0f}, + {0x3a0b, 0x60}, + {0x3a0d, 0x06}, + {0x3a0e, 0x06}, + {0x3a13, 0x54}, + {0x3815, 0x82}, + {0x5059, 0x80}, + {0x3615, 0x52}, + {0x505a, 0x0a}, + {0x505b, 0x2e}, + {0x3713, 0x92}, + {0x3714, 0x17}, + {0x3803, 0x0a}, + {0x3804, 0x05}, + {0x3805, 0x00}, + {0x3806, 0x01}, + {0x3807, 0x00}, + {0x3808, 0x01}, + {0x3809, 0x40}, + {0x380a, 0x01}, + {0x380b, 0x00}, + {0x380c, 0x0a}, /* total horizontal size higher 5 bits [4:0] pg 109, + line length */ + {0x380d, 0x04}, /* total horizontal size lower 8 bits [7:0] pg 109, + line length */ + {0x380e, 0x01}, /* total vertical size higher 5 bits [4:0] pg 109, + frame length */ + {0x380f, 0x38}, /* total vertical size lower 8 bits [7:0] pg 109, + frame length */ + {0x3815, 0x81}, + {0x3824, 0x23}, + {0x3825, 0x20}, + {0x3826, 0x00}, + {0x3827, 0x08}, + {0x370d, 0xc2}, + {0x3a08, 0x17}, + {0x3a09, 0x64}, + {0x3a0a, 0x13}, + {0x3a0b, 0x80}, + {0x3a00, 0x58}, + {0x3a1a, 0x06}, + {0x3503, 0x00}, + {0x3623, 0x01}, + {0x3633, 0x24}, + {0x3c01, 0x34}, + {0x3c04, 0x28}, + {0x3c05, 0x98}, + {0x3c07, 0x07}, + {0x3c09, 0xc2}, + {0x4000, 0x05}, + {0x401d, 0x28}, + {0x4001, 0x02}, + {0x401c, 0x42}, + {0x5046, 0x09}, + {0x3810, 0x40}, + {0x3836, 0x41}, + {0x505f, 0x04}, + {0x5000, 0x06}, + {0x5001, 0x00}, + {0x5002, 0x02}, + {0x503d, 0x00}, + {0x5901, 0x08}, + {0x585a, 0x01}, + {0x585b, 0x2c}, + {0x585c, 0x01}, + {0x585d, 0x93}, + {0x585e, 0x01}, + {0x585f, 0x90}, + {0x5860, 0x01}, + {0x5861, 0x0d}, + {0x5180, 0xc0}, + {0x5184, 0x00}, + {0x470a, 0x00}, + {0x470b, 0x00}, + {0x470c, 0x00}, + {0x300f, 0x8e}, + {0x3603, 0xa7}, + {0x3632, 0x55}, + {0x3620, 0x56}, + {0x3621, 0xaf}, + {0x3818, 0xc3}, + {0x3631, 0x36}, + {0x3632, 0x5f}, + {0x3711, 0x24}, + {0x401f, 0x03}, + + {0x3011, 0x14}, + {0x3007, 0x3B}, + {0x300f, 0x8f}, //0x8f:2-lane, 0x8b:1-lane + {0x4801, 0x0f}, + {0x3003, 0x03}, + {0x300e, 0x0c}, + {0x3010, 0x15}, //120/60/30fps:0x15/0x35/0x75 + {0x4803, 0x50}, + {0x4800, 0x24}, //bit[5]=0 as CSI continuous clock + {0x4837, 0x40}, //120/60/30fps:0x10/0x20/0x40 + {0x3815, 0x82}, + {0x3003, 0x01}, + {0x3008, 0x02}, + + {OV5650_TABLE_END, 0x0000} +}; + static struct ov5650_reg mode_end[] = { {0x3212, 0x00}, /* SRM_GROUP_ACCESS (group hold begin) */ {0x3003, 0x01}, /* reset DVP pg 97 */ @@ -582,15 +726,17 @@ enum { OV5650_MODE_2080x1164, OV5650_MODE_1920x1080, OV5650_MODE_1264x704, + OV5650_MODE_320x240, OV5650_MODE_INVALID }; static struct ov5650_reg *mode_table[] = { [OV5650_MODE_2592x1944] = mode_2592x1944, - [OV5650_MODE_1296x972] = mode_1296x972, + [OV5650_MODE_1296x972] = mode_1296x972, [OV5650_MODE_2080x1164] = mode_2080x1164, [OV5650_MODE_1920x1080] = mode_1920x1080, - [OV5650_MODE_1264x704] = mode_1264x704 + [OV5650_MODE_1264x704] = mode_1264x704, + [OV5650_MODE_320x240] = mode_320x240 }; /* 2 regs to program frame length */ @@ -790,6 +936,8 @@ static int ov5650_set_mode(struct ov5650_info *info, struct ov5650_mode *mode) sensor_mode = OV5650_MODE_1920x1080; else if (mode->xres == 1264 && mode->yres == 704) sensor_mode = OV5650_MODE_1264x704; + else if (mode->xres == 320 && mode->yres == 240) + sensor_mode = OV5650_MODE_320x240; else { pr_err("%s: invalid resolution supplied to set mode %d %d\n", __func__, mode->xres, mode->yres); |