diff options
| author | Bo Kim <bok@nvidia.com> | 2011-08-17 15:52:12 +0900 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-08-29 18:06:12 -0700 |
| commit | c642051d28913644c400731de1831d894fdb1211 (patch) | |
| tree | debaa68a0261115ed0a13bee5ddb310c4c6c4997 | |
| parent | 8a6c82747b76aec43901e773dc7b8b35e81b7d10 (diff) | |
ARM: tegra: clock: tegra2_pll_clk_set_rate() process p field is greater then 2.
This change makes tegra2_pll_clk_set_rate() will process for p field is greater
then 2. It helps to increase VCO.
Bug 852217
Bug 842032
Reviewed-on: http://git-master/r/47492
(cherry picked from commit e1fefd8a7fb9751ddfad95e469666f3c876123a8)
Change-Id: Id49b33cd8e568c6e5b619988a148242a85867eca
Reviewed-on: http://git-master/r/49585
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bo Kim <bok@nvidia.com>
Tested-by: Bo Kim <bok@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 337ebb022d4c..2b1209014b32 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -728,13 +728,25 @@ static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate) PLL_BASE_DIVM_MASK); val |= (sel->m << PLL_BASE_DIVM_SHIFT) | (sel->n << PLL_BASE_DIVN_SHIFT); - BUG_ON(sel->p < 1 || sel->p > 2); + BUG_ON(sel->p < 1 || sel->p > 128); if (c->flags & PLLU) { if (sel->p == 1) val |= PLLU_BASE_POST_DIV; } else { if (sel->p == 2) val |= 1 << PLL_BASE_DIVP_SHIFT; + else if (sel->p == 4) + val |= 2 << PLL_BASE_DIVP_SHIFT; + else if (sel->p == 8) + val |= 3 << PLL_BASE_DIVP_SHIFT; + else if (sel->p == 16) + val |= 4 << PLL_BASE_DIVP_SHIFT; + else if (sel->p == 32) + val |= 5 << PLL_BASE_DIVP_SHIFT; + else if (sel->p == 64) + val |= 6 << PLL_BASE_DIVP_SHIFT; + else if (sel->p == 128) + val |= 7 << PLL_BASE_DIVP_SHIFT; } clk_writel(val, c->reg + PLL_BASE); |