diff options
author | Catalin Marinas <catalin.marinas@arm.com> | 2009-07-20 16:25:37 +0100 |
---|---|---|
committer | Catalin Marinas <catalin.marinas@arm.com> | 2009-09-08 13:19:44 +0100 |
commit | 78b124262dda66b1122f70224d5906fd4f14bdbf (patch) | |
tree | 650cea3b4214ac9a63a196c4d2680c33015f8542 | |
parent | 0d7971281206bb437f884652ecbc401701e31919 (diff) |
Cortex-M3: Add NVIC support
This patch implements the NVIC (interrupt controller) support for
Cortex-M3.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
-rw-r--r-- | arch/arm/common/Kconfig | 3 | ||||
-rw-r--r-- | arch/arm/common/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/common/nvic.c | 99 | ||||
-rw-r--r-- | include/asm-arm/hardware/nvic.h | 34 |
4 files changed, 137 insertions, 0 deletions
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig index 86b5e6982660..b701d4d8de2a 100644 --- a/arch/arm/common/Kconfig +++ b/arch/arm/common/Kconfig @@ -4,6 +4,9 @@ config ARM_GIC config ARM_VIC bool +config ARM_NVIC + bool + config ICST525 bool diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index e6bdb9657dee..aaeff2199691 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_ARM_GIC) += gic.o obj-$(CONFIG_ARM_VIC) += vic.o +obj-$(CONFIG_ARM_NVIC) += nvic.o obj-$(CONFIG_ICST525) += icst525.o obj-$(CONFIG_ICST307) += icst307.o obj-$(CONFIG_SA1111) += sa1111.o diff --git a/arch/arm/common/nvic.c b/arch/arm/common/nvic.c new file mode 100644 index 000000000000..ea40cc8c7927 --- /dev/null +++ b/arch/arm/common/nvic.c @@ -0,0 +1,99 @@ +/* + * linux/arch/arm/common/nvic.c + * + * Copyright (C) 2008 ARM Limited, All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Support for the Nested Vectored Interrupt Controller found on the + * ARMv7-M CPUs (Cortex-M3) + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/smp.h> + +#include <asm/irq.h> +#include <asm/io.h> +#include <asm/mach/irq.h> +#include <asm/hardware/nvic.h> + +static DEFINE_SPINLOCK(irq_controller_lock); + +/* + * Routines to acknowledge, disable and enable interrupts + * + * Linux assumes that when we're done with an interrupt we need to + * unmask it, in the same way we need to unmask an interrupt when + * we first enable it. + * + * The NVIC has a separate notion of "end of interrupt" to re-enable + * an interrupt after handling, in order to support hardware + * prioritisation. + * + * We can make the NVIC behave in the way that Linux expects by making + * our "acknowledge" routine disable the interrupt, then mark it as + * complete. + */ +static void nvic_ack_irq(unsigned int irq) +{ + u32 mask = 1 << (irq % 32); + + spin_lock(&irq_controller_lock); + writel(mask, NVIC_CLEAR_ENABLE + irq / 32 * 4); + spin_unlock(&irq_controller_lock); +} + +static void nvic_mask_irq(unsigned int irq) +{ + u32 mask = 1 << (irq % 32); + + spin_lock(&irq_controller_lock); + writel(mask, NVIC_CLEAR_ENABLE + irq / 32 * 4); + spin_unlock(&irq_controller_lock); +} + +static void nvic_unmask_irq(unsigned int irq) +{ + u32 mask = 1 << (irq % 32); + + spin_lock(&irq_controller_lock); + writel(mask, NVIC_SET_ENABLE + irq / 32 * 4); + spin_unlock(&irq_controller_lock); +} + +static struct irq_chip nvic_chip = { + .name = "NVIC", + .ack = nvic_ack_irq, + .mask = nvic_mask_irq, + .unmask = nvic_unmask_irq, +}; + +void __init nvic_init(void) +{ + unsigned int max_irq, i; + + max_irq = ((readl(NVIC_INTR_CTRL) & 0x1f) + 1) * 32; + + /* + * Disable all interrupts + */ + for (i = 0; i < max_irq / 32; i++) + writel(~0, NVIC_CLEAR_ENABLE + i * 4); + + /* + * Set priority on all interrupts. + */ + for (i = 0; i < max_irq; i += 4) + writel(0, NVIC_PRIORITY + i); + + /* + * Setup the Linux IRQ subsystem. + */ + for (i = 0; i < NR_IRQS; i++) { + set_irq_chip(i, &nvic_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + } +} diff --git a/include/asm-arm/hardware/nvic.h b/include/asm-arm/hardware/nvic.h new file mode 100644 index 000000000000..b7f80266bafd --- /dev/null +++ b/include/asm-arm/hardware/nvic.h @@ -0,0 +1,34 @@ +/* + * linux/include/asm-arm/hardware/nvic.h + * + * Copyright (C) 2008 ARM Limited, All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_ARM_HARDWARE_NVIC_H +#define __ASM_ARM_HARDWARE_NVIC_H + +#include <linux/compiler.h> + +#define V7M_SCS 0xe000e000 +#define NVIC_INTR_CTRL (V7M_SCS + 0x004) +#define NVIC_SYSTICK_CTRL (V7M_SCS + 0x010) +#define NVIC_SYSTICK_RELOAD (V7M_SCS + 0x014) +#define NVIC_SYSTICK_CURRENT (V7M_SCS + 0x018) +#define NVIC_SYSTICK_CALIBRATION (V7M_SCS + 0x01c) +#define NVIC_SET_ENABLE (V7M_SCS + 0x100) +#define NVIC_CLEAR_ENABLE (V7M_SCS + 0x180) +#define NVIC_SET_PENDING (V7M_SCS + 0x200) +#define NVIC_CLEAR_PENDING (V7M_SCS + 0x280) +#define NVIC_ACTIVE_BIT (V7M_SCS + 0x300) +#define NVIC_PRIORITY (V7M_SCS + 0x400) +#define NVIC_INTR_CTRL_STATE (V7M_SCS + 0xd04) +#define NVIC_SOFTWARE_INTR (V7M_SCS + 0xf00) + +#ifndef __ASSEMBLY__ +void nvic_init(void); +#endif + +#endif |