diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-05-11 18:50:25 -0700 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-05-13 18:42:33 -0700 |
| commit | 1b8580f71a09d5004f2e1ca2eca17fd373b5ba4e (patch) | |
| tree | db88d91eda7d8455009dd0eecef91fd506948cbc | |
| parent | f1e0b9de06c999a8129aa2d129402d0d19be6fa3 (diff) | |
ARM: tegra: power: Limit Tegra3 CPU nominal voltage
Limit Tegra3 CPU nominal voltage in case when maximum rate specified
in the clock tree is below maximum rate in CPU dvfs table.
Change-Id: Ie7b47a1f482f3c33da19e530b05663683bd807a1
Reviewed-on: http://git-master/r/31307
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_dvfs.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c index 4423e4a0f2ea..e89b3e01a9c0 100644 --- a/arch/arm/mach-tegra/tegra3_dvfs.c +++ b/arch/arm/mach-tegra/tegra3_dvfs.c @@ -275,6 +275,7 @@ static int __init get_cpu_nominal_mv_index( { int i, j, mv; struct dvfs *d; + struct clk *c; /* * Start with nominal level for the chips with this speedo_id. Then, @@ -287,18 +288,28 @@ static int __init get_cpu_nominal_mv_index( mv = min(mv, tegra3_dvfs_rail_vdd_core.nominal_millivolts); /* - * Find matching cpu dvfs entry, and index to the minimum voltage for - * maximum frequency specified in the entry, not exceeding nominal - * limit. This index point to the final nominal voltage. + * Find matching cpu dvfs entry, and use it to determine index to the + * final nominal voltage, that satisfies the following requirements: + * - allows CPU to run at minimum of the maximum rates specified in + * the dvfs entry and clock tree + * - does not violate cpu_to_core dependency as determined above */ for (i = 0, j = 0; j < ARRAY_SIZE(cpu_dvfs_table); j++) { d = &cpu_dvfs_table[j]; if (match_dvfs_one(d, speedo_id, process_id)) { + c = tegra_get_clock_by_name(d->clk_name); + BUG_ON(!c); + for (; i < MAX_DVFS_FREQS; i++) { if ((d->freqs[i] == 0) || (cpu_millivolts[i] == 0) || (mv < cpu_millivolts[i])) break; + + if (c->max_rate <= d->freqs[i]*d->freqs_mult) { + i++; + break; + } } break; } |