diff options
| author | Stephen Boyd <(address hidden)> | 2012-02-10 16:49:11 +0530 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-02-15 12:44:49 -0800 |
| commit | 6dfe0d880acf300419da399d4973fe38cdd42318 (patch) | |
| tree | 2a27b7e199700c64566fbac507eb0edbf2df8bc7 | |
| parent | a138e0615700e7d31a6595aa01f5b3fe1a620d7c (diff) | |
cache-v7: Disable preemption when reading CCSIDR
armv7's flush_cache_all() flushes caches via set/way. To
determine the cache attributes (line size, number of sets,
etc.) the assembly first writes the CSSELR register to select a
cache level and then reads the CCSIDR register. The CSSELR register
is banked per-cpu and is used to determine which cache level CCSIDR
reads. If the task is migrated between when the CSSELR is written and
the CCSIDR is read the CCSIDR value may be for an unexpected cache
level (for example L1 instead of L2) and incorrect cache flushing
could occur.
Disable interrupts across the write and read so that the correct
cache attributes are read and used for the cache flushing
routine. We disable interrupts instead of disabling preemption
because the critical section is only 3 instructions and we want
to call v7_dcache_flush_all from __v7_setup which doesn't have a
full kernel stack with a struct thread_info.
This fixes a problem we see in scm_call() when flush_cache_all()
is called from preemptible context and sometimes the L2 cache is
not properly flushed out.
Signed-off-by: Stephen Boyd <(address hidden)>
Acked-by: Catalin Marinas <(address hidden)>
Reviewed-by: Nicolas Pitre <(address hidden)>
Cc: stable@vger.kernel.org
Change-Id: I34a54ac396929d9e4f9abb43fbeaeb71d5514b63
Reviewed-on: http://git-master/r/83094
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 963325eb083e..66bf91bd75a3 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -55,9 +55,15 @@ ENDPROC(v7_flush_icache_all) and r1, r1, #7 @ mask of the bits for current cache only cmp r1, #2 @ see what cache we have at this level blt 1004f @ skip if no cache, or just i-cache +#ifdef CONFIG_PREEMPT + save_and_disable_irqs r9 @ make cssr&csidr read atomic +#endif mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr isb @ isb to sych the new cssr&csidr mrc p15, 1, r1, c0, c0, 0 @ read the new csidr +#ifdef CONFIG_PREEMP + restore_irqs_notrace r9 +#endif and r2, r1, #7 @ extract the length of the cache lines add r2, r2, #4 @ add 4 (line length offset) ldr r4, =0x3ff |