diff options
| author | Hiroshi Doyu <hdoyu@nvidia.com> | 2013-05-03 06:18:02 +0300 |
|---|---|---|
| committer | Harshada Kale <hkale@nvidia.com> | 2013-06-10 03:51:22 -0700 |
| commit | ab30491df5386eb2873b53bb8bcfae83e91b2cb6 (patch) | |
| tree | 3ebd2caf040d513f9ea421d6eeabdb32dc9f4cb6 | |
| parent | 2fa899cea85450ffda872115c5c931089bd1d14f (diff) | |
iommu/tegra: smmu: Add Tegra errata 1053704 for some of Tegra SoC
Add workaround of TEGRA_ERRATA_1053704 for some of Tegra SoC
bug 1286500
Change-Id: I7d1a75b198051bc49eb7e14e4e7892eab9818f29
(cherry picked from commit fc688d6f91ae4250cb16274bc8b41875ead06b4e)
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/234132
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/iommu/Kconfig | 14 |
2 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index fa308f922b25..e5c6fbec5ec2 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -92,6 +92,7 @@ config ARCH_TEGRA_3x_SOC select TEGRA_LATENCY_ALLOWANCE if !TEGRA_FPGA_PLATFORM select TEGRA_LATENCY_ALLOWANCE_SCALING if !TEGRA_FPGA_PLATFORM select SOC_BUS + select TEGRA_ERRATA_1053704 help Support for NVIDIA Tegra T30 processor family, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller @@ -126,6 +127,7 @@ config ARCH_TEGRA_11x_SOC select TEGRA_ISOMGR_SYSFS select TEGRA_ISOMGR_DEBUG select TEGRA_ERRATA_1157520 + select TEGRA_ERRATA_1053704 select TEGRA_CORE_EDP_LIMITS select TEGRA_VDD_CORE_OVERRIDE if TEGRA_EMC_SCALING_ENABLE select TEGRA_THERMAL_THROTTLE_EXACT_FREQ diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index feec0e680d2a..35c1fd7d88a0 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -177,4 +177,18 @@ config TEGRA_IOMMU_SMMU_LINEAR IOMMU'able bus. Otherwise DMA API should be used correctly in device drivers. +config TEGRA_ERRATA_1053704 + bool "Tegra errata: SMMU Hit-Under-Miss FIFO Out-of-Order" + depends on TEGRA_IOMMU_SMMU + depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_11x_SOC + help + SMMU TLB entry invalidate, while hit-under-miss(HUM) FIFO + has pending transaction(s) based on the TLB entry, can cause + violation of transactions ordering requirement at SMMU, if + the subsequent transaction to the same IOVA address gets PTE + into a different TLB entry. If this happens, The new + transaction(s) can bypass pending transaction(s) and can + lead to memory corruption. The workaround is not to flush + TLB entry, which has pending transactions in HUM FIFO. + endif # IOMMU_SUPPORT |