misc: tegra-profiler: add Cortex-A57 events

Tegra Profiler: add ARMv8 Cortex-A57 specific pmu events.

Bug 1582354
Bug 1598009

Change-Id: I72b1e1ccea3d455d91492cb6ad8538f2405c3937
Signed-off-by: Igor Nabirushkin <inabirushkin@nvidia.com>
Reviewed-on: http://git-master/r/654818
(cherry picked from commit 0d4bbf2c837461aa1571d242be80907fbad14482)
Reviewed-on: http://git-master/r/672035
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

3 files changed, 88 insertions, 9 deletions

diff --git a/drivers/misc/tegra-profiler/armv8_events.h b/drivers/misc/tegra-profiler/armv8_events.h
index 1d675ddddabf..656089a51038 100644
--- a/drivers/misc/tegra-profiler/armv8_events.h
+++ b/drivers/misc/tegra-profiler/armv8_events.h
@@ -1,7 +1,7 @@
 /*
  * drivers/misc/tegra-profiler/armv8_events.h
  *
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -22,13 +22,14 @@
 #define QUADD_AA64_CPU_IMP_NVIDIA	'N'
 
 #define QUADD_AA64_CPU_IDCODE_CORTEX_A57	0x01
-
+#define QUADD_AA64_CPU_IDCODE_CORTEX_A53	0x03
 
 enum {
 	QUADD_AA64_CPU_TYPE_UNKNOWN = 1,
+	QUADD_AA64_CPU_TYPE_UNKNOWN_IMP,
 	QUADD_AA64_CPU_TYPE_ARM,
+	QUADD_AA64_CPU_TYPE_CORTEX_A53,
 	QUADD_AA64_CPU_TYPE_CORTEX_A57,
-	QUADD_AA64_CPU_TYPE_UNKNOWN_IMP,
 	QUADD_AA64_CPU_TYPE_DENVER,
 };
 
@@ -128,6 +129,16 @@ enum {
 	QUADD_ARMV8_HW_EVENT_BUS_CYCLES				= 0x1D,
 };
 
+/*
+ * ARMv8 Cortex-A57 specific event types.
+ */
+enum {
+	QUADD_ARMV8_A57_HW_EVENT_L1D_CACHE_REFILL_LD	= 0x42,
+	QUADD_ARMV8_A57_HW_EVENT_L1D_CACHE_REFILL_ST	= 0x43,
+	QUADD_ARMV8_A57_HW_EVENT_L2D_CACHE_REFILL_LD	= 0x52,
+	QUADD_ARMV8_A57_HW_EVENT_L2D_CACHE_REFILL_ST	= 0x53,
+};
+
 #define QUADD_ARMV8_UNSUPPORTED_EVENT	0xff00
 #define QUADD_ARMV8_CPU_CYCLE_EVENT	0xffff
 
diff --git a/drivers/misc/tegra-profiler/armv8_pmu.c b/drivers/misc/tegra-profiler/armv8_pmu.c
index 7a4ffc17079a..940c8c3acfcd 100644
--- a/drivers/misc/tegra-profiler/armv8_pmu.c
+++ b/drivers/misc/tegra-profiler/armv8_pmu.c
@@ -1,7 +1,7 @@
 /*
  * drivers/misc/tegra-profiler/armv8_pmu.c
  *
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -50,7 +50,60 @@ static DEFINE_PER_CPU(struct quadd_pmu_info, cpu_pmu_info);
 
 static struct quadd_pmu_ctx pmu_ctx;
 
-static unsigned quadd_armv8_pmuv3_events_map[QUADD_EVENT_TYPE_MAX] = {
+static unsigned
+quadd_armv8_pmuv3_arm_events_map[QUADD_EVENT_TYPE_MAX] = {
+	[QUADD_EVENT_TYPE_INSTRUCTIONS] =
+		QUADD_ARMV8_HW_EVENT_INSTR_EXECUTED,
+	[QUADD_EVENT_TYPE_BRANCH_INSTRUCTIONS] =
+		QUADD_ARMV8_UNSUPPORTED_EVENT,
+	[QUADD_EVENT_TYPE_BRANCH_MISSES] =
+		QUADD_ARMV8_HW_EVENT_PC_BRANCH_MIS_PRED,
+	[QUADD_EVENT_TYPE_BUS_CYCLES] =
+		QUADD_ARMV8_UNSUPPORTED_EVENT,
+
+	[QUADD_EVENT_TYPE_L1_DCACHE_READ_MISSES] =
+		QUADD_ARMV8_HW_EVENT_L1_DCACHE_REFILL,
+	[QUADD_EVENT_TYPE_L1_DCACHE_WRITE_MISSES] =
+		QUADD_ARMV8_HW_EVENT_L1_DCACHE_REFILL,
+	[QUADD_EVENT_TYPE_L1_ICACHE_MISSES] =
+		QUADD_ARMV8_HW_EVENT_L1_ICACHE_REFILL,
+
+	[QUADD_EVENT_TYPE_L2_DCACHE_READ_MISSES] =
+		QUADD_ARMV8_HW_EVENT_L2_CACHE_REFILL,
+	[QUADD_EVENT_TYPE_L2_DCACHE_WRITE_MISSES] =
+		QUADD_ARMV8_HW_EVENT_L2_CACHE_REFILL,
+	[QUADD_EVENT_TYPE_L2_ICACHE_MISSES] =
+		QUADD_ARMV8_UNSUPPORTED_EVENT,
+};
+
+static unsigned
+quadd_armv8_pmuv3_a57_events_map[QUADD_EVENT_TYPE_MAX] = {
+	[QUADD_EVENT_TYPE_INSTRUCTIONS] =
+		QUADD_ARMV8_HW_EVENT_INSTR_EXECUTED,
+	[QUADD_EVENT_TYPE_BRANCH_INSTRUCTIONS] =
+		QUADD_ARMV8_UNSUPPORTED_EVENT,
+	[QUADD_EVENT_TYPE_BRANCH_MISSES] =
+		QUADD_ARMV8_HW_EVENT_PC_BRANCH_MIS_PRED,
+	[QUADD_EVENT_TYPE_BUS_CYCLES] =
+		QUADD_ARMV8_UNSUPPORTED_EVENT,
+
+	[QUADD_EVENT_TYPE_L1_DCACHE_READ_MISSES] =
+		QUADD_ARMV8_A57_HW_EVENT_L1D_CACHE_REFILL_LD,
+	[QUADD_EVENT_TYPE_L1_DCACHE_WRITE_MISSES] =
+		QUADD_ARMV8_A57_HW_EVENT_L1D_CACHE_REFILL_ST,
+	[QUADD_EVENT_TYPE_L1_ICACHE_MISSES] =
+		QUADD_ARMV8_HW_EVENT_L1_ICACHE_REFILL,
+
+	[QUADD_EVENT_TYPE_L2_DCACHE_READ_MISSES] =
+		QUADD_ARMV8_A57_HW_EVENT_L2D_CACHE_REFILL_LD,
+	[QUADD_EVENT_TYPE_L2_DCACHE_WRITE_MISSES] =
+		QUADD_ARMV8_A57_HW_EVENT_L2D_CACHE_REFILL_ST,
+	[QUADD_EVENT_TYPE_L2_ICACHE_MISSES] =
+		QUADD_ARMV8_UNSUPPORTED_EVENT,
+};
+
+static unsigned
+quadd_armv8_pmuv3_denver_events_map[QUADD_EVENT_TYPE_MAX] = {
 	[QUADD_EVENT_TYPE_INSTRUCTIONS] =
 		QUADD_ARMV8_HW_EVENT_INSTR_EXECUTED,
 	[QUADD_EVENT_TYPE_BRANCH_INSTRUCTIONS] =
@@ -750,6 +803,7 @@ struct quadd_event_source_interface *quadd_armv8_pmu_init(void)
 	strncpy(pmu_ctx.arch.name, "Unknown", sizeof(pmu_ctx.arch.name));
 	pmu_ctx.arch.type = QUADD_AA64_CPU_TYPE_UNKNOWN;
 	pmu_ctx.arch.ver = 0;
+	pmu_ctx.current_map = NULL;
 
 	switch (aa64_dfr) {
 	case QUADD_AA64_PMUVER_PMUV3:
@@ -759,7 +813,8 @@ struct quadd_event_source_interface *quadd_armv8_pmu_init(void)
 
 		pmu_ctx.counters_mask =
 			QUADD_ARMV8_COUNTERS_MASK_PMUV3;
-		pmu_ctx.current_map = quadd_armv8_pmuv3_events_map;
+		pmu_ctx.current_map =
+			quadd_armv8_pmuv3_arm_events_map;
 
 		pmcr = armv8_pmu_pmcr_read();
 
@@ -775,10 +830,20 @@ struct quadd_event_source_interface *quadd_armv8_pmu_init(void)
 				strlen(pmu_ctx.arch.name));
 			pmu_ctx.arch.name[sizeof(pmu_ctx.arch.name) - 1] = '\0';
 
-			if (idcode == QUADD_AA64_CPU_IDCODE_CORTEX_A57) {
+			if (idcode == QUADD_AA64_CPU_IDCODE_CORTEX_A53) {
+				pmu_ctx.arch.type =
+					QUADD_AA64_CPU_TYPE_CORTEX_A53;
+
+				strncat(pmu_ctx.arch.name, " CORTEX-A53",
+					sizeof(pmu_ctx.arch.name) -
+					strlen(pmu_ctx.arch.name));
+			} else if (idcode == QUADD_AA64_CPU_IDCODE_CORTEX_A57) {
 				pmu_ctx.arch.type =
 					QUADD_AA64_CPU_TYPE_CORTEX_A57;
-				strncat(pmu_ctx.arch.name, " CORTEX_A57",
+				pmu_ctx.current_map =
+					quadd_armv8_pmuv3_a57_events_map;
+
+				strncat(pmu_ctx.arch.name, " CORTEX-A57",
 					sizeof(pmu_ctx.arch.name) -
 					strlen(pmu_ctx.arch.name));
 			} else {
@@ -792,8 +857,11 @@ struct quadd_event_source_interface *quadd_armv8_pmu_init(void)
 			strncat(pmu_ctx.arch.name, " NVIDIA (Denver)",
 				sizeof(pmu_ctx.arch.name) -
 				strlen(pmu_ctx.arch.name));
+
 			pmu_ctx.arch.type = QUADD_AA64_CPU_TYPE_DENVER;
 			pmu_ctx.arch.ver = ext_ver;
+			pmu_ctx.current_map =
+				quadd_armv8_pmuv3_denver_events_map;
 		} else {
 			strncat(pmu_ctx.arch.name, " Unknown implementor code",
 				sizeof(pmu_ctx.arch.name) -
diff --git a/drivers/misc/tegra-profiler/version.h b/drivers/misc/tegra-profiler/version.h
index 1c12e5afb604..88210df23026 100644
--- a/drivers/misc/tegra-profiler/version.h
+++ b/drivers/misc/tegra-profiler/version.h
@@ -18,7 +18,7 @@
 #ifndef __QUADD_VERSION_H
 #define __QUADD_VERSION_H
 
-#define QUADD_MODULE_VERSION		"1.83"
+#define QUADD_MODULE_VERSION		"1.84"
 #define QUADD_MODULE_BRANCH		"Dev"
 
 #endif	/* __QUADD_VERSION_H */