diff options
| author | Dong Aisheng <aisheng.dong@freescale.com> | 2015-10-10 17:22:57 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:23:32 +0800 |
| commit | 1e1b24e77bf2d7143a9e7eeaae24c3361fa26aea (patch) | |
| tree | 955929d70a0ecf0bcca3a18cb420a5647711580b | |
| parent | 57064da0c63c3ddef084bb742b752d97af6b5e5f (diff) | |
MLK-11683 dts: imx6qp-sabresd: enhance uSDHC clk pad driver strength
The old driver strength of uSDHC clk pad of two slot can not work well
on the new imx6qp sabresd board because we can easily meet CRC errors
due to signal quality issue, especially with a SDIO card.
Enhance the driver strength of the CLK pad from 0x10059 to 0x10071
to avoid such issue
Signed-off-by: Dong Aisheng <aisheng.dong@freescale.com>
(cherry picked from commit 59a54039528cc2a7df30ee62e37bc47487c163e4)
| -rw-r--r-- | arch/arm/boot/dts/imx6qp-sabresd.dts | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qp-sabresd.dts b/arch/arm/boot/dts/imx6qp-sabresd.dts index 1397f8653cd3..879fdca30534 100644 --- a/arch/arm/boot/dts/imx6qp-sabresd.dts +++ b/arch/arm/boot/dts/imx6qp-sabresd.dts @@ -92,6 +92,40 @@ status = "disabled"; }; +&iomuxc { + imx6qdl-sabresd { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + }; +}; + &mxcfb1 { prefetch; }; |