Merge branch 'imx_4.14.98_2.3.0' into toradex_4.14-2.3.x-imx

Fix conflicts after merging changes from the latest NXP branch.

 Conflicts:
          arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
          drivers/pci/dwc/pci-imx6.c

Related-to: ELB-1306
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>

19 files changed, 501 insertions, 152 deletions

diff --git a/Documentation/devicetree/bindings/ata/imx-sata.txt b/Documentation/devicetree/bindings/ata/imx-sata.txt
index 49c4135dd9f2..d4bfd51443d5 100644
--- a/Documentation/devicetree/bindings/ata/imx-sata.txt
+++ b/Documentation/devicetree/bindings/ata/imx-sata.txt
@@ -26,6 +26,8 @@ Optional properties:
 - fsl,phy-imp: PHY impedance ratio value refer to the differnt HW design.
   Set it to 0x6c when 85OHM is used, keep it to default value 0x80 when
   100OHM is used.
+- clock-names : imx8qm sata requires some extra cloks "per_clk0",
+  "per_clk1", "per_clk2","per_clk3", "per_clk4", "per_clk5",
 
 Examples:
 
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index fd55fa614226..77f08d0f55a2 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QM) += fsl-imx8qm-lpddr4-arm2.dtb \
 				 fsl-imx8qm-mek-domu-dpu1-hdmi.dtb \
 				 fsl-imx8qm-mek-root.dtb \
 				 fsl-imx8qm-mek-inmate.dtb \
+				 fsl-imx8qm-pcieax2pciebx1.dtb \
 				 fsl-imx8qm-lpddr4-arm2-dp.dtb \
 				 fsl-imx8qm-lpddr4-arm2-hdmi.dtb \
 				 fsl-imx8qm-lpddr4-arm2-hdmi-in.dtb \
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi
index 913f8e83707a..3aebf64eaa2b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi
@@ -1108,7 +1108,7 @@
 			};
 		};
 
-		pd_hsio: hsio-power-domain {
+		pd_hsio: PD_HSIO {
 			compatible = "nxp,imx8-pd";
 			reg = <SC_R_NONE>;
 			#power-domain-cells = <0>;
@@ -3553,8 +3553,11 @@
 			 <&clk IMX8QXP_HSIO_PCIE_SLV_AXI_CLK>,
 			 <&clk IMX8QXP_HSIO_PHY_X1_PCLK>,
 			 <&clk IMX8QXP_HSIO_PCIE_X1_PER_CLK>,
-			 <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>;
-		clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi";
+			 <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>,
+			 <&clk IMX8QXP_HSIO_PHY_X1_PER_CLK>,
+			 <&clk IMX8QXP_HSIO_MISC_PER_CLK>;
+		clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per",
+			"pcie_inbound_axi", "phy_per", "misc_per";
 
 		interrupt-map-mask = <0 0 0 0x7>;
 		interrupt-map =  <0 0 0 1 &gic 0 105 4>,
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts
index 5a522e6c05fc..30dd84f67da6 100755
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts
@@ -630,8 +630,8 @@
 			ldo1_reg: regulator@8 {
 				reg = <8>;
 				regulator-compatible = "ldo1";
-				regulator-min-microvolt = <3000000>;
-				regulator-max-microvolt = <3300000>;
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <1900000>;
 				regulator-boot-on;
 				regulator-always-on;
 			};
@@ -639,7 +639,7 @@
 			ldo2_reg: regulator@9 {
 				reg = <9>;
 				regulator-compatible = "ldo2";
-				regulator-min-microvolt = <900000>;
+				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <900000>;
 				regulator-boot-on;
 				regulator-always-on;
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts
index 86e2c78e99ff..d8a516c71e22 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts
@@ -613,8 +613,8 @@
 			ldo1_reg: regulator@8 {
 				reg = <8>;
 				regulator-compatible = "ldo1";
-				regulator-min-microvolt = <3000000>;
-				regulator-max-microvolt = <3300000>;
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <1900000>;
 				regulator-boot-on;
 				regulator-always-on;
 			};
@@ -622,7 +622,7 @@
 			ldo2_reg: regulator@9 {
 				reg = <9>;
 				regulator-compatible = "ldo2";
-				regulator-min-microvolt = <900000>;
+				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <900000>;
 				regulator-boot-on;
 				regulator-always-on;
@@ -966,12 +966,6 @@
 };
 
 &A53_0 {
-	operating-points = <
-		/* kHz    uV */
-		1500000 1000000
-		1400000 950000
-		1200000 950000
-	>;
 	arm-supply = <&buck2_reg>;
 };
 
@@ -984,6 +978,19 @@
 };
 
 &gpu {
+	assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>,
+			<&clk IMX8MN_CLK_GPU_SHADER_SRC>,
+			<&clk IMX8MN_CLK_GPU_AXI>,
+			<&clk IMX8MN_CLK_GPU_AHB>,
+			<&clk IMX8MN_GPU_PLL>,
+			<&clk IMX8MN_CLK_GPU_CORE_DIV>,
+			<&clk IMX8MN_CLK_GPU_SHADER_DIV>;
+	assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
+				<&clk IMX8MN_GPU_PLL_OUT>,
+				<&clk IMX8MN_SYS_PLL1_800M>,
+				<&clk IMX8MN_SYS_PLL1_800M>;
+	assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>,
+				<400000000>, <400000000>;
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
index c85fd8aed9ad..71133435d2f6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
@@ -4160,8 +4160,12 @@
 		clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>,
 			 <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>,
 			 <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>,
-			 <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>;
-		clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
+			 <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>,
+			 <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>,
+			 <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>,
+			 <&clk IMX8QM_HSIO_MISC_PER_CLK>;
+		clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per",
+				"pcie_inbound_axi", "phy_per", "misc_per";
 
 		interrupt-map-mask = <0 0 0 0x7>;
 		interrupt-map =  <0 0 0 1 &gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
@@ -4203,8 +4207,13 @@
 		clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>,
 			 <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>,
 			 <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>,
-			 <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>;
-		clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
+			 <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>,
+			 <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>,
+			 <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>,
+			 <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>,
+			 <&clk IMX8QM_HSIO_MISC_PER_CLK>;
+		clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pciex2_per",
+				"pcie_inbound_axi", "phy_per", "misc_per";
 
 		interrupt-map-mask = <0 0 0 0x7>;
 		interrupt-map =  <0 0 0 1 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
@@ -4230,10 +4239,18 @@
 			 <&clk IMX8QM_HSIO_PHY_X1_PCLK>,
 			 <&clk IMX8QM_HSIO_SATA_EPCS_TX_CLK>,
 			 <&clk IMX8QM_HSIO_SATA_EPCS_RX_CLK>,
+			 <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>,
+			 <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>,
+			 <&clk IMX8QM_HSIO_SATA_PER_CLK>,
+			 <&clk IMX8QM_HSIO_PHY_X1_PER_CLK>,
+			 <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>,
+			 <&clk IMX8QM_HSIO_MISC_PER_CLK>,
 			 <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>,
 			 <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>,
 			 <&clk IMX8QM_HSIO_PHY_X1_APB_CLK>;
 		clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx",
+				"per_clk0", "per_clk1", "per_clk2",
+				"per_clk3", "per_clk4", "per_clk5",
 				"phy_pclk0", "phy_pclk1", "phy_apbclk";
 		hsio = <&hsio>;
 		power-domains = <&pd_sata0>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi
index 4c2c29695644..8634b5d1f30a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi
@@ -466,6 +466,14 @@
 			>;
 		};
 
+		pinctrl_pcieb: pciebgrp {
+			fsl,pins = <
+				SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30	0x06000021
+				SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31		0x04000021
+				SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00		0x06000021
+			>;
+		};
+
 		pinctrl_sim0: sim0grp {
 			fsl,pins = <
 				SC_P_SIM0_CLK_DMA_SIM0_CLK		0xc0000021
@@ -1138,6 +1146,15 @@
 	status = "okay";
 };
 
+&pcieb {
+	ext_osc = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcieb>;
+	reset-gpio = <&gpio5 0 GPIO_ACTIVE_LOW>;
+	clkreq-gpio = <&gpio4 30 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
 &intmux_cm40 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts
new file mode 100644
index 000000000000..6bac94c0b44c
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 NXP
+ */
+
+
+#include "fsl-imx8qm-mek.dts"
+
+/*
+ * Add the PCIeA x2 lanes and PCIeB x1 lane usecase
+ * hsio-cfg = <PCIEAX2PCIEBX1>
+ * NOTE: In this case, the HSIO nodes contained
+ * hsio-cfg = <PCIEAX1PCIEBX1SATA> would be re-configured.
+ */
+&pciea{
+	ext_osc = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pciea>;
+	disable-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
+	reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
+	clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
+	epdev_on-supply = <&epdev_on>;
+	num-lanes = <2>;
+	clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>,
+		 <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>,
+		 <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>,
+		 <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>,
+		 <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>,
+		 <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>,
+		 <&clk IMX8QM_HSIO_MISC_PER_CLK>;
+	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per",
+			"pcie_inbound_axi", "phy_per", "misc_per";
+	hsio-cfg = <PCIEAX2PCIEBX1>;
+	status = "okay";
+};
+
+&pcieb{
+	ext_osc = <1>;
+	clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>,
+		 <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>,
+		 <&clk IMX8QM_HSIO_PHY_X1_PCLK>,
+		 <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>,
+		 <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>,
+		 <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>,
+		 <&clk IMX8QM_HSIO_PHY_X1_PER_CLK>,
+		 <&clk IMX8QM_HSIO_MISC_PER_CLK>;
+	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pciex2_per",
+			"pcie_inbound_axi", "phy_per", "misc_per";
+	power-domains = <&pd_pcie1>;
+	hsio-cfg = <PCIEAX2PCIEBX1>;
+	status = "okay";
+};
+
+&sata {
+	status = "disabled";
+};
+
diff --git a/crypto/tcrypt.c b/crypto/tcrypt.c
index 54952bd885c4..8bbc5de37ca4 100644
--- a/crypto/tcrypt.c
+++ b/crypto/tcrypt.c
@@ -224,7 +224,7 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs,
 	struct scatterlist *sg;
 	struct scatterlist *sgout;
 	const char *e;
-	void *assoc;
+	void *assoc, *assoc_out;
 	char *iv;
 	char *xbuf[XBUFSIZE];
 	char *xoutbuf[XBUFSIZE];
@@ -287,6 +287,8 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs,
 		do {
 			assoc = axbuf[0];
 			memset(assoc, 0xff, aad_size);
+			assoc_out = axbuf[1];
+			memset(assoc_out, 0xff, aad_size);
 
 			if ((*keysize + *b_size) > TVMEMSIZE * PAGE_SIZE) {
 				pr_err("template (%u) too big for tvmem (%lu)\n",
@@ -326,7 +328,7 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs,
 				     assoc, aad_size);
 
 			sg_init_aead(sgout, xoutbuf,
-				     *b_size + (enc ? authsize : 0), assoc,
+				     *b_size + (enc ? authsize : 0), assoc_out,
 				     aad_size);
 
 			aead_request_set_ad(req, aad_size);
@@ -348,6 +350,9 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs,
 					       ret);
 					break;
 				}
+
+				memset(assoc, 0xff, aad_size);
+				memset(assoc_out, 0xff, aad_size);
 			}
 
 			aead_request_set_crypt(req, sg, sgout,
diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c
index e1b0fe4cef7c..16e19affc514 100644
--- a/drivers/ata/ahci_imx.c
+++ b/drivers/ata/ahci_imx.c
@@ -148,6 +148,12 @@ struct imx_ahci_priv {
 	struct clk *phy_apbclk;
 	struct clk *phy_pclk0;
 	struct clk *phy_pclk1;
+	struct clk *per_clk0;
+	struct clk *per_clk1;
+	struct clk *per_clk2;
+	struct clk *per_clk3;
+	struct clk *per_clk4;
+	struct clk *per_clk5;
 	void __iomem *phy_base;
 	struct clk *sata_ext;
 	int clkreq_gpio;
@@ -484,39 +490,112 @@ static struct attribute *fsl_sata_ahci_attrs[] = {
 };
 ATTRIBUTE_GROUPS(fsl_sata_ahci);
 
-static int imx8_sata_enable(struct ahci_host_priv *hpriv)
+static int imx8_sata_clk_enable(struct imx_ahci_priv *imxpriv)
 {
-	u32 val, reg;
-	int i, ret;
-	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
+	int ret;
 	struct device *dev = &imxpriv->ahci_pdev->dev;
 
 	/* configure the hsio for sata */
 	ret = clk_prepare_enable(imxpriv->phy_pclk0);
 	if (ret < 0) {
-		dev_err(dev, "can't enable phy pclk0.\n");
+		dev_err(dev, "can't enable phy_pclk0.\n");
 		return ret;
 	}
 	ret = clk_prepare_enable(imxpriv->phy_pclk1);
 	if (ret < 0) {
-		dev_err(dev, "can't enable phy pclk1.\n");
+		dev_err(dev, "can't enable phy_pclk1.\n");
 		goto disable_phy_pclk0;
 	}
 	ret = clk_prepare_enable(imxpriv->epcs_tx_clk);
 	if (ret < 0) {
-		dev_err(dev, "can't enable epcs tx clk.\n");
+		dev_err(dev, "can't enable epcs_tx_clk.\n");
 		goto disable_phy_pclk1;
 	}
 	ret = clk_prepare_enable(imxpriv->epcs_rx_clk);
 	if (ret < 0) {
-		dev_err(dev, "can't enable epcs rx clk.\n");
+		dev_err(dev, "can't enable epcs_rx_clk.\n");
 		goto disable_epcs_tx_clk;
 	}
 	ret = clk_prepare_enable(imxpriv->phy_apbclk);
 	if (ret < 0) {
-		dev_err(dev, "can't enable phy pclk1.\n");
+		dev_err(dev, "can't enable phy_apbclk.\n");
 		goto disable_epcs_rx_clk;
 	}
+	ret = clk_prepare_enable(imxpriv->per_clk0);
+	if (ret < 0) {
+		dev_err(dev, "can't enable per_clk.\n");
+		goto disable_phy_apbclk;
+	}
+	ret = clk_prepare_enable(imxpriv->per_clk1);
+	if (ret < 0) {
+		dev_err(dev, "can't enable per_clk.\n");
+		goto disable_per_clk0;
+	}
+	ret = clk_prepare_enable(imxpriv->per_clk2);
+	if (ret < 0) {
+		dev_err(dev, "can't enable per_clk.\n");
+		goto disable_per_clk1;
+	}
+	ret = clk_prepare_enable(imxpriv->per_clk3);
+	if (ret < 0) {
+		dev_err(dev, "can't enable per_clk.\n");
+		goto disable_per_clk2;
+	}
+	ret = clk_prepare_enable(imxpriv->per_clk4);
+	if (ret < 0) {
+		dev_err(dev, "can't enable per_clk.\n");
+		goto disable_per_clk3;
+	}
+	ret = clk_prepare_enable(imxpriv->per_clk5);
+	if (ret < 0)
+		dev_err(dev, "can't enable per_clk.\n");
+	else
+		return 0;
+
+	clk_disable_unprepare(imxpriv->per_clk4);
+disable_per_clk3:
+	clk_disable_unprepare(imxpriv->per_clk3);
+disable_per_clk2:
+	clk_disable_unprepare(imxpriv->per_clk2);
+disable_per_clk1:
+	clk_disable_unprepare(imxpriv->per_clk1);
+disable_per_clk0:
+	clk_disable_unprepare(imxpriv->per_clk0);
+disable_phy_apbclk:
+	clk_disable_unprepare(imxpriv->phy_apbclk);
+disable_epcs_rx_clk:
+	clk_disable_unprepare(imxpriv->epcs_rx_clk);
+disable_epcs_tx_clk:
+	clk_disable_unprepare(imxpriv->epcs_tx_clk);
+disable_phy_pclk1:
+	clk_disable_unprepare(imxpriv->phy_pclk1);
+disable_phy_pclk0:
+	clk_disable_unprepare(imxpriv->phy_pclk0);
+	return ret;
+}
+
+static void imx8_sata_clk_disable(struct imx_ahci_priv *imxpriv)
+{
+	clk_disable_unprepare(imxpriv->epcs_rx_clk);
+	clk_disable_unprepare(imxpriv->epcs_tx_clk);
+	clk_disable_unprepare(imxpriv->per_clk5);
+	clk_disable_unprepare(imxpriv->per_clk4);
+	clk_disable_unprepare(imxpriv->per_clk3);
+	clk_disable_unprepare(imxpriv->per_clk2);
+	clk_disable_unprepare(imxpriv->per_clk1);
+	clk_disable_unprepare(imxpriv->per_clk0);
+}
+
+static int imx8_sata_enable(struct ahci_host_priv *hpriv)
+{
+	u32 val, reg;
+	int i, ret;
+	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
+	struct device *dev = &imxpriv->ahci_pdev->dev;
+
+	ret = imx8_sata_clk_enable(imxpriv);
+	if (ret)
+		return ret;
 	/* Configure PHYx2 PIPE_RSTN */
 	regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEA_OFFSET
 			+ IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val);
@@ -745,14 +824,9 @@ static int imx8_sata_enable(struct ahci_host_priv *hpriv)
 
 err_out:
 	clk_disable_unprepare(imxpriv->phy_apbclk);
-disable_epcs_rx_clk:
-	clk_disable_unprepare(imxpriv->epcs_rx_clk);
-disable_epcs_tx_clk:
-	clk_disable_unprepare(imxpriv->epcs_tx_clk);
-disable_phy_pclk1:
 	clk_disable_unprepare(imxpriv->phy_pclk1);
-disable_phy_pclk0:
 	clk_disable_unprepare(imxpriv->phy_pclk0);
+	imx8_sata_clk_disable(imxpriv);
 
 	return ret;
 }
@@ -858,8 +932,7 @@ static void imx_sata_disable(struct ahci_host_priv *hpriv)
 	}
 
 	if (imxpriv->type == AHCI_IMX8QM) {
-		clk_disable_unprepare(imxpriv->epcs_rx_clk);
-		clk_disable_unprepare(imxpriv->epcs_tx_clk);
+		imx8_sata_clk_disable(imxpriv);
 	}
 	clk_disable_unprepare(imxpriv->sata_ref_clk);
 
@@ -1169,6 +1242,36 @@ static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv)
 		return PTR_ERR(imxpriv->phy_apbclk);
 	}
 
+	imxpriv->per_clk0 = devm_clk_get(dev, "per_clk0");
+	if (IS_ERR(imxpriv->per_clk0)) {
+		dev_err(dev, "can't get per_clk0 clock.\n");
+		return PTR_ERR(imxpriv->per_clk0);
+	}
+	imxpriv->per_clk1 = devm_clk_get(dev, "per_clk1");
+	if (IS_ERR(imxpriv->per_clk1)) {
+		dev_err(dev, "can't get per_clk1 clock.\n");
+		return PTR_ERR(imxpriv->per_clk1);
+	}
+	imxpriv->per_clk2 = devm_clk_get(dev, "per_clk2");
+	if (IS_ERR(imxpriv->per_clk2)) {
+		dev_err(dev, "can't get per_clk2 clock.\n");
+		return PTR_ERR(imxpriv->per_clk2);
+	}
+	imxpriv->per_clk3 = devm_clk_get(dev, "per_clk3");
+	if (IS_ERR(imxpriv->per_clk3)) {
+		dev_err(dev, "can't get per_clk3 clock.\n");
+		return PTR_ERR(imxpriv->per_clk3);
+	}
+	imxpriv->per_clk4 = devm_clk_get(dev, "per_clk4");
+	if (IS_ERR(imxpriv->per_clk4)) {
+		dev_err(dev, "can't get per_clk4 clock.\n");
+		return PTR_ERR(imxpriv->per_clk4);
+	}
+	imxpriv->per_clk5 = devm_clk_get(dev, "per_clk5");
+	if (IS_ERR(imxpriv->per_clk5)) {
+		dev_err(dev, "can't get per_clk5 clock.\n");
+		return PTR_ERR(imxpriv->per_clk5);
+	}
 	/* Fetch GPIO, then enable the external OSC */
 	imxpriv->clkreq_gpio = of_get_named_gpio(np, "clkreq-gpio", 0);
 	if (gpio_is_valid(imxpriv->clkreq_gpio)) {
diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c
index 961d848ebc6c..6051f7dc79e6 100644
--- a/drivers/crypto/caam/caamhash.c
+++ b/drivers/crypto/caam/caamhash.c
@@ -119,7 +119,7 @@ struct caam_hash_state {
 	u8 buf_1[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
 	int buflen_1;
 	u8 caam_ctx[MAX_CTX_LEN] ____cacheline_aligned;
-	int (*update)(struct ahash_request *req);
+	int (*update)(struct ahash_request *req) ____cacheline_aligned;
 	int (*final)(struct ahash_request *req);
 	int (*finup)(struct ahash_request *req);
 	int current_buf;
diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c
index 15371c3d5efa..aca752562821 100644
--- a/drivers/crypto/caam/jr.c
+++ b/drivers/crypto/caam/jr.c
@@ -452,8 +452,16 @@ int caam_jr_enqueue(struct device *dev, u32 *desc,
 	 * Guarantee that the descriptor's DMA address has been written to
 	 * the next slot in the ring before the write index is updated, since
 	 * other cores may update this index independently.
+	 *
+	 * Under heavy DDR load, smp_wmb() or dma_wmb() fail to make the input
+	 * ring be updated before the CAAM starts reading it. So, CAAM will
+	 * process, again, an old descriptor address and will put it in the
+	 * output ring. This will make caam_jr_dequeue() to fail, since this
+	 * old descriptor is not in the software ring.
+	 * To fix this, use wmb() which works on the full system instead of
+	 * inner/outer shareable domains.
 	 */
-	smp_wmb();
+	wmb();
 
 	jrp->inp_ring_write_index = (jrp->inp_ring_write_index + 1) &
 				    (JOBR_DEPTH - 1);
diff --git a/drivers/crypto/mxs-dcp.c b/drivers/crypto/mxs-dcp.c
index 71cb9f5543ce..a334fa954ee0 100644
--- a/drivers/crypto/mxs-dcp.c
+++ b/drivers/crypto/mxs-dcp.c
@@ -26,6 +26,7 @@
 #include <crypto/sha.h>
 #include <crypto/internal/hash.h>
 #include <crypto/internal/skcipher.h>
+#include <crypto/scatterwalk.h>
 
 #define DCP_MAX_CHANS	4
 #define DCP_BUF_SZ	PAGE_SIZE
@@ -638,49 +639,46 @@ static int dcp_sha_req_to_buf(struct crypto_async_request *arq)
 	struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
 	struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
 	struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
-	const int nents = sg_nents(req->src);
 
 	uint8_t *in_buf = sdcp->coh->sha_in_buf;
 	uint8_t *out_buf = sdcp->coh->sha_out_buf;
 
-	uint8_t *src_buf;
-
 	struct scatterlist *src;
 
-	unsigned int i, len, clen;
+	unsigned int i, len, clen, oft = 0;
 	int ret;
 
 	int fin = rctx->fini;
 	if (fin)
 		rctx->fini = 0;
 
-	for_each_sg(req->src, src, nents, i) {
-		src_buf = sg_virt(src);
-		len = sg_dma_len(src);
-
-		do {
-			if (actx->fill + len > DCP_BUF_SZ)
-				clen = DCP_BUF_SZ - actx->fill;
-			else
-				clen = len;
-
-			memcpy(in_buf + actx->fill, src_buf, clen);
-			len -= clen;
-			src_buf += clen;
-			actx->fill += clen;
+	src = req->src;
+	len = req->nbytes;
 
-			/*
-			 * If we filled the buffer and still have some
-			 * more data, submit the buffer.
-			 */
-			if (len && actx->fill == DCP_BUF_SZ) {
-				ret = mxs_dcp_run_sha(req);
-				if (ret)
-					return ret;
-				actx->fill = 0;
-				rctx->init = 0;
-			}
-		} while (len);
+	while (len) {
+		if (actx->fill + len > DCP_BUF_SZ)
+			clen = DCP_BUF_SZ - actx->fill;
+		else
+			clen = len;
+
+		scatterwalk_map_and_copy(in_buf + actx->fill, src, oft, clen,
+					 0);
+
+		len -= clen;
+		oft += clen;
+		actx->fill += clen;
+
+		/*
+		 * If we filled the buffer and still have some
+		 * more data, submit the buffer.
+		 */
+		if (len && actx->fill == DCP_BUF_SZ) {
+			ret = mxs_dcp_run_sha(req);
+			if (ret)
+				return ret;
+			actx->fill = 0;
+			rctx->init = 0;
+		}
 	}
 
 	if (fin) {
diff --git a/drivers/mxc/vpu_malone/vpu_b0.c b/drivers/mxc/vpu_malone/vpu_b0.c
index 6757f7251ec0..7ee3e8a5f570 100644
--- a/drivers/mxc/vpu_malone/vpu_b0.c
+++ b/drivers/mxc/vpu_malone/vpu_b0.c
@@ -40,7 +40,7 @@
 #include <media/v4l2-mem2mem.h>
 #include <media/videobuf2-v4l2.h>
 #include <media/videobuf2-dma-contig.h>
-#include <media/videobuf2-dma-sg.h>
+#include <media/videobuf2-vmalloc.h>
 
 #include "vpu_b0.h"
 #include "insert_startcode.h"
@@ -5650,8 +5650,7 @@ static int create_instance_file(struct vpu_ctx *ctx)
 	create_instance_buffer_file(ctx);
 	create_instance_flow_file(ctx);
 	create_instance_perf_file(ctx);
-	atomic64_set(&ctx->statistic.total_dma_size, 0);
-	atomic64_set(&ctx->statistic.total_alloc_size, 0);
+
 
 	return 0;
 }
@@ -5816,13 +5815,24 @@ static int v4l2_open(struct file *filp)
 	mutex_init(&ctx->instance_mutex);
 	mutex_init(&ctx->cmd_lock);
 	mutex_init(&ctx->perf_lock);
-	if (kfifo_alloc(&ctx->msg_fifo,
-			sizeof(struct event_msg) * VID_API_MESSAGE_LIMIT,
-			GFP_KERNEL)) {
+	atomic64_set(&ctx->statistic.total_dma_size, 0);
+	atomic64_set(&ctx->statistic.total_alloc_size, 0);
+
+	ctx->msg_buffer_size = sizeof(struct event_msg) * VID_API_MESSAGE_LIMIT;
+	if (!is_power_of_2(ctx->msg_buffer_size))
+		ctx->msg_buffer_size = roundup_pow_of_two(ctx->msg_buffer_size);
+	ctx->msg_buffer = vzalloc(ctx->msg_buffer_size);
+	if (!ctx->msg_buffer) {
 		vpu_err("fail to alloc fifo when open\n");
 		ret = -ENOMEM;
 		goto err_alloc_fifo;
 	}
+	atomic64_add(ctx->msg_buffer_size, &ctx->statistic.total_alloc_size);
+	if (kfifo_init(&ctx->msg_fifo, ctx->msg_buffer, ctx->msg_buffer_size)) {
+		vpu_err("fail to init fifo when open\n");
+		ret = -EINVAL;
+		goto err_init_kfifo;
+	}
 	ctx->dev = dev;
 	ctx->str_index = idx;
 	dev->ctx[idx] = ctx;
@@ -5906,8 +5916,12 @@ err_open_crc:
 	ctx->tsm = NULL;
 err_create_tsm:
 	remove_instance_file(ctx);
-	kfifo_free(&ctx->msg_fifo);
 	dev->ctx[idx] = NULL;
+err_init_kfifo:
+	vfree(ctx->msg_buffer);
+	atomic64_sub(ctx->msg_buffer_size, &ctx->statistic.total_alloc_size);
+	ctx->msg_buffer = NULL;
+	ctx->msg_buffer_size = 0;
 err_alloc_fifo:
 	mutex_destroy(&ctx->instance_mutex);
 	mutex_destroy(&ctx->cmd_lock);
@@ -5983,7 +5997,10 @@ static int v4l2_release(struct file *filp)
 	mutex_lock(&ctx->dev->dev_mutex);
 	ctx->ctx_released = true;
 	cancel_work_sync(&ctx->instance_work);
-	kfifo_free(&ctx->msg_fifo);
+	vfree(ctx->msg_buffer);
+	atomic64_sub(ctx->msg_buffer_size, &ctx->statistic.total_alloc_size);
+	ctx->msg_buffer = NULL;
+	ctx->msg_buffer_size = 0;
 	if (ctx->instance_wq)
 		destroy_workqueue(ctx->instance_wq);
 	mutex_unlock(&ctx->dev->dev_mutex);
@@ -6331,13 +6348,21 @@ static int vpu_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_rm_vdev;
 
-	ret = kfifo_alloc(&dev->mu_msg_fifo,
-			  sizeof(u_int32) * VPU_MAX_NUM_STREAMS * VID_API_MESSAGE_LIMIT,
-			  GFP_KERNEL);
-	if (ret) {
+	dev->mu_msg_buffer_size =
+		sizeof(u_int32) * VPU_MAX_NUM_STREAMS * VID_API_MESSAGE_LIMIT;
+	if (!is_power_of_2(dev->mu_msg_buffer_size))
+		dev->mu_msg_buffer_size = roundup_pow_of_two(dev->mu_msg_buffer_size);
+	dev->mu_msg_buffer = vzalloc(dev->mu_msg_buffer_size);
+	if (!dev->mu_msg_buffer) {
 		vpu_err("error: fail to alloc mu msg fifo\n");
 		goto err_rm_vdev;
 	}
+	ret = kfifo_init(&dev->mu_msg_fifo,
+			dev->mu_msg_buffer, dev->mu_msg_buffer_size);
+	if (ret) {
+		vpu_err("error: fail to init mu msg fifo\n");
+		goto err_free_fifo;
+	}
 
 	dev->workqueue = alloc_workqueue("vpu", WQ_UNBOUND | WQ_MEM_RECLAIM, 1);
 	if (!dev->workqueue) {
@@ -6369,7 +6394,9 @@ err_poweroff:
 	pm_runtime_put_sync(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
 err_free_fifo:
-	kfifo_free(&dev->mu_msg_fifo);
+	vfree(dev->mu_msg_buffer);
+	dev->mu_msg_buffer = NULL;
+	dev->mu_msg_buffer_size = 0;
 err_rm_vdev:
 	if (dev->pvpu_decoder_dev) {
 		video_unregister_device(dev->pvpu_decoder_dev);
@@ -6406,7 +6433,9 @@ static int vpu_remove(struct platform_device *pdev)
 	dev->debugfs_root = NULL;
 	dev->debugfs_dbglog = NULL;
 	dev->debugfs_fwlog = NULL;
-	kfifo_free(&dev->mu_msg_fifo);
+	vfree(dev->mu_msg_buffer);
+	dev->mu_msg_buffer = NULL;
+	dev->mu_msg_buffer_size = 0;
 	destroy_workqueue(dev->workqueue);
 	if (dev->m0_p_fw_space_vir)
 		iounmap(dev->m0_p_fw_space_vir);
diff --git a/drivers/mxc/vpu_malone/vpu_b0.h b/drivers/mxc/vpu_malone/vpu_b0.h
index e1e0949e5237..3756a9ea7765 100644
--- a/drivers/mxc/vpu_malone/vpu_b0.h
+++ b/drivers/mxc/vpu_malone/vpu_b0.h
@@ -314,6 +314,8 @@ struct vpu_dev {
 	char precheck_content[1024];
 
 	struct kfifo mu_msg_fifo;
+	void *mu_msg_buffer;
+	unsigned int mu_msg_buffer_size;
 	u_int32 vpu_irq;
 
 	/* reserve for kernel version 5.4 or later */
@@ -399,6 +401,8 @@ struct vpu_ctx {
 	int str_index;
 	struct queue_data q_data[2];
 	struct kfifo msg_fifo;
+	void *msg_buffer;
+	unsigned int msg_buffer_size;
 	struct mutex instance_mutex;
 	struct work_struct instance_work;
 	struct workqueue_struct *instance_wq;
diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c
index 9242d211c24b..950a014984e4 100644
--- a/drivers/pci/dwc/pci-imx6.c
+++ b/drivers/pci/dwc/pci-imx6.c
@@ -78,6 +78,10 @@ struct imx_pcie {
 	struct clk		*pcie_bus;
 	struct clk		*pcie_phy;
 	struct clk		*pcie_inbound_axi;
+	struct clk		*pciex2_per;
+	struct clk		*pcie_per;
+	struct clk		*phy_per;
+	struct clk		*misc_per;
 	struct clk		*pcie;
 	struct clk		*pcie_ext;
 	struct clk		*pcie_ext_src;
@@ -310,6 +314,10 @@ struct imx_pcie {
 #define IMX8MM_GPR_PCIE_POWER_OFF		BIT(17)
 #define IMX8MM_GPR_PCIE_SSC_EN			BIT(16)
 
+static void pci_imx_clk_disable(struct device *dev);
+static void pci_imx_clk_enable(struct imx_pcie *imx_pcie);
+static void pci_imx_ltssm_disable(struct device *dev);
+
 static int pcie_phy_poll_ack(struct imx_pcie *imx_pcie, int exp_val)
 {
 	struct dw_pcie *pci = imx_pcie->pci;
@@ -526,21 +534,23 @@ static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
 		regmap_update_bits(imx_pcie->reg_src, 0x2c, BIT(2), BIT(2));
 		break;
 	case IMX8QXP:
-			val = IMX8QM_CSR_PCIEB_OFFSET;
-			regmap_update_bits(imx_pcie->iomuxc_gpr,
-					val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
-					IMX8QM_CTRL_BUTTON_RST_N,
-					IMX8QM_CTRL_BUTTON_RST_N);
-			regmap_update_bits(imx_pcie->iomuxc_gpr,
-					val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
-					IMX8QM_CTRL_PERST_N,
-					IMX8QM_CTRL_PERST_N);
-			regmap_update_bits(imx_pcie->iomuxc_gpr,
-					val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
-					IMX8QM_CTRL_POWER_UP_RST_N,
-					IMX8QM_CTRL_POWER_UP_RST_N);
+		pci_imx_clk_enable(imx_pcie);
+		val = IMX8QM_CSR_PCIEB_OFFSET;
+		regmap_update_bits(imx_pcie->iomuxc_gpr,
+				val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
+				IMX8QM_CTRL_BUTTON_RST_N,
+				IMX8QM_CTRL_BUTTON_RST_N);
+		regmap_update_bits(imx_pcie->iomuxc_gpr,
+				val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
+				IMX8QM_CTRL_PERST_N,
+				IMX8QM_CTRL_PERST_N);
+		regmap_update_bits(imx_pcie->iomuxc_gpr,
+				val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
+				IMX8QM_CTRL_POWER_UP_RST_N,
+				IMX8QM_CTRL_POWER_UP_RST_N);
 		break;
 	case IMX8QM:
+		pci_imx_clk_enable(imx_pcie);
 		for (i = 0; i <= imx_pcie->ctrl_id; i++) {
 			val = IMX8QM_CSR_PCIEA_OFFSET + i * SZ_64K;
 			regmap_update_bits(imx_pcie->iomuxc_gpr,
@@ -637,15 +647,88 @@ static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie)
 				IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
 
 		break;
-	case IMX8QXP:
 	case IMX8QM:
+	case IMX8QXP:
 		ret = clk_prepare_enable(imx_pcie->pcie_inbound_axi);
-		if (ret)
+		if (ret) {
 			dev_err(dev, "unable to enable pcie_axi clock\n");
+			return ret;
+		}
+		ret = clk_prepare_enable(imx_pcie->pcie_per);
+		if (ret) {
+			dev_err(dev, "unable to enable pcie_per clock\n");
+			goto err_pcie_per;
+		}
+		ret = clk_prepare_enable(imx_pcie->phy_per);
+		if (unlikely(ret)) {
+			dev_err(dev, "unable to enable phy per clock\n");
+			goto err_phy_per;
+		}
+		ret = clk_prepare_enable(imx_pcie->misc_per);
+		if (unlikely(ret)) {
+			dev_err(dev, "unable to enable misc per clock\n");
+			goto err_misc_per;
+		}
+		/*
+		 * PCIA CSR would be touched during the initialization of the
+		 * PCIEB of 8QM.
+		 * Enable the PCIEA peripheral clock for this case here.
+		 */
+		if (imx_pcie->variant == IMX8QM && imx_pcie->ctrl_id == 1) {
+			ret = clk_prepare_enable(imx_pcie->pciex2_per);
+			if (unlikely(ret)) {
+				dev_err(dev, "can't enable pciex2 per clock\n");
+				goto err_pciex2_per;
+			}
+		}
+		break;
+	default:
 		break;
 	}
 
 	return ret;
+err_pciex2_per:
+	clk_disable_unprepare(imx_pcie->misc_per);
+err_misc_per:
+	clk_disable_unprepare(imx_pcie->phy_per);
+err_phy_per:
+	clk_disable_unprepare(imx_pcie->pcie_per);
+err_pcie_per:
+	clk_disable_unprepare(imx_pcie->pcie_inbound_axi);
+	return ret;
+}
+
+static void pci_imx_clk_enable(struct imx_pcie *imx_pcie)
+{
+	int ret;
+	struct dw_pcie *pci = imx_pcie->pci;
+	struct device *dev = pci->dev;
+
+	ret = clk_prepare_enable(imx_pcie->pcie_phy);
+	if (ret)
+		dev_err(dev, "unable to enable pcie_phy clock\n");
+
+	if (imx_pcie->ext_osc && (imx_pcie->variant == IMX6QP))
+		clk_set_parent(imx_pcie->pcie_bus,
+				imx_pcie->pcie_ext_src);
+	ret = clk_prepare_enable(imx_pcie->pcie_bus);
+	if (ret)
+		dev_err(dev, "unable to enable pcie_bus clock\n");
+
+	ret = clk_prepare_enable(imx_pcie->pcie_ext);
+	if (ret)
+		dev_err(dev, "unable to enable pcie_ext clock\n");
+
+	ret = clk_prepare_enable(imx_pcie->pcie);
+	if (ret)
+		dev_err(dev, "unable to enable pcie clock\n");
+
+	ret = imx_pcie_enable_ref_clk(imx_pcie);
+	if (ret)
+		dev_err(dev, "unable to enable pcie ref clock\n");
+
+	/* allow the clocks to stabilize */
+	udelay(200);
 }
 
 static int imx7d_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
@@ -765,42 +848,16 @@ static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
 	if (imx_pcie->dis_gpiod)
 		gpiod_set_value_cansleep(imx_pcie->dis_gpiod, 0);
 
-	ret = clk_prepare_enable(imx_pcie->pcie);
-	if (ret) {
-		dev_err(dev, "unable to enable pcie clock\n");
-		goto err_pcie;
-	}
-
-	if (imx_pcie->ext_osc && (imx_pcie->variant == IMX6QP))
-		clk_set_parent(imx_pcie->pcie_bus,
-				imx_pcie->pcie_ext_src);
-	ret = clk_prepare_enable(imx_pcie->pcie_bus);
-	if (ret) {
-		dev_err(dev, "unable to enable pcie_bus clock\n");
-		goto err_pcie_bus;
-	}
-
-	ret = clk_prepare_enable(imx_pcie->pcie_ext);
-	if (ret) {
-		dev_err(dev, "unable to enable pcie_ext clock\n");
-		goto err_pcie_bus;
-	}
-
-	ret = clk_prepare_enable(imx_pcie->pcie_phy);
-	if (ret) {
-		dev_err(dev, "unable to enable pcie_phy clock\n");
-		goto err_pcie_phy;
-	}
-
-	ret = imx_pcie_enable_ref_clk(imx_pcie);
-	if (ret) {
-		dev_err(dev, "unable to enable pcie ref clock\n");
-		goto err_ref_clk;
+	switch (imx_pcie->variant) {
+	case IMX8QXP:
+	case IMX8QM:
+		/* ClKs had been enabled */
+		break;
+	default:
+		pci_imx_clk_enable(imx_pcie);
+		break;
 	}
 
-	/* allow the clocks to stabilize */
-	udelay(200);
-
 	switch (imx_pcie->variant) {
 	case IMX6SX:
 		regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
@@ -971,13 +1028,7 @@ static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
 	if (ret == 0)
 		return ret;
 
-err_ref_clk:
-	clk_disable_unprepare(imx_pcie->pcie_phy);
-err_pcie_phy:
-	clk_disable_unprepare(imx_pcie->pcie_bus);
-err_pcie_bus:
-	clk_disable_unprepare(imx_pcie->pcie);
-err_pcie:
+	pci_imx_clk_disable(dev);
 	if (imx_pcie->vpcie && regulator_is_enabled(imx_pcie->vpcie) > 0) {
 		ret = regulator_disable(imx_pcie->vpcie);
 		if (ret)
@@ -1497,9 +1548,14 @@ static void pci_imx_clk_disable(struct device *dev)
 				IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
 				0);
 		break;
-	case IMX8QXP:
 	case IMX8QM:
+		if (imx_pcie->ctrl_id == 1)
+			clk_disable_unprepare(imx_pcie->pciex2_per);
+	case IMX8QXP:
+		clk_disable_unprepare(imx_pcie->pcie_per);
 		clk_disable_unprepare(imx_pcie->pcie_inbound_axi);
+		clk_disable_unprepare(imx_pcie->phy_per);
+		clk_disable_unprepare(imx_pcie->misc_per);
 		break;
 	}
 }
@@ -2081,8 +2137,7 @@ static int pci_imx_suspend_noirq(struct device *dev)
 				IMX6Q_GPR1_PCIE_TEST_PD,
 				IMX6Q_GPR1_PCIE_TEST_PD);
 	} else {
-		pm_runtime_put_sync(dev);
-
+		pci_imx_ltssm_disable(dev);
 		pci_imx_clk_disable(dev);
 
 		imx_pcie_phy_pwr_dn(imx_pcie);
@@ -2151,9 +2206,6 @@ static int pci_imx_resume_noirq(struct device *dev)
 		regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
 				IMX6Q_GPR1_PCIE_TEST_PD, 0);
 	} else {
-		pm_runtime_get_sync(dev);
-
-		pci_imx_ltssm_disable(dev);
 		imx_pcie_assert_core_reset(imx_pcie);
 		imx_pcie_init_phy(imx_pcie);
 		ret = imx_pcie_deassert_core_reset(imx_pcie);
@@ -2499,6 +2551,29 @@ static int imx_pcie_probe(struct platform_device *pdev)
 			 ("fsl,imx6sx-iomuxc-gpr");
 	} else if (imx_pcie->variant == IMX8QM
 			|| imx_pcie->variant == IMX8QXP) {
+		imx_pcie->pcie_per = devm_clk_get(dev, "pcie_per");
+		if (IS_ERR(imx_pcie->pcie_per)) {
+			dev_err(dev, "pcie_per clock source missing or invalid\n");
+			return PTR_ERR(imx_pcie->pcie_per);
+		}
+		imx_pcie->phy_per = devm_clk_get(dev, "phy_per");
+		if (IS_ERR(imx_pcie->phy_per)) {
+			dev_err(dev, "failed to get per clock.\n");
+			return PTR_ERR(imx_pcie->phy_per);
+		}
+		imx_pcie->misc_per = devm_clk_get(dev, "misc_per");
+		if (IS_ERR(imx_pcie->misc_per)) {
+			dev_err(dev, "failed to get per clock.\n");
+			return PTR_ERR(imx_pcie->misc_per);
+		}
+		if (imx_pcie->variant == IMX8QM && imx_pcie->ctrl_id == 1) {
+			imx_pcie->pciex2_per = devm_clk_get(dev, "pciex2_per");
+			if (IS_ERR(imx_pcie->pciex2_per)) {
+				dev_err(dev, "can't get pciex2_per.\n");
+				return PTR_ERR(imx_pcie->pciex2_per);
+			}
+		}
+
 		imx_pcie->iomuxc_gpr =
 			 syscon_regmap_lookup_by_phandle(node, "hsio");
 		imx_pcie->pcie_inbound_axi = devm_clk_get(&pdev->dev,
diff --git a/drivers/regulator/bd71837-regulator.c b/drivers/regulator/bd71837-regulator.c
index 38c70726ef43..3d6a7f849116 100644
--- a/drivers/regulator/bd71837-regulator.c
+++ b/drivers/regulator/bd71837-regulator.c
@@ -174,10 +174,10 @@ static const struct regulator_linear_range bd71837_buck8_voltage_ranges[] = {
 
 /*
  * LDO1
- * 3.0 to 3.3V (100mV step)
+ * 1.6 to 1.9V (100mV step)
  */
 static const struct regulator_linear_range bd71837_ldo1_voltage_ranges[] = {
-	REGULATOR_LINEAR_RANGE(3000000, 0x00, 0x03, 100000),
+	REGULATOR_LINEAR_RANGE(1600000, 0x00, 0x03, 100000),
 };
 
 /*
@@ -351,7 +351,7 @@ static const struct regulator_desc bd71837_regulators[] = {
 		.owner = THIS_MODULE,
 	},
 	/*
-	 * LDO2 0.9V
+	 * LDO2 0.8V
 	 * Fixed voltage
 	 */
 	{
@@ -360,7 +360,7 @@ static const struct regulator_desc bd71837_regulators[] = {
 		.ops = &bd71837_fixed_regulator_ops,
 		.type = REGULATOR_VOLTAGE,
 		.n_voltages = BD71837_LDO2_VOLTAGE_NUM,
-		.min_uV = 900000,
+		.min_uV = 800000,
 		.enable_reg = BD71837_REG_LDO2_VOLT,
 		.enable_mask = LDO2_EN,
 		.enable_time = 1000,
diff --git a/drivers/staging/android/ion/ion_cma_heap.c b/drivers/staging/android/ion/ion_cma_heap.c
index fa3e4b7e0c9f..8589eff9b77f 100644
--- a/drivers/staging/android/ion/ion_cma_heap.c
+++ b/drivers/staging/android/ion/ion_cma_heap.c
@@ -22,6 +22,10 @@
 #include <linux/cma.h>
 #include <linux/scatterlist.h>
 #include <linux/highmem.h>
+#include <asm/cacheflush.h>
+#ifdef CONFIG_ARM
+#include <asm/outercache.h>
+#endif
 
 #include "ion.h"
 
@@ -55,17 +59,36 @@ static int ion_cma_allocate(struct ion_heap *heap, struct ion_buffer *buffer,
 	if (PageHighMem(pages)) {
 		unsigned long nr_clear_pages = nr_pages;
 		struct page *page = pages;
+#ifdef CONFIG_ARM
+		phys_addr_t base = __pfn_to_phys(page_to_pfn(pages));
+		phys_addr_t end = base + size;
+#endif
 
 		while (nr_clear_pages > 0) {
 			void *vaddr = kmap_atomic(page);
 
 			memset(vaddr, 0, PAGE_SIZE);
+#ifdef CONFIG_ARM
+			__cpuc_flush_dcache_area(vaddr,PAGE_SIZE);
+#else
+			__flush_dcache_area(vaddr,PAGE_SIZE);
+#endif
 			kunmap_atomic(vaddr);
 			page++;
 			nr_clear_pages--;
 		}
+#ifdef CONFIG_ARM
+		outer_flush_range(base, end);
+#endif
 	} else {
-		memset(page_address(pages), 0, size);
+		void *ptr = page_address(pages);
+		memset(ptr, 0, size);
+#ifdef CONFIG_ARM
+		__cpuc_flush_dcache_area(ptr,size);
+		outer_flush_range(__pa(ptr), __pa(ptr) + size);
+#else
+		__flush_dcache_area(ptr,size);
+#endif
 	}
 
 	table = kmalloc(sizeof(*table), GFP_KERNEL);
diff --git a/sound/soc/fsl/fsl_dsp.h b/sound/soc/fsl/fsl_dsp.h
index fb01a4985c48..c813d531a5bc 100644
--- a/sound/soc/fsl/fsl_dsp.h
+++ b/sound/soc/fsl/fsl_dsp.h
@@ -128,7 +128,7 @@ struct fsl_dsp {
 #define MSG_BUF_SIZE		8192
 #define INPUT_BUF_SIZE		4096
 #define OUTPUT_BUF_SIZE		16384
-#define DSP_CONFIG_SIZE    4096
+#define DSP_CONFIG_SIZE		8192
 
 void *memcpy_dsp(void *dest, const void *src, size_t count);
 void *memset_dsp(void *dest, int c, size_t count);