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authorStefan Agner <stefan.agner@toradex.com>2018-03-19 10:53:42 +0100
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2018-03-23 18:20:27 +0100
commit72928ca0214c76e4d7abadd6768295509a159bfa (patch)
treea12e5c2ead46cb5c43be36ea82dda2282eebdc7c
parentc6c1c2923ca1cac28b0fc7fe81385af4f68b5d5f (diff)
Revert "MLK-14498-2 ARM: imx7d: clk: select uart clock parent and rate"
This seems to limit possible baud rates due to lower input clock. Since Toradex modules do not use UART5/6 as console, do not set clock explicitly. This reverts commit 4f447cb8bccb1d40973e46478d7b11aa61961c90. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
-rw-r--r--drivers/clk/imx/clk-imx7d.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index eceb055..4741ca1 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -940,11 +940,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
/* set parent of SIM1 root clock */
imx_clk_set_parent(clks[IMX7D_SIM1_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_120M_CLK]);
- imx_clk_set_parent(clks[IMX7D_UART5_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]);
- imx_clk_set_rate(clks[IMX7D_UART5_ROOT_DIV], 80000000);
- imx_clk_set_parent(clks[IMX7D_UART6_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]);
- imx_clk_set_rate(clks[IMX7D_UART6_ROOT_DIV], 80000000);
-
imx_register_uart_clocks(uart_clks);
}
CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init);